VISHAY IRFBE20PBF Power MOSFET Owner’s Manual

: June 21, 2024
: VISHAY

Table of Contents

IRFBE20
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IRFBE20

www.vishay.com **** Vishay

Siliconix

Power MOSFET

TO-220AB

N-Channel MOSFET

PRODUCT SUMMARY

VDS (V)|

800

RDS(on) (Ω)|

VGS = 10 V

|

6.5

Qg (max.) (nC)|

38

Qgs (nC)|

5.0

Qgd (nC)|

21

Configuration|

Single

FEATURES

Dynamic dV/dt rating
Repetitive avalanche rated
Fast switching
Ease of paralleling
Simple drive requirements
Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

Note

This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details

DESCRIPTION

Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness.

The TO-220AB package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 W. The low thermal resistance and low package cost of the TO-220AB contribute to its wide acceptance throughout the industry.

ORDERING INFORMATION

Package| TO-220AB
Lead (Pb)-free| IRFBE20PbF
Lead (Pb)-free and halogen-free| IRFBE20PbF-BE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER|

SYMBOL

| LIMIT|

UNIT

Drain-source voltage|

VDS

| 800|

V

Gate-source voltage|

VGS

|

± 20

Continuous drain current| VGS at 10 V| TC = 25 °C|

ID

| 1.8|

A

TC = 100 °C|

1.2

Pulsed drain current a|

IDM

|

7.2

Linear derating factor| |

0.43

|

W/°C

Single pulse avalanche energy b|

EAS

| 180|

mJ

Repetitive avalanche current a|

IAR

| 1.8|

A

Repetitive avalanche energy a|

EAR

| 5.4|

mJ

Maximum power dissipation| TC = 25 °C|

PD

| 54|

W

Peak diode recovery dV/dt c|

dV/dt

| 2.0|

V/ns

Operating junction and storage temperature range|

TJ, Tstg

| -55 to +150|

°C

Soldering recommendations (peak temperature) d| For 10 s| |

300

Mounting torque| 6-32 or M3 screw| |

10

|

lbf · in

1.1

|

N · m

Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 50 V, starting TJ = 25 °C, L = 104 mH, Rg = 25 Ω, IAS = 1.8 A (see fig. 12)
c. ISD ≤ 1.8 A, dI/dt ≤ 80 A/μs, VDD ≤ 600, TJ ≤ 150 °C
d. 1.6 mm from case

THERMAL RESISTANCE RATINGS

PARAMETER|

SYMBOL

| TYP.| MAX.|

UNIT

Maximum junction-to-ambient|

RthJA

| –| 62|

°C/W

Case-to-sink, flat, greased surface|

RthCS

| 0.50|

–

Maximum junction-to-case (drain)|

RthJC

| –|

2.3

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER|

SYMBOL

| TEST CONDITIONS| MIN.| TYP.| MAX.|

UNIT

Static
Drain-source breakdown voltage|

VDS

| VGS = 0 V, ID = 250 μA|

800

| –| –|

V

VDS temperature coefficient|

ΔVDS/TJ

| Reference to 25 °C, ID = 1 mA|

–

| 0.98| –|

V/°C

Gate-source threshold voltage|

VGS(th)

| VDS = VGS, ID = 250 μA|

2.0

| –| 4.0|

V

Gate-source leakage|

IGSS

| VGS = ± 20 V|

–

| –| ± 100|

nA

Zero gate voltage drain current|

IDSS

| VDS = 800 V, VGS = 0 V|

–

| –| 100|

μA

VDS = 640 V, VGS = 0 V, TJ = 125 °C|

–

| –|

500

Drain-source on-state resistance|

RDS(on)

| VGS = 10 V| ID = 1.1 Ab|

–

| –| 6.5|

Ω

Forward transconductance|

gfs

| VDS = 100 V, ID = 1.1 Ab|

0.80

| –| –|

S

Dynamic
Input capacitance| Ciss| VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5|

–

| 530| –|

pF

Output capacitance| Coss|

–

| 150|

–

Reverse transfer capacitance| Crss|

–

| 90|

–

Total gate charge| Qg| VGS = 10 V| ID = 1.8 A, VDS = 400 V, see fig. 6 and 13b|

–

| –| 38|

nC

Gate-source charge| Qgs|

–

| –|

5.0

Gate-drain charge| Qgd|

–

| –|

21

Turn-on delay time| td(on)| VDD = 400 V, ID = 1.8 A,
Rg = 18 Ω, RD = 230 Ω, see fig. 10b|

–

| 8.2| –|

ns

Rise time| tr|

–

| 17|

–

Turn-off delay time| td(off)|

–

| 58|

–

Fall time| tf|

–

| 27|

–

Gate input resistance| Rg| f = 1 MHz, open drain| 0.6| –| 4.2|

Ω

Internal drain inductance| LD|

Between lead, 6 mm (0.25″) from package and center of die contact

|

–

| 4.5| –|

nH

Internal source inductance| LS|

–

| 7.5|

–

Drain-Source Body Diode Characteristics
Continuous source-drain diode current| IS|

MOSFET symbol showing the integral reverse p – n junction diode

|

–

| –| 1.8|

A

Pulsed diode forward current a| ISM|

–

| –|

7.2

Body diode voltage| VSD| TJ = 25 °C, IS = 1.8 A, VGS = 0 Vb|

–

| –| 1.4|

V

Body diode reverse recovery time| trr| TJ = 25 °C, IF = 1.8 A, dI/dt = 100 A/μsb|

–

| 380| 570|

ns

Body diode reverse recovery charge| Qrr|

–

| 0.94| 1.4|

μC

Forward turn-on time|

ton

| Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 – Typical Output Characteristics, T C = 25 °C

Fig. 2 – Typical Output Characteristics, T C = 150 °C

Fig. 3 – Typical Transfer Characteristics

Fig. 4 – Normalized On-Resistance vs. Temperature

Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 – Typical Source-Drain Diode Forward Voltage

Fig. 8 – Maximum Safe Operating Area

Fig. 9 – Maximum Drain Current vs. Case Temperature

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a – Switching Time Test Circuit

Fig. 10b – Switching Time Waveforms

Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case

Vary tp to obtain required IAS

Fig. 12a – Unclamped Inductive Test Circuit

Fig. 12b – Unclamped Inductive Waveforms

Fig. 12c – Maximum Avalanche Energy vs. Drain Current

Fig. 13a – Basic Gate Charge Waveform

Current regulator
Same type as D.U.T.
Current sampling resistors

Fig. 13b – Gate Charge Test Circuit

Peak Diode Recovery dV/dt Test Circuit

Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance current transformer
• dV/dt controlled by Rg
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
• D.U.T. – device under test

VISHAY IRFBE20PBF Power MOSFET - Fig. 14b

Driver gate drive
D.U.T. ISD waveform
Reverse recovery current
D.U.T. VDS waveform
Re-applied voltage
Inductor current
Body diode forward drop
Diode recovery dV/dt
Body diode forward current

Note
a. VGS = 5 V for logic level devices

Fig. 14 – For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91117.

S21-0868-Rev. C, 16-Aug-2021 Document Number: 91117

For technical questions, contact: hvm@vishay.com

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Revision: 01-Jan-2024 Document Number: 91000

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