VISHAY IRF730AS Power MOSFET Owner’s Manual

May 15, 2024
VISHAY

VISHAY IRF730AS Power MOSFET

Specifications

  • Brand: Vishay Siliconix
  • Product Type: Power MOSFET
  • Channel Type: N-Channel MOSFET
  • Package Types: I2PAK (TO-262), D2PAK (TO-263)
  • Maximum Drain-Source Voltage (VDS): 400V
  • Maximum On-Resistance (RDS(on)): 1.0 Ohm
  • Maximum Gate Charge (Qg): 22nC
  • Configuration: Single

Features

  • RoHS-compliant and non-RoHS-compliant options are available
  • Lead (Pb)-free and halogen-free

Applications
Typical SMPS Topologies

Ordering Information

Package: D2PAK (TO-263)
Lead (Pb)-free and halogen-free options available

Parameter Details

  • Drain-Source Voltage (VDS): 400V
  • Gate-Source Voltage (VGS): Operating at 10V
  • Continuous Drain Current (ID): Up to 300A
  • Maximum Power Dissipation: Refer to the datasheet for details

Thermal Resistance Ratings:

  • Maximum Junction-to-Ambient: 40°C/W
  • Maximum Junction-to-Case: 1.7°C/W

FAQs
Q: Are there RoHS-compliant options available?
A: Yes, the product comes in RoHS-compliant and non-RoHS-compliant versions. Please refer to the datasheet for specific details.

IRF730AS, SiHF730AS, IRF730AL, SiHF730AL

www.vishay.com

PRODUCT SUMMARY

VDS (V)| 400
RDS(on) max. (Ù)| VGS = 10 V| 1.0
Qg max. (nC)| 22
Qgs (nC)| 5.8
Qgd (nC)| 9.3
Configuration| Single

Power MOSFET

FEATURES

  • Low gate charge Qg results in simple drive requirement

  • Improved gate, avalanche and dynamic dV/dt ruggedness

  • Fully characterized capacitance and avalanche voltage and current

  • Effective Coss specified

  • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

Note
This datasheet provides information about parts that are RoHS-compliant and / or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information/tables in this datasheet for details

APPLICATIONS

  • Switch mode power supply (SMPS)
  • Uninterruptible power supply
  • High speed power switching

TYPICAL SMPS TOPOLOGIES

  • Single transistor flyback Xfmr. reset
  • Single transistor forward Xfmr. reset (both US line input only)

ORDERING INFORMATION

Package| D2PAK (TO-263)| D2PAK (TO-263)| D2PAK (TO-263)| I2PAK (TO-262)
Lead (Pb)-free and halogen-free| SiHF730AS-GE3| SiHF730ASTRL-GE3 a| SiHF730ASTRR-GE3 a| SiHF730AL-GE3
Lead (Pb)-free| IRF730ASPbF| IRF730ASTRLPbF a| –| –

Note
See device orientation.

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| LIMIT| UNIT
Drain-source voltage| VDS| 400| V
Gate-source voltage| VGS| ± 30
Continuous drain current| VGS at 10 V| TC = 25 °C| ID| 5.5|

A

TC = 100 °C| 3.5
Pulsed drain current a, e| IDM| 22
Linear derating factor| | 0.6| W/°C
Single pulse avalanche energy b, e| EAS| 290| mJ
Avalanche current a| IAR| 5.5| A
Repetiitive avalanche energy a| EAR| 7.4| mJ
Maximum power dissipation| TC = 25 °C| PD| 74| W
Peak diode recovery dV/dt c, e| dV/dt| 4.6| V/ns
Operating junction and storage temperature range| TJ, Tstg| -55 to +150| °C
Soldering recommendations (peak temperature) d| for 10 s| | 300

Notes

  • Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
  • Starting TJ = 25 °C, L = 19 mH, Rg = 25 Ω, IAS = 5.5 A (see fig. 12)
  • ISD ≤ 5.5 A, dI/dt ≤ 90 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
  • 1.6 mm from case
  • Uses IRF730A, SiHF730A data and test conditions

THERMAL RESISTANCE RATINGS

PARAMETER| SYMBOL| TYP.| MAX.| UNIT
Maximum junction-to-ambient (PCB mounted, steady-state) a| RthJA| –| 40|

°C/W

Maximum junction-to-case (drain)| RthJC| –| 1.7

Note

  • When mounted on 1″ square PCB (FR-4 or G-10 material)

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.| MAX.| UNIT
Static
Drain-source breakdown voltage| VDS| VGS = 0, ID = 250 μA| 400| –| –| V
VDS temperature coefficient| ÄVDS/TJ| Reference to 25 °C, ID = 1 mA d| –| 0.5| –| V/°C
Gate-source threshold voltage| VGS(th)| VDS = VGS, ID = 250 μA| 2.0| –| 4.5| V
Gate-Source Leakage| IGSS| VGS = ± 30 V| –| –| ± 100| nA
Zero Gate Voltage Drain Current| IDSS| VDS = 400 V, VGS = 0 V| –| –| 25| μA
VDS = 320 V, VGS = 0 V, TJ = 125 °C| –| –| 250
Drain-Source On-State Resistance| RDS(on)| VGS = 10 V| ID = 3.3 A b| –| –| 1.0| Ù
Forward Transconductance| gfs| VDS = 50 V, ID = 3.3 A d| 3.1| –| –| S
Dynamic
Input Capacitance| Ciss| VGS = 0 V, VDS = 25 V,

f = 1.0 MHz, see fig. 5d

| –| 600| –|

pF

Output Capacitance| Coss| –| 103| –
Reverse Transfer Capacitance| Crss| –| 4.0| –
Output Capacitance| Coss| VGS = 0 V| VDS = 1.0 V, f = 1.0 MHz| –| 890| –|
VDS = 320 V, f = 1.0 MHz| –| 30| –|
Effective Output Capacitance| Coss eff.| VDS = 0 V to 320 V c, d| –| 45| –|
Total Gate Charge| Qg|

VGS = 10 V

|

ID = 3.5 A, VDS = 320 V,

see fig. 6 and 13 b, d

| –| –| 22|

nC

Gate-Source Charge| Qgs| –| –| 5.8
Gate-Drain Charge| Qgd| –| –| 9.3
Turn-On Delay Time| td(on)|

VDD = 200 V, ID = 3.5 A,

Rg = 12 Ù, RD = 57 Ù, see fig. 10 b, d

| –| 10| –|

ns

Rise Time| tr| –| 22| –
Turn-Off Delay Time| td(off)| –| 20| –
Fall Time| tf| –| 16| –
Gate Input Resistance| Rg| f = 1 MHz, open drain| 2.7| –| 10.9| Ù
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current| IS| MOSFET symbol

D showing the integral reverse

Gp – n junction diodeS

| –| –| 5.5|

A

Pulsed Diode Forward Current a| ISM| –| –| 22
Body Diode Voltage| VSD| TJ = 25 °C, IS = 5.5 A, VGS = 0 V b| –| –| 1.6| V
Body Diode Reverse Recovery Time| trr| TJ = 25 °C, IF = 3.5 A, dI/dt = 100 A/μs b, d| –| 370| 550| ns
Body Diode Reverse Recovery Charge| Qrr| –| 1.6| 2.4| μC
Forward Turn-On Time| ton| Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Notes

  • Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
  • Pulse width ≤ 300 μs; duty cycle ≤ 2 %.
  • Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS.
  •  Uses IRF730A, SiHF730A data and test conditions.

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91046.

Package Information

Vishay Siliconix

TO-263AB (HIGH VOLTAGE)

| MILLIMETERS| INCHES| | | MILLIMETERS| INCHES
---|---|---|---|---|---|---
DIM.| MIN.| MAX.| MIN.| MAX.| DIM.| MIN.| MAX.| MIN.| MAX.
A| 4.06| 4.83| 0.160| 0.190| D1| 6.86| –| 0.270| –
A1| 0.00| 0.25| 0.000| 0.010| E| 9.65| 10.67| 0.380| 0.420
b| 0.51| 0.99| 0.020| 0.039| E1| 6.22| –| 0.245| –
b1| 0.51| 0.89| 0.020| 0.035| e| 2.54 BSC| 0.100 BSC
b2| 1.14| 1.78| 0.045| 0.070| H| 14.61| 15.88| 0.575| 0.625
b3| 1.14| 1.73| 0.045| 0.068| L| 1.78| 2.79| 0.070| 0.110
c| 0.38| 0.74| 0.015| 0.029| L1| –| 1.65| –| 0.066
c1| 0.38| 0.58| 0.015| 0.023| L2| –| 1.78| –| 0.070
c2| 1.14| 1.65| 0.045| 0.065| L3| 0.25 BSC| 0.010 BSC
D| 8.38| 9.65| 0.330| 0.380| L4| 4.78| 5.28| 0.188| 0.208
ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970

Notes

  1. Dimensioning and tolerancing per ASME Y14.5M-1994.
  2. Dimensions are shown in millimeters (inches).
  3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured at the outmost extremes of the plastic body at datum A.
  4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
  5. Dimension b1 and c1 apply to base metal only.
  6. Datum A and B to be determined at datum plane H.
  7. Outline conforms to JEDEC outline to TO-263AB.

I2PAK (TO-262) (HIGH VOLTAGE)

| MILLIMETERS| INCHES| | | MILLIMETERS| INCHES
---|---|---|---|---|---|---
DIM.| MIN.| MAX.| MIN.| MAX.| DIM.| MIN.| MAX.| MIN.| MAX.
A| 4.06| 4.83| 0.160| 0.190| D| 8.38| 9.65| 0.330| 0.380
A1| 2.03| 3.02| 0.080| 0.119| D1| 6.86| –| 0.270| –
b| 0.51| 0.99| 0.020| 0.039| E| 9.65| 10.67| 0.380| 0.420
b1| 0.51| 0.89| 0.020| 0.035| E1| 6.22| –| 0.245| –
b2| 1.14| 1.78| 0.045| 0.070| e| 2.54 BSC| 0.100 BSC
b3| 1.14| 1.73| 0.045| 0.068| L| 13.46| 14.10| 0.530| 0.555
c| 0.38| 0.74| 0.015| 0.029| L1| –| 1.65| –| 0.065
c1| 0.38| 0.58| 0.015| 0.023| L2| 3.56| 3.71| 0.140| 0.146
c2| 1.14| 1.65| 0.045| 0.065|
ECN: S-82442-Rev. A, 27-Oct-08 DWG: 5977

Notes

  1. Dimensioning and tolerancing per ASME Y14.5M-1994.
  2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost extremes of the plastic body.
  3. Thermal pad contour optional within dimension E, L1, D1, and E1.
  4. Dimension b1 and c1 apply to base metal only.

RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead

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