VISHAY SiS413DN P-Channel 30 V D-S MOSFET User Manual

**VISHAY SiS413DN P-Channel 30 V D-S MOSFET User Manual

**

FEATURES

• TrenchFET® Power MOSFET
• 100% Rg and UIS Tested
• Material categorization:
  For definitions of compliance please see
  www.vishay.com/doc?99912

APPLICATIONS

• Adaptor Switch
• Load Switch
• Power Management
• Mobile Computing

Ordering Information:
SiS413DN-T1-GE3 (Lead (Pb)-free and Halogen-free)
PRODUCT SUMMARY

V DS (V)| R DS(on) ( W ) Max.| I D (A)| (Typ.)
– 30| 0.0094 at VGS = – 10 V| – 18d| 35.4 nC
0.0132 at VGS = – 4.5 V| – 18d
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

Parameter| Symbol| Limit| Unit
Drain-Source Voltage| VDS| – 30| V
Gate-Source Voltage| VGS| ± 20
Continuous Drain Current (TJ = 150 °C)| TC = 25 °C| ID| – 18d|

A

TC = 70 °C| – 18d
TA = 25 °C| – 14.7a, b
TA = 70 °C| – 11.7a, b
Pulsed Drain Current (t = 300 µs)| IDM| – 70
Continuous Source-Drain Diode Current| TC = 25 °C| IS| – 18d
TA = 25 °C| – 3a, b
Avalanche Current| L = 0.1 mH| IAS| – 20
Single-Pulse Avalanche Energy| EAS| 20| mJ
Maximum Power Dissipation| TC = 25 °C| PD| 52| W
TC = 70 °C| 33
TA = 25 °C| 3.7a, b
TA = 70 °C| 2.4a, b
Operating Junction and Storage Temperature Range| TJ, Tstg| – 55 to 150| °C
Soldering Recommendations (Peak Temperature)e, f| | 260
THERMAL RESISTANCE RATINGS

Parameter| Symbol| Typical| Maximum| Unit
Maximum Junction-to-Ambienta, c| t £ 10 s| RthJA| 26| 33| °C/W
Maximum Junction-to-Case| Steady State| RthJC| 1.9| 2.4

Notes:
a. Surface mounted on 1″ x 1″ FR4 board.
b. t = 10 s.
c. Maximum under steady state conditions is 81 °C/W.
d. Package limited.
e. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection.
f. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.

Vishay Siliconix

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

Parameter| Symbol| Test Conditions| Min.| Typ.| Max.| Unit
Static
Drain-Source Breakdown Voltage| VDS| VGS = 0 V, ID = – 250 µA| – 30| | | V
VDS Temperature Coefficient| DVDS/TJ| ID = – 250 µA| | – 23| | mV/°C
VGS(th) Temperature Coefficient| DVGS(th)/TJ| | 4.6|
Gate-Source Threshold Voltage| VGS(th)| VDS = VGS, ID = – 250 µA| – 1| | – 2.5| V
Gate-Source Leakage| IGSS| VDS = 0 V, VGS = ± 20 V| | | ± 100| nA
Zero Gate Voltage Drain Current| IDSS| VDS = – 30 V, VGS = 0 V| | | – 1| µA
VDS = – 30 V, VGS = 0 V, TJ = 55 °C| | | – 5
On-State Drain Currenta| ID(on)| VDS ³ – 10 V, VGS = – 10 V| – 30| | | A
Drain-Source On-State Resistancea| RDS(on)| VGS = – 10 V, ID = – 15 A| | 0.0076| 0.0094| W
VGS = – 4.5 V, ID = – 10 A| | 0.0108| 0.0132
Forward Transconductancea| gfs| VDS = – 10 V, ID = – 15 A| | 50| | S
Dynamic b
Input Capacitance| Ciss| VDS = – 15 V, VGS = 0 V, f = 1 MHz| | 4280| | pF
Output Capacitance| Coss| | 427|
Reverse Transfer Capacitance| Crss| | 382|
Total Gate Charge| Qg| VDS = – 15 V, VGS = – 10 V, ID = – 10 A| | 73| 110|

nC

VDS = – 15 V, VGS = – 4.5 V, ID = – 10 A| | 35.4| 53
Gate-Source Charge| Qgs| | 10.6|
Gate-Drain Charge| Qgd| | 11.6|
Gate Resistance| Rg| f = 1 MHz| 0.4| 1.6| 3.2| W
Turn-On Delay Time| td(on)| VDD = – 15 V, RL = 1.5 WID @ – 10 A, VGEN = – 10 V, Rg = 1 W| | 11| 22|

ns

Rise Time| tr| | 11| 22
Turn-Off DelayTime| td(off)| | 45| 90
Fall Time| tf| | 8| 16
Turn-On Delay Time| td(on)| VDD = – 15 V, RL = 1.5 WID @ – 10 A, VGEN = – 4.5 V, Rg = 1 W| | 55| 100
Rise Time| tr| | 82| 150
Turn-Off DelayTime| td(off)| | 40| 80
Fall Time| tf| | 13| 26
Drain-Source Body Diode Characteristics
Continous Source-Drain Diode Current| IS| TC = 25 °C| | | – 18| A
Pulse Diode Forward Current| ISM| | | | – 70
Body Diode Voltage| VSD| IS = – 3 A, VGS = 0 V| | – 0.74| – 1.2| V
Body Diode Reverse Recovery Time| trr| IF = – 10 A, dI/dt = 100 A/µs, TJ = 25 °C| | 18| 36| ns
Body Diode Reverse Recovery Charge| Qrr| | 8| 16| nC
Reverse Recovery Fall Time| ta| | 7| | ns
Reverse Recovery Rise Time| tb| | 11|

Notes:
a. Pulse test; pulse width  300 µs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Output Characteristics

Transfer Characteristics

On-Resistance vs. Drain Current

Capacitance

Gate Charge

On Resistance vs. Junction Temperature

Source-Drain Diode Forward Voltage

On-Resistance vs. Gate-to-Source Voltage

Threshold Voltage

Single Pulse Power, Junction-to-Ambient

Safe Operating Area

Current Derating

Power, Junction-to-Case

**Power, Junction-to-Ambient

**

The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit

Normalized Thermal Transient Impedance, Junction-to-Ambient

Normalized Thermal Transient Impedance, Junction-to-Case

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?63262.

PowerPAK® 1212-8, (Single / Dual)

Notes

1. Inch will govern
2. imensions exclusive of mold gate burrs
3. Dimensions exclusive of mold flash and cutting burrs
   

Backside view of single pad

Backside view of dual pad

ECN: S16-2667-Rev. M, 09-Jan-17 DWG: 5882

PowerPAK® 1212 Mounting and Thermal Considerations

Johnson Zhao MOSFETs for switching applications are now available with die on resistances around 1 mΩ and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvious that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. The PowerPAK 1212-8 provides ultra-low thermal impedance in a small package that is ideal for space-constrained applications. In this application note, the PowerPAK 1212-8’s construction is described. Following this, mounting information is presented. Finally, thermal and electrical performance is discussed.

THE PowerPAK PACKAGE
The PowerPAK 1212-8 package **(Figure 1)

** is a derivative of PowerPAK SO-8. It utilizes the same packaging technology, maximizing the die area. The bottom of the die attach pad is exposed to provide a direct, low resistance thermal path to the substrate the device is mounted on. The PowerPAK 1212-8 thus translates the benefits of the PowerPAK SO-8 into a smaller package, with the same level of thermal performance. (Please refer to application note “PowerPAK SO-8 Mounting and Thermal Considerations.”)

The PowerPAK 1212-8 has a footprint area comparable to TSOP-6. It is over 40 % smaller than standard TSSOP-8. Its die capacity is more than twice the size of the standard TSOP-6’s. It has thermal performance an order of magnitude better than the SO-8, and 20 times better than TSSOP-8. Its thermal performance is better than all current SMT packages in the market. It will take the advantage of any PC board heat sink capability. Bringing the junction temperature down also increases the die efficiency by around 20 % compared with TSSOP-8. For applications where bigger packages are typically required solely for thermal consideration, the PowerPAK 1212-8 is a good option.

Both the single and dual PowerPAK 1212-8 utilize the same pin-outs as the single and dual PowerPAK SO-8. The low 1.05 mm PowerPAK height profile makes both versions an excellent choice for applications with space constraints.

PowerPAK 1212 SINGLE MOUNTING
To take the advantage of the single PowerPAK 1212-8’s thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 single in the index of this document.

In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package.

This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot- toambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance.

PowerPAK 1212 DUAL
To take the advantage of the dual PowerPAK 1212-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 10 mils. This matches the spacing of the two drain pads on the PowerPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot- toambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance.

REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a preconditioning test and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow temperature profile used, and the temperatures and time duration, are shown in Figures 2 and 3. For the lead (Pb)-free solder profile, see http://[www.vishay.com/](http://www.vishay.com/) doc?73257.

TABLE 1: EQIVALENT STEADY STATE PERFORMANCE

Package| SO-8| TSSOP-8| TSOP-8| PPAK 1212| PPAK SO-8
Configuration| Single| Dual| Single| Dual| Single| Dual| Single| Dual| Single| Dual
Thermal Resiatance RthJC(C/W)| 20| 40| 52| 83| 40| 90| 2.4| 5.5| 1.8| 5.5

THERMAL PERFORMANCE

Introduction

A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, Rθjc, or the junction to- foot thermal resistance, Rθjf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a  comparison of the PowerPAK 1212-8, PowerPAK SO-8, standard TSSOP-8 and SO-8 equivalent steady state performance.

By minimizing the junction-to-foot thermal resistance, the MOSFET die temperature is very close to the temperature of the PC board. Consider four devices mounted on a PC board with a board temperature of 45 °C (Figure 4).

Suppose each device is dissipating 2 W. Using the junction-to-foot thermal resistance characteristics of the PowerPAK 1212-8 and the other SMT packages, die temperatures are determined to be 49.8 °C for the PowerPAK 1212-8, 85 °C for the standard SO-8, 149 °C for standard TSSOP-8, and 125 °C for TSOP-6. This is a 4.8 °C rise above the board temperature for the PowerPAK 1212-8, and over 40 °C for other SMT packages. A 4.8 °C rise has minimal effect on rDS(ON) whereas a rise of over 40 °C will cause an increase in rDS(ON) as high as 20 %.

Spreading Copper

Designers add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper. Figure 5
and Figure 6


show the thermal resistance of a PowerPAK 1212-8 single and dual devices mounted on a 2-in. x 2-in., four-layer FR-4 PC boards. The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.2 to 0.3 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No significant effect was observed.

Vishay Siliconi

CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK 1212-8 uses the same packaging technology and has been shown to have the same level of thermal performance while having a footprint that is more than 40 % smaller than the standard TSSOP-8. Recommended PowerPAK 1212-8 land patterns are provided to aid in PC board layout for designs using this new package.

The PowerPAK 1212-8 combines small size with attractive thermal characteristics. By minimizing the thermal rise above the board temperature, PowerPAK simplifies thermal design considerations, allows the device to run cooler, keeps rDS(ON) low, and permits the device to handle more current than a same- or larger-size MOSFET die in the standard TSSOP-8 or SO-8 packages.

RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Single
Recommended Minimum Pads Dimensions in Inches/(mm)

Disclaimer

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References

• Vishay Intertechnology: Passives & Discrete Semiconductors
• Vishay Intertechnology: Passives & Discrete Semiconductors
• SiS413DN MOSFETs | Vishay

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