VISHAY SiS468DN Siliconix Discrete Semiconductor User Guide

VISHAY SiS468DN Siliconix Discrete Semiconductor

Product Specifications

• Brand: Vishay Siliconix
• Model: SiS468DN
• Type: N-Channel MOSFET
• Drain-Source Voltage (VDS): 80V
• RDS(on) max. at VGS = 10V: 0.0195 ohms
• RDS(on) max. at VGS = 7.5V: 0.0210 ohms
• RDS(on) max. at VGS = 4.5V: 0.0320 ohms
• Gate Charge (Qg): 8.7nC (typical)
• Continuous Drain Current (ID): 30A
• Configuration: Single

Product Features

• N-Channel MOSFET
• Lead (Pb)-free and halogen-free package

Thermal Resistance Ratings

• Maximum Junction-to-Ambient: 26°C/W
• Maximum Junction-to-Case: 1.9°C/W (steady state)

Product Usage Instructions

Installation

1. Ensure the operating junction temperature range is between -55°C to +150°C.
2. Mount the MOSFET on a 1 x 1 FR4 board for optimal thermal performance.
3. Refer to the solder profile provided by Vishay for peak temperature recommendations.

Operation

1. Apply a gate-source voltage within the specified range for the desired drain-source current.
2. Monitor the drain-source voltage to stay within the 80V limit.
3. Avoid exceeding the continuous drain current rating of 30A.

Frequently Asked Questions (FAQ)

• Q: What is the maximum drain-source breakdown voltage of the SiS468DN MOSFET?
  A: The maximum drain-source breakdown voltage is 80V.

• Q: What is the typical gate charge for this MOSFET?
  A: The typical gate charge is 8.7nC.

• Q: Can manual soldering with a soldering iron be used for leadless components?
  A: Manual soldering with a soldering iron is not recommended for leadless components like the PowerPAK 1212-8.

PowerPAK® 1212-8 Single

FEATURES

• TrenchFET® power MOSFET
• 100 % Rg and UIS tested
• Capable of operating with 5 V gate drive
• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

APPLICATIONS

• Telecom bricks
• Primary side switch
• Synchronous rectification

PRODUCT SUMMARY

PRODUCT SUMMARY

VDS (V)| 80
RDS(on) max. (W) at VGS = 10 V| 0.0195
RDS(on) max. (W) at VGS = 7.5 V| 0.0210
RDS(on) max. (W) at VGS = 4.5 V| 0.0320
Qg typ. (nC)| 8.7
ID (A) f, g| 30
Configuration| Single
ORDERING INFORMATION

Package| PowerPAK® 1212-8
Lead (Pb)-free and halogen-free| SiS468DN-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| LIMIT| UNIT
Drain-source voltage| VDS| 80| V
Gate-source voltage| VGS| ± 20

Continuous drain current (TJ = 150 °C)

| TC = 25 °C|

ID

| 30 g|

A

TC = 70 °C| 29.2
TA = 25 °C| 9.8 a, b
TA = 70 °C| 7.8 a, b
Pulsed drain current (t = 300 μs)| IDM| 60
Continuous source-Drain diode current| TC = 25 °C| IS| 30 g
TA = 25 °C| 3.1 a, b
Single pulse avalanche current| L = 0.1 mH| IAS| 10
Single pulse avalanche energy| EAS| 5| mJ

Maximum power dissipation

| TC = 25 °C|

PD

| 52|

W

TC = 70 °C| 33.3
TA = 25 °C| 3.7 a, b
TA = 70 °C| 2.4 a, b
Operating junction and storage temperature range| TJ, Tstg| -55 to +150| °C
Soldering recommendations (peak temperature) c, d| | 260
THERMAL RESISTANCE RATINGS

PARAMETER| SYMBOL| TYPICAL| MAXIMUM| UNIT
Maximum junction-to-ambient a, e| t £ 10 s| RthJA| 26| 33| °C/W
Maximum junction-to-case (drain)| Steady-state| RthJC| 1.9| 2.4

THERMAL RESISTANCE RATINGS

Notes

• Surface mounted on 1″ x 1″ FR4 board
• t = 10 s
• See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom-side solder interconnection
• Rework conditions: Manual soldering with a soldering iron is not recommended for leadless components
• Maximum under steady-state conditions is 81 °C/W
• Based on TC = 25 °C
• Package limited

SPECIFICATIONS

(TJ = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.| MAX.| UNIT
---|---|---|---|---|---|---
Static
Drain-source breakdown voltage| VDS| VGS = 0 V, ID = 250 μA| 80| –| –| V
VDS temperature coefficient| DVDS/TJ| ID = 250 μA| –| 36| –| mV/°C
VGS(th) temperature coefficient| DVGS(th)/TJ| –| -5.5| –
Gate-source threshold voltage| VGS(th)| VDS = VGS, ID = 250 μA| 1.5| –| 3| V
Gate-source leakage| IGSS| VDS = 0 V, VGS = ± 20 V| –| –| ± 100| nA
Zero gate voltage drain current| IDSS| VDS = 80 V, VGS = 0 V| –| –| 1| μA
VDS = 80 V, VGS = 0 V, TJ = 55 °C| –| –| 10
On-state drain current a| ID(on)| VDS ³ 5 V, VGS = 10 V| 20| –| –| A

Drain-source on-state resistance a

|

RDS(on)

| VGS = 10 V, ID = 10 A| –| 0.0160| 0.0195|

W

VGS = 7.5 V, ID = 7 A| –| 0.0170| 0.0210
VGS = 4.5 V, ID = 5 A| –| 0.0230| 0.0320
Forward transconductance a| gfs| VDS = 15 V, ID = 10 A| –| 25| –| S
Dynamic b
Input capacitance| Ciss|

VDS = 40 V, VGS = 0 V, f = 1 MHz

| –| 780| –|

pF

Output capacitance| Coss| –| 400| –
Reverse transfer capacitance| Crss| –| 39| –

Total gate charge

|

Qg

| VDS = 40 V, VGS = 10 V, ID = 10 A| –| 18.1| 28|

nC

VDS = 40 V, VGS = 7.5 V, ID = 10 A| –| 13.8| 21

VDS = 40 V, VGS = 4.5 V, ID = 10 A

| –| 8.7| 14
Gate-source charge| Qgs| –| 2.6| –
Gate-drain charge| Qgd| –| 3.9| –
Output charge| Qoss| VDS = 40 V, VGS = 0 V| –| 23| 35
Gate resistance| Rg| f = 1 MHz| 0.2| 1| 2| W
Turn-on delay time| td(on)|

VDD = 40 V, RL = 4 W,

ID @ 10 A, VGEN = 7.5 V, Rg = 1 W

| –| 9| 18|

ns

Rise time| tr| –| 11| 22
Turn-off delay time| td(off)| –| 15| 30
Fall time| tf| –| 9| 18
Turn-on delay time| td(on)|

VDD = 40 V, RL = 4 W,

ID @ 10 A, VGEN = 10 V, Rg = 1 W

| –| 8| 16
Rise time| tr| –| 10| 20
Turn-off delay time| td(off)| –| 15| 30
Fall time| tf| –| 9| 18
Drain-Source Body Diode Characteristics
Continuous source-drain diode current| IS| TC = 25 °C| –| –| 30| A
Pulse diode forward current| ISM| | –| –| 60
Body diode voltage| VSD| IS = 4 A, VGS = 0 V| –| 0.78| 1.2| V
Body diode reverse recovery time| trr|

IF = 10 A, di/dt = 100 A/μs, TJ = 25 °C

| –| 31| 60| ns
Body diode reverse recovery charge| Qrr| –| 25| 50| nC
Reverse recovery fall time| ta| –| 15.5| –| ns
Reverse recovery rise time| tb| –| 15.5| –

Notes

• Pulse test; pulse width 300 μs, duty cycle 2 %
• Guaranteed by design, not subject to production testing

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and the functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TYPICAL CHARACTERISTICS

(25 °C, unless otherwise noted)

Note
The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating when this rating falls below the package limit

Package Information

PowerPAK® 1212-8, (Single / Dual)

ECN: S16-2667-Rev. M, 09-Jan-17 DWG: 5882

Mounting and Thermal Considerations

Johnson Zhao
MOSFETs for switching applications are now available with die-on resistances around 1 mΩ and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvious that the degradation of a high-performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. The PowerPAK 1212-8 provides ultra-low thermal impedance in a small package that is ideal for space-constrained applications. In this application note, the PowerPAK 1212-8’s construction is described. Following this, mounting information is presented. Finally, thermal and electrical performance is discussed.

THE PowerPAK PACKAGE
The PowerPAK 1212-8 package (Figure 1) is a derivative of PowerPAK SO-8. It utilizes the same packaging technology, maximizing the die area. The bottom of the die attach pad is exposed to provide a direct, low-resistance thermal path to the substrate the device is mounted on. The PowerPAK 1212-8 thus translates the benefits of the PowerPAK SO-8 into a smaller package, with the same level of thermal performance. (Please refer to application note “PowerPAK SO-8 Mounting and Thermal Considerations.”)

• The PowerPAK 1212-8 has a footprint area comparable to TSOP-6. It is over 40 % smaller than standard
• TSSOP-8. Its die capacity is more than twice the size of the standard TSOP-6’s. It has thermal performance an order of magnitude better than the SO-8, and 20 times better than TSSOP-8. Its thermal performance is better than all current SMT packages in the market. It will take advantage of any PC board heat sink capability. Bringing the junction temperature down also increases the die efficiency by around 20 % compared with TSSOP-8. For applications where bigger packages are typically required solely for thermal consideration, the PowerPAK 1212-8 is a good option.
• Both the single and dual PowerPAK 1212-8 utilizes the same pin-outs as the single and dual PowerPAK SO-8.
• The low 1.05 mm PowerPAK height profile makes both versions an excellent choice for applications with space constraints.

PowerPAK 1212 SINGLE MOUNTING

• To take advantage of the single PowerPAK 1212-8’s thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 single in the index of this document.
• In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to ambient thermal resistance.
• Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance.

PowerPAK 1212 DUAL

• To take the advantage of the dual PowerPAK 1212-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826,
• Recommended Minimum Pad Patterns With Outline
• Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 dual in the index of this document.
• The gap between the two drain pads is 10 mils. This matches the spacing of the two drain pads on the PowerPAK 1212-8 dual package.
• This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient.
  Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to ambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance.

REFLOW SOLDERING

Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a preconditioning test and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow temperature profile used, and the temperatures and time duration, are shown in Figures 2 and 3. For the lead (Pb)-free solder profile, see http://www.vishay.com/doc?73257.

EQUIVALENT STEADY STATE PERFORMANCE

THERMAL PERFORMANCE

Introduction

A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, Rθjc, or the junction to- foot thermal resistance, Rθjf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the PowerPAK 1212-8, PowerPAK SO-8, standard TSSOP-8 and SO-8 equivalent steady state performance.
By minimizing the junction-to-foot thermal resistance, the MOSFET die temperature is very close to the temperature of the PC board. Consider four devices mounted on a PC board with a board temperature of 45 °C (Figure 4). Suppose each device is dissipating 2 W. Using the junction- to-foot thermal resistance characteristics of the PowerPAK 1212-8 and the other SMT packages, die temperatures are determined to be 49.8 °C for the PowerPAK 1212-8, 85 °C for the standard SO-8, 149 °C for standard TSSOP-8, and 125 °C for TSOP-6. This is a 4.8 °C rise above the board temperature for the Power- PAK 1212-8, and over 40 °C for other SMT packages. A 4.8 °C rise has minimal effect on rDS(ON) whereas a rise of over 40 °C will cause an increase in rDS(ON) as high as 20 %.

Spreading Copper

• Designers add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper.
  Figure 5 and Figure 6 show the thermal resistance of a PowerPAK 1212-8 single and dual devices mounted on a 2-in. x 2-in., four-layer FR-4 PC boards. The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications.

• The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.2 to 0.3 square inches of spreading copper gives no additional thermal performance improvement.

• A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No significant effect was observed.

Vishay Siliconix

CONCLUSIONS

As a derivative of the PowerPAK SO-8, the PowerPAK 1212-8 uses the same packaging technology and has been shown to have the same level of thermal performance while having a footprint that is more than 40 % smaller than the standard TSSOP-8.
Recommended PowerPAK 1212-8 land patterns are provided to aid in PC board layout for designs using this new package.
The PowerPAK 1212-8 combines small size with attractive thermal characteristics. By minimizing the thermal rise above the board temperature, PowerPAK simplifies thermal design considerations, allows the device to run cooler, keeps rDS(ON) low, and permits the device to handle more current than a same- or larger-size MOSFET die in the standard TSSOP-8 or SO-8 packages.

RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Single

Disclaimer

• ALL PRODUCTS, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
• Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.
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• Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts.
• Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.
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© 2023 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 01-Jan-2023
Document Number: 91000
www.vishay.com

References

• applications.no
• SiS468DN MOSFETs | Vishay

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