VISHAY IRF740LC Power Mosfet Owner’s Manual

: June 16, 2024
: VISHAY

Table of Contents

IRF740LC
- Power MOSFET
- References
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IRF740LC

www.vishay.com Vishay Siliconix

Power MOSFET

TO-220AB

N-Channel MOSFET

PRODUCT SUMMARY

VDS (V)|

400

RDS(on) (Ω)|

VGS = 10 V

|

0.55

Qg (max.) (nC)|

39

Qgs (nC)|

10

Qgd (nC)|

19

Configuration|

Single

FEATURES

Ultra low gate charge
Reduced gate drive requirement
Enhanced 30 V VGS rating
Reduced Ciss, Coss, Crss
Extremely high frequency operation
Repetitive avalanche rated
Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

Note

This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details

DESCRIPTION

This new series of low charge Power MOSFETs achieve significantly lower gate charge over conventional MOSFETs. Utilizing the new LCDMOS technology, the device improvements are achieved without added product cost, allowing for reduced gate drive requirements and total system savings. In addition, reduced switching losses and improved efficiency are achievable in a variety of high frequency applications. Frequencies of a few MHz at high current are possible using the new Low Charge MOSFETs.

These device improvements combined with the proven ruggedness and reliability that are characteristic of Power MOSFETs ofter the designer a new standard in power transistors for switching applications.

ORDERING INFORMATION

Package| TO-220AB
Lead (Pb)-free| IRF740LCPbF
Lead (Pb)-free and halogen-free| IRF740LCPbF-BE3

ABSOLUTE MAXIMUM RATINGS

(TC = 25 °C, unless otherwise noted)

PARAMETER|

SYMBOL

| LIMIT|

UNIT

Drain-source voltage|

VDS

| 400|

V

Gate-source voltage|

VGS

|

± 30

Continuous drain current| VGS at 10 V| TC = 25 °C|

ID

| 10|

A

TC = 100 °C|

6.3

Pulsed drain current a|

IDM

|

32

Linear derating factor| |

1.0

|

W/°C

Single pulse avalanche energy b|

EAS

| 520|

mJ

Repetitive avalanche current a|

IAR

| 10|

A

Repetitive avalanche energy a|

EAR

| 13|

mJ

Maximum power dissipation| TC = 25 °C|

PD

| 125|

W

Peak diode recovery dV/dt c|

dV/dt

| 4.0|

V/ns

Operating junction and storage temperature range|

TJ, Tstg

| -55 to +150|

°C

Soldering recommendations (peak temperature) d| For 10 s| |

300d

Mounting torque| 6-32 or M3 screw| |

10

|

lbf · in

1.1

|

N · m

Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 50 V, starting TJ = 25 °C, L = 9.1 mH, Rg = 25 Ω, IAS = 10 A (see fig. 12)
c. ISD ≤ 10 A, dI/dt ≤ 120 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case

THERMAL RESISTANCE RATINGS

PARAMETER|

SYMBOL

| TYP.| MAX.|

UNIT

Maximum junction-to-ambient|

RthJA

| –| 62|

°C/W

Case-to-sink, flat, greased surface|

RthCS

| 0.50|

–

Maximum junction-to-case (drain)|

RthJC

| –|

1.0

SPECIFICATIONS

(TJ = 25 °C, unless otherwise noted)

PARAMETER|

SYMBOL

| TEST CONDITIONS| MIN.| TYP.| MAX.|

UNIT

Static
Drain-source breakdown voltage|

VDS

| VGS = 0 V, ID = 250 μA| 400| –| –|

V

VDS temperature coefficient |

ΔVDS/TJ

| Reference to 25 °C, ID = 1 mA| –| 0.76| –|

V/°C

Gate-source threshold voltage|

VGS(th)

| VDS = VGS, ID = 250 μA| 2.0| –| 4.0|

V

Gate-source leakage |

IGSS

| VGS = ± 20 V| –| –| ± 100|

nA

Zero gate voltage drain current |

IDSS

|

VDS = 400 V, VGS = 0 V

|

–

| –| 25|

μA

VDS = 320 V, VGS = 0 V, TJ = 125 °C|

–

| –|

250

Drain-source on-state resistance|

RDS(on)

| VGS = 10 V| ID = 6.0 Ab|

–

| –| 0.55|

Ω

Forward transconductance|

gfs

| VDS = 50 V, ID = 6.0 Ab|

3.0

| –| –|

S

Dynamic
Input capacitance|

Ciss

| VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5|

–

| 1100| –|

pF

Output capacitance|

Coss

|

–

| 190|

–

Reverse transfer capacitance|

Crss

|

–

| 18|

–

Total gate charge|

Qg

| VGS = 10 V| ID = 10 A, VDS = 320 V, see fig. 6 and 13b|

–

| –| 39|

nC

Gate-source charge|

Qgs

|

–

| –|

10

Gate-drain charge|

Qgd

|

–

| –|

19

Turn-on delay time|

td(on)

| VDD = 200 V, ID = 10 A,
Rg = 9.1 Ω, RD = 20 Ω, see fig. 10b|

–

| 11| –|

ns

Rise time|

tr

|

–

| 31|

–

Turn-off delay time|

td(off)

|

–

| 25|

–

Fall time|

tf

|

–

| 20|

–

Internal drain inductance|

LD

|

Between lead, 6 mm (0.25″) from package and center of die contact

|

–

| 4.5| –|

nH

Internal source inductance|

LS

|

–

| 7.5|

–

Drain-Source Body Diode Characteristics
Continuous source-drain diode current|

IS

| MOSFET symbol showing the integral reverse p – n junction diode|

–

| –| 10|

A

Pulsed diode forward current a|

ISM

|

–

| –|

32

Body diode voltage|

VSD

| TJ = 25 °C, IS = 10 A, VGS = 0 Vb|

–

| –| 2.0|

V

Body diode reverse recovery time|

trr

| TJ = 25 °C, IF = 10 A, dI/dt = 100 A/μsb|

–

| 380| 570|

ns

Body diode reverse recovery charge|

Qrr

|

–

| 2.8| 4.2|

μC

Forward turn-on time|

ton

| Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

20 µs Pulse Width
TC = 25 °C

Fig. 1 – Typical Output Characteristics, T C = 25 °C

20 µs Pulse Width
TC = 150 °C

Fig. 1 – Typical Output Characteristics, T C = 150 °C

20 µs Pulse Width
VDS = 50 V

Fig. 2 – Typical Transfer Characteristics

ID = 10 A
VGS = 10 V

Fig. 3 – Normalized On-Resistance vs. Temperature

VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd

Fig. 4 – Typical Capacitance vs. Drain-to-Source Voltage

ID = 11 A
VDS = 320 V
VDS = 200 V
VDS = 80 V
For test circuit see figure 13

Fig. 5 – Typical Gate Charge vs. Gate-to-Source Voltage

VGS = 0 V

Fig. 6 – Typical Source-Drain Diode Forward Voltage

Operation in this area limited by RDS(on)
TC = 25 °C
TJ = 150 °C
Single Pulse

Fig. 7 – Maximum Safe Operating Area

Fig. 9 – Maximum Drain Current vs. Case Temperature

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a – Switching Time Test Circuit

Fig. 10b – Switching Time Waveforms

Single Pulse
(Thermal Response)
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC

Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case

Vary tp to obtain required IAS

Fig. 12a – Unclamped Inductive Test Circuit

Fig. 12b – Unclamped Inductive Waveforms

Fig. 12c – Maximum Avalanche Energy vs. Drain Current

Charge

Fig. 13a – Basic Gate Charge Waveform

Current regulator
Same type as D.U.T.
Current sampling resistors

Fig. 13b – Gate Charge Test Circuit

Peak Diode Recovery dV/dt Test Circuit

Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance current transformer
• dV/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
• D.U.T. – device under test
Driver gate drive
D.U.T. ISD waveform
Reverse recovery current
D.U.T. VDS waveform
Re-applied voltage
Inductor current
Body diode forward drop
Diode recovery dV/dt
Body diode forward current

VGS = 5 V for logic level devices

Fig. 14 – For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91053.

S21-0853-Rev. C, 16-Aug-2021 Document Number: 91053

For technical questions, contact: hvm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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Revision: 01-Jan-2023 Document Number: 91000

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