VISHAY IRLR110 Power Mosfet Instruction Manual
- June 4, 2024
- VISHAY
Table of Contents
- VISHAY IRLR110 Power Mosfet Instruction Manual
- Power MOSFET
- DESCRIPTION
- Note
- Notes
- Notes
- TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
- Peak Diode Recovery dV/dt Test Circuit
- TO-252AA Case Outline
- VERSION 2: FACILITY CODE = N
- Notes
- Case Outline for TO-251AA (High Voltage)
- Notes
- OPTION 2: FACILITY CODE = N
- Notes
- RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
- Disclaimer
- Read More About This Manual & Download PDF:
- References
- Read User Manual Online (PDF format)
- Download This Manual (PDF format)
VISHAY IRLR110 Power Mosfet Instruction Manual
Power MOSFET
FEATURES
- Dynamic dV/dt rating
- Repetitive avalanche rated
- Surface-mount (IRLR110, SiHLR110)
- Straight lead (IRLU110, SiHLU110)
- Available in tape and reel
- Logic-level gate drive
- RDS(on) specified at VGS = 4 V and 5 V
- Material categorization: for definitions of compliance please see www.vishay.com/doc?99912
DESCRIPTION
Third generation ower MOSFETs from Vishay provide the designer with the best
combination of fast switching, ruggedized device design, low on-resistance and
cost-effectiveness.
The DPAK is designed for surface mounting using vapor phase, infrared, or wave
soldering techniques. The straight lead version (IRLU, SiHLU series) is for
through-hole
mounting applications. Power dissipation levels up to 1.5 W are possible in
typical surface-mount applications.
PRODUCT SUMMARY
VDS (V)| 100
RDS(on) (L)| VGS = 5.0 V| 0.54
Qg (Max.) (nC)| 6.1
Qgs (nC)| 2.0
Qgd (nC)| 3.3
Configuration| Single
ORDERING INFORMATION
Package| DPAK (TO-252)| DPAK (TO-252)| DPAK (TO-252)| IPAK (TO-251)
Lead (Pb)-free and halogen-free| SiHLR110-GE3| SiHLR110TR-GE3| –| SiHLU110-GE3
IRLR110PbF-BE3| IRLR110TRPbF-BE3| –| –
Lead (Pb)-free| IRLR110PbF| IRLR110TRPbFa| IRLR110TRLPbF| IRLU110PbF
Note
- See device orientation
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER| SYMBOL| LIMIT| UNIT
Drain-source voltage| VDS| 100| V
Gate-source voltage| VGS| ± 10
Continuous drain current| VGS at 5 V| TC = 25 °C| ID| 4.3|
A
TC = 100 °C| 2.7
Pulsed drain current a| IDM| 17
Linear derating factor| | 0.20| W/°C
Linear derating factor (PCB mount) e| 0.020
Single pulse avalanche energy b| EAS| 100| mJ
Repetitive avalanche current a| IAR| 4.3| A
Repetitive avalanche energy a| EAR| 2.5| mJ
Maximum power dissipation| TC = 25 °C| PD| 25| W
Maximum power dissipation (PCB mount) e| TA = 25 °C| 2.5
Peak diode recovery dV/dt c| dV/dt| 5.5| V/ns
Operating junction and storage temperature range| TJ, Tstg| -55 to +150| °C
Soldering recommendations (peak temperature) d| For 10 s| | 260
Notes
- Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
- VDD = 25 V, starting TJ = 25 °C, L = 8.1 mH, Rg = 25 Ω, IAS = 4.3 A (see fig. 12)
- ISD ≤ 5.6 A, dI/dt ≤ 140 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
- 1.6 mm from case
- When mounted on 1″ square PCB (FR-4 or G-10 material)
THERMAL RESISTANCE RATINGS
PARAMETER| SYMBOL| MIN.| TYP.| MAX.| UNIT
Maximum junction-to-ambient| RthJA| –| –| 110|
°C/W
Maximum junction-to-ambient (PCB mount) a| RthJA| –| –| 50
Maximum junction-to-case (drain)| RthJC| –| –| 5.0
Note
- When mounted on 1″ square PCB (FR-4 or G-10 material)
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.|
MAX.| UNIT
Static
Drain-source breakdown voltage| VDS| VGS = 0 V, ID = 250 μA| 100| –| –| V
VDS temperature coefficient| DVDS/TJ| Reference to 25 °C, ID = 1 mA| –| 0.12|
–| V/°C
Gate-source threshold voltage| VGS(th)| VDS = VGS, ID = – 250 μA| 1.0| –| 2.0|
V
Gate-source leakage| IGSS| VGS = ± 10 V| –| –| ± 100| nA
Zero gate voltage drain current| IDSS| VDS = 100 V, VGS = 0 V| –| –| 25| μA
VDS = 80 V, VGS = 0 V, TJ = 125 °C| –| –| 250
Drain-source on-state resistance| RDS(on)| VGS = 5.0 V| ID = 2.6 Ab| –| –|
0.54| L
VGS = 4.0 V| ID = 2.2 Ab| –| –| 0.76
Forward transconductance| gfs| VDS = 50 V, ID = 2.6 A| 2.3| –| –| S
Dynamic
Input capacitance| Ciss| VGS = 0 V, VDS = 25 V,
f = 1.0 MHz, see fig. 5
| –| 250| –|
pF
Output capacitance| Coss| –| 80| –
Reverse transfer capacitance| Crss| –| 15| –
Total gate charge| Qg|
VGS = 5.0 V
|
ID = 5.6 A, VDS = 80 V,
see fig. 6 and 13b
| –| –| 6.1|
nC
Gate-source charge| Qgs| –| –| 2.0
Gate-drain charge| Qgd| –| –| 3.3
Turn-on delay time| td(on)|
VDD = 50 V, ID = 5.6 A,
Rg = 12 L, RD = 8.4 L, see fig. 10b
| –| 9.3| –|
ns
Rise time| tr| –| 47| –
Turn-off delay time| td(off)| –| 16| –
Fall time| tf| –| 17| –
Internal drain inductance| LD| Between lead,
6 mm (0.25″) from package and center of die contactc
|
G
|
D
S
| | –| 4.5| –|
nH
Internal source inductance| LS| –| 7.5| –
Drain-Source Body Diode Characteristics
Continuous source-drain diode current| IS| MOSFET symbol showing the integral
reverse
p – n junction diode
|
G
| |
D
S
| –| –| 4.3|
A
Pulsed diode forward current a| ISM| –| –| 17
Body diode voltage| VSD| TJ = 25 °C, IS =4.3 A, VGS = 0 Vb| –| –| 2.5| V
Body diode reverse recovery time| trr| TJ = 25 °C, IF = 5.6 A, dI/dt = 100
A/μsb| –| 100| 130| ns
Body diode reverse recovery charge| Qrr| –| 0.50| 0.65| μC
Forward turn-on time| ton| Intrinsic turn-on time is negligible (turn-on is
dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see
fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 – Typical Output Characteristics, TC = 25 °C
Fig. 2 – Typical Transfer Characteristics
Fig. 3 – Typical Output Characteristics, TC = 150 °C
Fig. 4 – Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 – Typical Source-Drain Diode Forward Voltage
Fig. 5 – Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 – Maximum Safe Operating Area
Fig. 8 – Maximum Drain Current vs. Case Temperature
Fig. 10a – Switching Time Test Circuit
Fig. 10b – Switching Time Waveforms
Fig. 9 – Maximum Effective Transient Thermal Impedance, Junction-to- Case
Fig. 12b – Unclamped Inductive Waveforms
Fig. 12c – Maximum Avalanche Energy vs. Drain Curre nt
Fig. 13a – Basic Gate Charge Waveform
Fig. 13b – Gate Charge Test Circuit
Peak Diode Recovery dV/dt Test Circuit
Fig. 10 – For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be
manufactured at one of several qualified locations. Reliability data for
Silicon
Technology and Package Reliability represent a composite of all qualified
locations. For related documents such as package/tape drawings, part marking,
and reliability data, see www.vishay.com/ppg?91323
TO-252AA Case Outline
MILLIMETERS | |
---|---|
DIM. | MIN. |
A | 2.18 |
A1 | – |
b | 0.64 |
b2 | 0.76 |
b3 | 4.95 |
C | 0.46 |
C2 | 0.46 |
D | 5.97 |
D1 | 4.10 |
E | 6.35 |
E1 | 4.32 |
H | 9.40 |
e | 2.28 BSC |
e1 | 4.56 BSC |
L | 1.40 |
L3 | 0.89 |
L4 | – |
L5 | 1.01 |
Note
- Dimension L3 is for reference only
VERSION 2: FACILITY CODE = N
MILLIMETERS | |
---|---|
DIM. | MIN. |
A | 2.18 |
A1 | – |
b | 0.65 |
b1 | 0.64 |
b2 | 0.76 |
b3 | 4.95 |
c | 0.46 |
c1 | 0.41 |
c2 | 0.46 |
D | 5.97 |
D1 | 5.21 |
E | 6.35 |
E1 | 4.32 |
e | 2.29 BSC |
H | 9.94 |
MILLIMETERS | |
--- | --- |
DIM. | MIN. |
L | 1.50 |
L1 | 2.74 ref. |
L2 | 0.51 BSC |
L3 | 0.89 |
L4 | – |
L5 | 1.14 |
L6 | 0.65 |
q | 0° |
q1 | 0° |
q2 | 25° |
Notes
- Dimensioning and tolerance confirm to ASME Y14.5M-1994
- All dimensions are in millimeters. Angles are in degrees
- Heat sink side flash is max. 0.8 mm
- Radius on terminal is optional
Case Outline for TO-251AA (High Voltage)
OPTION 1:
MILLIMETERS | INCHES | MILLIMETERS | INCHES | |||
---|---|---|---|---|---|---|
DIM. | MIN. | MAX. | MIN. | MAX. | DIM. | MIN. |
MAX. | MIN. | MAX. | ||||
A | 2.18 | 2.39 | 0.086 | 0.094 | D1 | 5.21 |
A1 | 0.89 | 1.14 | 0.035 | 0.045 | E | 6.35 |
b | 0.64 | 0.89 | 0.025 | 0.035 | E1 | 4.32 |
b1 | 0.65 | 0.79 | 0.026 | 0.031 | e | 2.29 BSC |
b2 | 0.76 | 1.14 | 0.030 | 0.045 | L | 8.89 |
b3 | 0.76 | 1.04 | 0.030 | 0.041 | L1 | 1.91 |
b4 | 4.95 | 5.46 | 0.195 | 0.215 | L2 | 0.89 |
c | 0.46 | 0.61 | 0.018 | 0.024 | L3 | 1.14 |
c1 | 0.41 | 0.56 | 0.016 | 0.022 | q1 | 0′ |
c2 | 0.46 | 0.86 | 0.018 | 0.034 | q2 | 25′ |
D | 5.97 | 6.22 | 0.235 | 0.245 |
ECN: E21-0605-Rev. B, 25-Oct-2021 DWG: 5968
Notes
- Dimensioning and tolerancing per ASME Y14.5M-1994
- Dimension are shown in inches and millimeters
- Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005″) per side. These dimensions are measured at the outermost extremes of the plastic body
- Thermal pad contour optional with dimensions b4, L2, E1 and D1
- Lead dimension uncontrolled in L3
- Dimension b1, b3 and c1 apply to base metal only
- Outline conforms to JEDEC® outline TO-251AA
OPTION 2: FACILITY CODE = N
DIM.| MIN.| MAX.| MAX.| | DIM.| MIN.|
MAX.| MAX.
---|---|---|---|---|---|---|---|---
A| 2.180| 2.285| 2.390| D2| 5.380| –| –
A1| 0.890| 1.015| 1.140| E| 6.350| 6.540| 6.730
b| 0.640| 0.765| 0.890| E1| 4.32| –| –
b1| 0.640| 0.715| 0.790| e| 2.29 BSC|
b2| 0.760| 0.950| 1.140| L| 8.890| 9.270| 9.650
b3| 0.760| 0.900| 1.040| L1| 1.910| 2.100| 2.290
b4| 4.950| 5.205| 5.460| L2| 0.890| 1.080| 1.270
c| 0.460| –| 0.610| L3| 1.140| 1.330| 1.520
c1| 0.410| –| 0.560| L4| 1.300| 1.400| 1.500
c2| 0.460| –| 0.610| q1| 0°| 7.5°| 15°
D| 5.970| 6.095| 6.220| q2| 4°| –| –
D1| 4.300| –| –|
ECN: E21-0605-Rev. B, 25-Oct-2021 DWG: 5968
Notes
- Dimensioning and tolerancing per ASME 5M-1994
- All dimension are in millimeters, angles are in degrees
- Heat sink side flash is 0.8 mm
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Disclaimer
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Read More About This Manual & Download PDF:
References
- Vishay Intertechnology: Passives & Discrete Semiconductors
- IRLR110, IRLU110, SiHLR110, SiHLU110 Power MOSFET | Vishay
Read User Manual Online (PDF format)
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