VISHAY IRLD024 Power MOSFET Instruction Manual
- June 10, 2024
- VISHAY
Table of Contents
VISHAY IRLD024 Power MOSFET Instruction Manual
FEATURES
- Dynamic dV/dt rating
- For automatic insertion
- End stackable
- Logic-level gate drive
- RDS(on) dpecified at VGS = 4 V and 5 V
- 175 °C operating temperature
- Fast switching
- Material categorization: for definitions of compliance please see www.vishay.com/doc?99912
DESCRIPTION
Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness.
The 4 pin DIP package is a low cost machine-insertiable case style which can be stacked in multiple combinations on standard 0.1″ pin centers. The dual drain servers as a thermal link to the mounting surface for power dissipation levels up to 1 W.
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see
fig. 11)
b. VDD = 25 V, starting TJ = 25 °C, L = 16 mH, Rg = 25 Ω, IAS = 2.5 A (see
fig. 12)
c. ISD ≤ 17 A, dI/dt ≤ 140 A/μs, VDD ≤ VDS, TJ ≤ 175 °C
d. 1.6 mm from case
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see
fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
Fig. 1 – Typical Output Characteristics, TA = 25 °C
Fig. 2 – Typical Output Characteristics, TA = 175 °C
Fig. 3 – Typical Transfer Characteristics
Fig. 4 – Normalized On-Resistance vs. Temperature
Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 – Typical Source-Drain Diode Forward Voltage
Fig. 8 – Maximum Safe Operating Area
Fig. 9 – Maximum Drain Current vs. Ambient Temperature
Fig. 10a – Switching Time Test Circuit
Fig. 10b – Switching Time Waveforms
Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to- Ambient
Fig. 12a – Unclamped Inductive Test Circuit
Fig. 12b – Unclamped Inductive Waveforms
Fig. 12c – Maximum Avalanche Energy vs. Drain Current
Fig. 13a – Basic Gate Charge Waveform
Fig. 13b – Gate Charge Test Circuit
Fig. 14 – For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be
manufactured at one of several qualified locations. Reliability data for
Silicon
Technology and Package Reliability represent a composite of all qualified
locations. For related documents such as package/tape drawings, part marking,
and reliability data, see
www.vishay.com/ppg?91308.
HVM DIP (High voltage)
Note
- Package length does not include mold flash, protrusions or gate burrs. Package width does not include interlead flash or protrusions.
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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Revision: 01-Jan-2023
Document Number: 91000
Downloaded from Arrow.com.
References
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