VISHAY SiR638ADP-T1-RE3 N-Channel 40 V D-S MOSFET User Manual

VISHAY SiR638ADP-T1-RE3 N-Channel 40 V D-S MOSFET User Manual

Product Overview

Power PAK® SO-8 Single

FEATURES

• Trench FET® Gen IV power MOSFET
• 100 % Rg and UIS tested
• Qgd/Qgs ratio < 1 optimizes switching characteristics Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

APPLICATIONS

• Synchronous rectification
• OR-ing
• High power density DC/DC
• VRMs and embedded DC/DC
• DC/AC inverters
• Load switch

N-Channel MOSFET

PRODUCT SUMMARY

VDS (V)| 40
RDS(on) max. (W) at VGS = 10 V| 0.00088
RDS(on) max. (W) at VGS = 4.5 V| 0.00116
Qg typ. (nC)| 53
ID (A) a, g| 100
Configuration| Single
ORDERING INFORMATION

Package| PowerPAK SO-8
Lead (Pb)-free and halogen-free| SiR638ADP-T1-RE3
Lead (Pb)-free, halogen-free, BLR and IOL| SiR638ADP-T1-UE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| LIMIT| UNIT
Drain-source voltage| VDS| 40| V
Gate-source voltage| VGS| +20, -16
Continuous drain current (TJ = 150 °C)| TC = 25 °C| ID| 100 g|

A

TC = 70 °C| 100 g
TA = 25 °C| 62.8 b, c
TA = 70 °C| 50.2 b, c
Pulsed drain current (t = 100 μs)| IDM| 400
Continuous source-drain diode current| TC = 25 °C| IS| 94.5
TA = 25 °C| 5.6 b, c
Single pulse avalanche current| L = 0.1 mH| IAS| 50
Single pulse avalanche Energy| EAS| 125| mJ
Maximum power dissipation| TC = 25 °C| PD| 104| W
TC = 70 °C| 66.6
TA = 25 °C| 6.25 b, c
TA = 70 °C| 4 b, c
Operating junction and storage temperature range| TJ, Tstg| -55 to +150| °C
Soldering recommendations (peak temperature) d, e| | 260

THERMAL RESISTANCE RATINGS

PARAMETER

|

SYMBOL

|

TYPICAL

|

MAXIMUM

|

UNIT

Maximum junction-to-ambient b, f

| t £ 10 s| RthJA| 15| 20| °C/W
Maximum junction-to-case (drain)| Steady state| RthJC| 0.9| 1.2

Notes
a. Based on TC = 25 °C
b. Surface mounted on 1″ x 1″ FR4 board
c. t = 10 s
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components
f. Maximum under steady state conditions is 54 °C/W
g. Package limited

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.| MAX.| UNIT
Static
Drain-source breakdown voltage| VDS| VGS = 0 V, ID = 250 μA| 40| –| –| V
VDS temperature coefficient| DVDS/TJ| ID = 250 μA| –| 24| –| mV/°C
VGS(th) temperature coefficient| DVGS(th)/TJ| –| -5.4| –
Gate-source threshold voltage| VGS(th)| VDS = VGS, ID = 250 μA| 1.1| –| 2.3| V
Gate-source leakage| IGSS| VDS = 0 V, VGS = +20, -16 V| –| –| ± 100| nA
Zero gate voltage drain current| IDSS| VDS = 40 V, VGS = 0 V| –| –| 1| μA
VDS = 40 V, VGS = 0 V, TJ = 55 °C| –| –| 10
On-state drain current a| ID(on)| VDS ³ 5 V, VGS = 10 V| 50| –| –| A
Drain-source on-state resistance a| RDS(on)| VGS = 10 V, ID = 20 A| –| 0.00073| 0.00088| W
VGS = 4.5 V, ID = 15 A| –| 0.00096| 0.00116
Forward transconductance a| gfs| VDS = 10 V, ID = 20 A| –| 147| –| S
Dynamic b
Input capacitance| Ciss| VDS = 20 V, VGS = 0 V, f = 1 MHz| –| 9100| –| pF
Output capacitance| Coss| –| 1650| –
Reverse transfer capacitance| Crss| –| 210| –
Crss/Ciss ratio| | –| 0.024| 0.048|
Total gate charge| Qg| VDS = 20 V, VGS = 10 V, ID = 20 A| –| 110| 165|

nC

VDS = 20 V, VGS = 4.5 V, ID = 20 A| –| 53| 80
Gate-source charge| Qgs| –| 22.5| –
Gate-drain charge| Qgd| –| 9.5| –
Output charge| Qoss| VDS = 20 V, VGS = 0 V| –| 75| –
Gate resistance| Rg| f = 1 MHz| 0.3| 0.88| 1.5| W
Turn-on delay time| td(on)| VDD = 20 V, RL = 1 WID @ 20 A, VGEN = 10 V, Rg = 1 W| –| 15| 30|

ns

Rise time| tr| –| 42| 84
Turn-off delay time| td(off)| –| 42| 84
Fall time| tf| –| 10| 20
Turn-on delay time| td(on)| VDD = 20 V, RL = 1 WID @ 20 A, VGEN = 4.5 V, Rg = 1 W| –| 45| 90
Rise time| tr| –| 100| 200
Turn-off delay time| td(off)| –| 56| 112
Fall time| tf| –| 40| 80
Drain-Source Body Diode Characteristics
Continuous source-drain diode current| IS| TC = 25 °C| –| –| 100| A
Pulse diode forward current (tp = 100 μs)| ISM| | –| –| 400
Body diode voltage| VSD| IS = 10 A| –| 0.73| 1.1| V
Body diode reverse recovery time| trr| IF = 20 A, di/dt = 100 A/μs, TJ = 25 °C| –| 65| 130| ns
Body diode reverse recovery charge| Qrr| –| 90| 180| nC
Reverse recovery fall time| ta| –| 37| –| ns
Reverse recovery rise time| tb| –| 30| –

Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %
b. Guaranteed by design, not subject to production testing

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

**Output Characteristics

Transfer Characteristics

Capacitance

Gate Charge

On-Resistance vs. Junction Temperature

**

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

**
Source-Drain Diode Forward Voltage

On-Resistance vs. Gate-to-Source Voltage

Threshold Voltage

Single Pulse Power, Junction-to-Ambient

Safe Operating Area

Current Derating a

Power, Junction-to-Case

Power, Junction-to-Ambient**

Note
a. The power dissipation PD is based on TJ max. = 150 °C, using junction- to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit.

**Normalized Thermal Transient Impedance, Junction-to-Ambient

Normalized Thermal Transient Impedance, Junction-to-Case
**

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?75297.

PowerPAK® SO-8, (Single/Dual)

Notes

1. Inch will govern.
2. Dimensions exclusive of mold gate burrs.
3. Dimensions exclusive of mold flash and cutting burrs.

ECN: S17-0173-Rev. L, 13-Feb-17 DWG: 5881

PowerPAK® SO-8 Mounting and Thermal ConsiderationsAPPLICATION NOTE

by Wharton McDaniel
MOSFETs for switching applications are now available with die on resistances around 1 m and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvious that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues.
In this application note, PowerPAK’s construction is described. Following this mounting information is presented including land patterns and soldering profiles for maximum reliability. Finally, thermal and electrical performance is discussed.

THE PowerPAK PACKAGE
The PowerPAK package was developed around the SO-8 package (figure 1). The PowerPAK SO-8 utilizes the same footprint and the same pin-outs as the standard SO-8. This allows PowerPAK to be substituted directly for a standard SO-8 package. Being a leadless package, PowerPAK SO-8 utilizes the entire SO-8 footprint, freeing space normally occupied by the leads, and thus allowing it to hold a larger die than a standard SO-8. In fact, this larger die is slightly larger than a full sized DPAK die. The bottom of the die attach pad is exposed for the purpose of providing a direct, low resistance thermal path to the substrate the device is mounted on. Finally, the package height is lower than the standard SO-8, making it an excellent choice for applications with space constraints.

Fig. 1 PowerPAK 1212 Devices

PowerPAK SO-8 SINGLE MOUNTING
The PowerPAK single is simple to use. The pin arrangement (drain, source, gate pins) and the pin dimensions are the same as standard SO-8 devices (see figure 2). Therefore, the PowerPAK connection pads match directly to those of the SO-8. The only difference is the extended drain connection area. To take immediate advantage of the PowerPAK SO-8 single devices, they can be mounted to existing SO-8 land patterns.

Standard SO-8 PowerPAK SO-8
Fig. 2

The minimum land pattern recommended to take full advantage of the PowerPAK thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK SO-8 single in the index of this document.
In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease
in foot-to-board and foot-to-ambient thermal resistance. Under specific conditions of board configuration, copper weight and layer stack, experiments have found that more than about 0.25 in2 to 0.5 in2 of additional copper (in addition to the drain land) will yield little improvement in thermal performance.

PowerPAK SO-8 DUAL
The pin arrangement (drain, source, gate pins) and the pin dimensions of the PowerPAK SO-8 dual are the same as standard SO-8 dual devices. Therefore, the PowerPAK device connection pads match directly to those of the SO-8.
As in the single-channel package, the only exception is the extended drain connection area. Manufacturers can likewise take immediate advantage of the PowerPAK SO-8 dual devices by mounting them to existing SO-8 dual land patterns.

To take the advantage of the dual PowerPAK SO-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 24 mils. This matches the spacing of the two drain pads on the PowerPAK SO-8 dual package.

REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow temperature profile used, and the temperatures and time duration, are shown in figures 3 and 4. For the lead (Pb)-free solder profile, see www.vishay.com/doc?73257.

Fig. 3 Solder Reflow Temperature Profile

Fig. 4 Solder Reflow Temperatures and Time Durations
THERMAL PERFORMANCE
Introduction
A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, RthJC, or the junction-to-foot thermal resistance, RthJF This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the DPAK, PowerPAK SO-8, and standard SO-8. The PowerPAK has thermal performance equivalent to the DPAK, while having an order of magnitude better thermal performance over the SO-8.

TABLE 1 – DPAK AND POWERPAK SO-8 EQUIVALENT STEADY STATE PERFORMANCE

| DPAK| PowerPAK SO-8| Standard SO-8
Thermal Resistance RthJC| 1.2 °C/W| 1 °C/W| 16 °C/W

Thermal Performance on Standard SO-8 Pad Pattern
Because of the common footprint, a PowerPAK SO-8 can be mounted on an existing standard SO-8 pad pattern.
The question then arises as to the thermal performance of the PowerPAK device under these conditions. A characterization was made comparing a standard SO-8 and a PowerPAK device on a board with a trough cut out underneath the PowerPAK drain pad. This configuration restricted the heat flow to the SO-8 land pads. The results are shown in figure 5.

Si4874DY vs. Si7446DP PPAK on a 4-Layer Board SO-8 Pattern, Trough Under Drain

Pulse Duration (sec)
Fig. 5 Power PAK SO-8 and Standard SO-0 Land Pad Thermal Path

Because of the presence of the trough, this result suggests a minimum performance improvement of 10 °C/W by using a PowerPAK SO-8 in a standard SO-8 PC board mount.

The only concern when mounting a PowerPAK on a standard SO-8 pad pattern is that there should be no traces running between the body of the MOSFET. Where the standard SO-8 body is spaced away from the pc board, allowing traces to run underneath, the PowerPAK sits directly on the pc board.

Thermal Performance – Spreading Copper
Designers may add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper.

Figure 6 shows the thermal resistance of a PowerPAK SO-8 device mounted on a 2-in. 2-in., four-layer FR-4 PC board.
The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.3 to 0.4 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No significant effect was observed.

Rth vs. Spreading Copper (0 %, 50 %, 100 % Back Copper)
) stt a w/ C( ecnadep Im Spreading Copper (sq in)
Fig. 6 Spreading Copper Junction-to-Ambient Performance

SYSTEM AND ELECTRICAL IMPACT OF PowerPAK SO-8
In any design, one must take into account the change in MOSFET RDS(on) with temperature (figure 7).

On-Resistance vs. Junction Temperature
R ) no( SD) dezil a mr o N( ( ecnat si se R- n O – R
T J – Junction Temperature (°C)
Fig. 7 MOSFET RDS(on) vs. Temperature
A MOSFET generates internal heat due to the current passing through the channel. This self-heating raises the junction temperature of the device above that of the PC board to which it is mounted, causing increased power dissipation in the device. A major source of this problem lies in the large values of the junction-to-foot thermal resistance of the SO-8 package.

PowerPAK SO-8 minimizes the junction-to-board thermal resistance to where the MOSFET die temperature is very close to the temperature of the PC board. Consider two devices mounted on a PC board heated to 105 °C by other components on the board (figure 8).

Fig. 8 Temperature of Devices on a PC Board

Suppose each device is dissipating 2.7 W. Using the junction-to-foot thermal resistance characteristics of the Power PAK SO-8 and the standard SO-8, the die temperature is determined to be 107 °C for the Power PAK (and for DPAK) and 148 °C for the standard SO-8. This is a 2 °C rise above the board temperature for the Power PAK and a 43 °C rise for the standard SO-8. Referring to figure 7, a 2 °C difference has minimal effect on RDS(on) whereas a 43 °C difference has a significant effect on RDS(on).

Minimizing the thermal rise above the board temperature by using Power PAK has not only eased the thermal design but it has allowed the device to run cooler, keep rDS(on) low, and permits the device to handle more current than the same MOSFET die in the standard SO-8 package.

CONCLUSIONS
PowerPAK SO-8 has been shown to have the same thermal performance as the DPAK package while having the same footprint as the standard SO-8 package. The PowerPAK SO-8 can hold larger die approximately equal in size to the maximum that the DPAK can accommodate implying no sacrifice in performance because of package limitations. Recommended PowerPAK SO-8 land patterns are provided to aid in PC board layout for designs using this new package.

Thermal considerations have indicated that significant advantages can be gained by using PowerPAK SO-8 devices in designs where the PC board was laid out for the standard SO-8. Applications experimental data gave thermal performance data showing minimum and typical thermal performance in a SO-8 environment, plus information on the optimum thermal performance obtainable including spreading copper. This further emphasized the DPAK equivalency.
PowerPAK SO-8 therefore has the desired small size characteristics of the SO-8 combined with the attractive thermal characteristics of the DPAK package.

**RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single

**                                     Recommended Minimum Pads Dimensions in Inches/(mm)
Return to Index

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Revision: 01-Jan-2023 1 Document Number: 91000

For technical questions, contact: powermosfettechsupport@vishay.com
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References

• Vishay Intertechnology: Passives & Discrete Semiconductors
• SiR638ADP MOSFETs | Vishay

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