VISHAY SiSD5300DN Channel Source Flip Technology Delivers Instructions

SiSD5300DN
Vishay Siliconix
N-Channel 30 V (D-S) MOSFET
PowerPAK® 1212-F

PRODUCT SUMMARY

FEATURES

• TrenchFET ® Gen V power MOSFET
• Very low R DS x Q g figure-of-merit (FOM)
• Source flip technology, enhance thermal performance
• 100 % R and UIS tested
• Material categorization: for definitions of complianceg please see www.vishay.com/doc?99912

APPLICATIONS

• DC/DC converter
• Synchronous rectification
• Battery management
• Oring and load switch

ORDERING INFORMATION

ABSOLUTE MAXIMUM RATINGS (T A = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| LIMIT| UNIT
Drain-source voltage| VDS| 30| V
Gate-source voltage| VGS| +16, -12
Continuous drain current (TJ = 150 °C)| TC = 25 °C| ID| 198| A
TC = 70 °C| 158
TA = 25 °C| 62 b, c
TA = 70 °C| 50 b, c
Pulsed drain current (t = 100 μs)| IDM| 500
Continuous source-drain diode current| TC = 25 °C| IS| 52
TA = 25 °C| 4.9 b, c
Single pulse avalanche current| L = 0.1 mH| IAS| 38
Single pulse avalanche energy| EAS| 72| mJ
Maximum power dissipation| TC = 25 °C| PD| 57| W
TC = 70 °C| 36
TA = 25 °C| 5.4 b, c
TA = 70 °C| 3.5 b, c
Operating junction and storage temperature range| TJ, Tstg| -55 to +150| °C
Soldering recommendations (peak temperature) d, e| | 260
THERMAL RESISTANCE RATINGS

PARAMETER| SMYBOL| TYPICAL| MAXIMUM|

UNIT

Maximum junction-to-ambient b, f| t £ 10 s| RthJA| 18| 23| °C/W
Maximum junction-to-case (source)| Steady state| RthJC| 1.7| 2.2

Notes
a. Based on T C = 25 °C
b. Surface mounted on 1″ x 1″ FR4 board
c. t = 10 s
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-F is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components
f. Maximum under steady state conditions is 56 °C/W
S23-0191-Rev. A, 10-Apr-20231
Document Number: 62220
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SPECIFICATIONS

(T J = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.| MAX.| UNIT
---|---|---|---|---|---|---
Static
Drain-source breakdown voltage| VDS| VGS = 0 V, ID = 250 μA| 30| –| –| V
VDS temperature coefficient| DVDS/TJ| ID = 10 mA| –| 19.5| –| mV/°C
VGS(th) temperature coefficient| DVGS(th)/TJ| ID = 250 μA| –| -5.1| –
Gate-source threshold voltage| VGS(th)| VDS = VGS, ID = 250 μA| 1.0| –| 2.0| V
Gate-source leakage| IGSS| VDS = 0 V, VGS = +16, -12 V| –| –| ± 100| nA
Zero gate voltage drain current| IDSS| VDS = 24 V, VGS = 0 V| –| –| 1| μA
VDS = 24 V, VGS = 0 V, TJ = 55 °C| –| –| 10
Drain-source on-state resistance a| RDS(on)| VGS = 10 V, ID = 15 A| –| 0.00071| 0.00087| W
VGS = 4.5 V, ID = 10 A| –| 0.00105| 0.00130
Forward transconductance a| gfs| VDS = 10 V, ID = 45 A| –| 162| –| S
Dynamic b
Input capacitance| Ciss| VDS = 15 V, VGS = 0 V, f = 1 MHz| –| 5030| –| pF
Output capacitance| Coss| –| 1355| –
Reverse transfer capacitance| Crss| –| 105| –
Crss/Ciss ratio| | –| 0.021| 0.042|
Total gate charge| Qg| VDS = 15 V, VGS = 10 V, ID = 10 A| –| 59| 36.2| nC
VDS = 15 V, VGS = 4.5 V, ID = 10 A| –| 27| 17.6
Gate-source charge| Qgs| –| 12| –
Gate-drain charge| Qgd| –| 4.4| –
Output charge| Qoss| VDS = 15 V, VGS = 0 V| –| 45| –
Gate resistance| Rg| f = 1 MHz| 0.16| 0.8| 1.6| W
Turn-on delay time| td(on)| VDD = 15 V, RL = 1.5 W
ID @ 10 A, VGEN = 10 V, Rg = 1 W| –| 13| 30| ns
Rise time| tr| –| 5| 10
Turn-off delay time| td(off)| –| 31| 60
Fall time| tf| –| 6| 15
Turn-on delay time| td(on)| VDD = 15 V, RL = 1.5 W
ID @ 10 A, VGEN = 4.5 V, Rg = 1 W| –| 26| 50
Rise time| tr| –| 90| 180
Turn-off delay time| td(off)| –| 32| 60
Fall time| tf| –| 15| 30
Drain-Source Body Diode Characteristics
Continuous source-drain diode current| IS| TC = 25 °C| –| –| 52| A
Pulse diode forward current a| ISM| | –| –| 500
Body diode voltage| VSD| IS = 10 A| –| 0.75| 1.1| V
Body diode reverse recovery time| trr| IF = 10 A, di/dt = 100 A/μs, TJ = 25 °C| –| 42| 85| ns
Body diode reverse recovery charge| Qrr| –| 40| 80| nC
Reverse recovery fall time| ta| –| 22| –| ns
Reverse recovery rise time| tb| –| 20| –

Notes
a. Pulse test: pulse width ≤ 300 μs, duty cycle ≤ 2 %
b. Guaranteed by design, not subject to production testing
c. Based on characterization, not subject to production testing
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TYPICAL CHARACTERISTICS

(25 °C, unless otherwise noted)

Note
a. The power dissipation P D is based on T J max. = 150 °C, using junction-to- case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit

  Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62220.

Legal Disclaimer Notice

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Revision: 01-Jan-2024
Document Number: 91000

For technical questions, contact:
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com

References

• Vishay Intertechnology: Passives & Discrete Semiconductors

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