VISHAY SI7465DP-T1-E3 P-Channel 60 V D-S MOSFET Owner’s Manual
- June 1, 2024
- VISHAY
Table of Contents
www.vishay.com
P-Channel 60 V (D-S) MOSFET
Si7465DP
Vishay Siliconix
SI7465DP-T1-E3 P-Channel 60 V D-S MOSFET
PRODUCT SUMMARY
V DS (V)| R DS(on) ( W )| I D (A)| Q g (TYP.)
-60| 0.064 at VGS = -10 V| -5| 26
0.080 at VGS = -4.5 V| -4.5
Ordering Information:
Si7465DP-T1-E3 (Lead (Pb)-free)
Si7465DP-T1-GE3 (Lead (Pb)-free and Halogen-free)
FEATURES
- TrenchFET® Power MOSFET
- New Low Thermal Resistance PowerPAK® Package with Low 1.07 mm Profile
- Material categorization:
- For definitions of compliance please see www.vishay.com/doc?99912
ABSOLUTE MAXIMUM RATINGS
**** (TA = 25 °C, unless otherwise noted)
PARAMETER| SYMBOL| 10 s| STEADY STATE| UNIT
Drain-Source Voltage| VDS| -60| V
Gate-Source Voltage| VGS| ± 20
Continuous Drain Current (TJ = 150°C)a| TA = 25 °C| ID| -5| -3.2|
A
TA = 70 °C| -4| -2.6
Pulsed Drain Current| IDM| -25
Continuous Source Current (Diode Conduction)a| IS| -2.9| -1.2
Avalanche Current| L = 0.1 mH| IAS| 22
Single Pulse Avalanche Energy| EAS| 24.2| mJ
Maximum Power Dissipationa| TA = 25 °C| PD| 3.5| 1.5| W
TA = 70 °C| 2.2| 0.94
Operating Junction and Storage Temperature Range| TJ, Tstg| -55 to 150| °C
Soldering Recommendations (Peak Temperature)b,c| | 260
THERMAL RESISTANCE RATINGS
| PARAMETER | SYMBOL | TYPICAL | MAXIMUM | UNIT |
|---|---|---|---|---|
| Maximum Junction-to-Ambienta | t £ 10 s | RthJA | 27 | 36 |
°C/W
Steady State| 60| 85
Maximum Junction-to-Case (Drain)| Steady State| RthJC| 3.3| 4.3
Notes
a. Surface mounted on 1″ x 1″ FR4 board.
b. See solder profile
(www.vishay.com/ppg?73257. The PowerPAK
1212-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder
fillet at the exposed copper tip cannot be guaranteed and is not required to
ensure adequate bottom side solder interconnection.
c. Rework conditions: Manual soldering with a soldering iron is not
recommended for leadless components.
SPECIFICATIONS
(TJ = 25 °C, unless otherwise noted)
PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.|
MAX.| UNIT
Static
Gate Threshold Voltage| VGS(th)| VDS = VGS, ID = -250 μA| -1| | -3| V
Gate-Body Leakage| IGSS| VDS = 0 V, VGS = ± 20 V| | | ± 100| nA
Zero Gate Voltage Drain Current| IDSS| VDS = -60 V, VGS = 0 V| | | -1| μA
VDS = -60 V, VGS = 0 V, TJ = 70 °C| | | -10
On-State Drain Currenta| ID(on)| VDS £ -5 V, VGS = -10 V| -25| | | A
Drain-Source On-State Resistancea| RDS(on)| VGS = -10 V, ID = -5 A| | 0.051|
0.064| W
VGS = -4.5 V, ID = -4.5 A| | 0.064| 0.080
Forward Transconductancea| gfs| VDS = -15 V, ID = -5 A| | 16| | S
Diode Forward Voltagea| VSD| IS = -2.9 A, VGS = 0 V| | -0.8| -1.2| V
Dynamic b
Total Gate Charge| Qg|
VDS = -30 V, VGS = -10 V, ID = -5 A
| | 26| 40|
nC
Gate-Source Charge| Qgs| | 4.5|
Gate-Drain Charge| Qgd| | 7|
Gate Resistance| Rg| | | 7| | W
Turn-On Delay Time| td(on)|
VDD = -30 V, RL = 30 W
ID @ -1 A, VGEN = –10 V, Rg = 6 W
| | 8| 15|
ns
Rise Time| tr| | 9| 15
Turn-Off Delay Time| td(off)| | 65| 100
Fall Time| tf| | 30| 45
Source-Drain Reverse Recovery Time| trr| IF = -5 A, dI/dt = 100 A/μs| | 41| 70
Notes
a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
Vishay Siliconix maintains worldwide manufacturing
capability. Products may be manufactured at one of several qualified
locations. Reliability data for Silicon echnology and Package Reliability
represent a composite of all qualified locations. For related documents such
as package/tape drawings, part marking, and reliability data, see
www.vishay.com/ppg?73113.
Package Information
Vishay Siliconix
PowerPAK® SO-8, (Single/Dual)
Notes
- Inch will govern.
- Dimensions exclusive of mold gate burrs.
- Dimensions exclusive of mold flash and cutting burrs.
| DIM. | MILLIMETERS | INCHES |
|---|---|---|
| MIN. | NOM. | MAX. |
| A | 0.97 | 1.04 |
| A1 | – | |
| b | 0.33 | 0.41 |
| c | 0.23 | 0.28 |
| D | 5.05 | 5.15 |
| D1 | 4.80 | 4.90 |
| D2 | 3.56 | 3.76 |
| D3 | 1.32 | 1.50 |
| D4 | 0.57 typ. | 0.0225 typ. |
| D5 | 3.98 typ. | 0.157 typ. |
| E | 6.05 | 6.15 |
| E1 | 5.79 | 5.89 |
| E2 | 3.48 | 3.66 |
| E3 | 3.68 | 3.78 |
| E4 | 0.75 typ. | 0.030 typ. |
| e | 1.27 BSC | 0.050 BSC |
| K | 1.27 typ. | 0.050 typ. |
| K1 | 0.56 | – |
| H | 0.51 | 0.61 |
| L | 0.51 | 0.61 |
| L1 | 0.06 | 0.13 |
| q | 0° | – |
| W | 0.15 | 0.25 |
| M | 0.125 typ. | 0.005 typ. |
ECN: S17-0173-Rev. L, 13-Feb-17 DWG: 5881
Application Note AN821
PowerPAK® SO-8 Mounting and Thermal Consideration s
by Wharton McDaniel
MOSFETs for switching applications are now available with die on resistances
around 1 mΩ and with the capability to handle 85 A. While these die
capabilities represent a major advance over what was available just a few
years ago, it is important for power MOSFET packaging technology to keep pace.
It should be obvious that degradation of a high performance die by the package
is undesirable. PowerPAK is a new package technology that addresses these
issues.
In this application note, PowerPAK’s construction is described. Following this
mounting information is presented including land patterns and soldering
profiles for maximum reliability. Finally, thermal and electrical performance
is discussed.
THE PowerPAK PACKAGE
The PowerPAK package was developed around the SO-8 package (figure 1). The
PowerPAK SO-8 utilizes the same footprint and the same pin-outs as the
standard SO-8. This allows PowerPAK to be substituted directly for a standard
SO-8 package. Being a leadless package, PowerPAK SO-8 utilizes the entire SO-8
footprint, freeing space normally occupied by the leads, and thus allowing it
to hold a larger die than a standard SO-8. In fact, this larger die is
slightly larger than a full sized DPAK die. The bottom of the die attach pad
is exposed for the purpose of providing a direct, low resistance thermal path
to the substrate the device is mounted on. Finally, the package height is
lower than the standard SO-8, making it an excellent choice for applications
with space constraints.
PowerPAK SO-8 SINGLE
MOUNTING
The PowerPAK single is simple to use. The pin arrangement (drain, source,
gate pins) and the pin dimensions are the same as standard SO-8 devices (see
figure 2). Therefore, the PowerPAK connection pads match directly to those of
the SO-8. The only difference is the extended drain connection area. To take
immediate advantage of the PowerPAK SO-8 single devices, they can be mounted
to existing SO-8 land patterns. The minimum land pattern recommended to take
full advantage of the PowerPAK thermal performance see Application Note 826,
Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay
Siliconix MOSFETs. Click on the PowerPAK SO-8 single in the index of this
document.
In this figure, the drain land pattern is given to make full contact to the
drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and top of the drawn
pattern. This extension will serve to increase the heat dissipation by
decreasing the thermal resistance from the foot of the PowerPAK to the PC
board and therefore to the ambient. Note that increasing the drain land area
beyond a certain point will yield little decrease in foot-to-board and foot-
to-ambient thermal resistance. Under specific conditions of board
configuration, copper weight and layer stack, experiments have found that more
than about 0.25 in 2 to 0.5 in 2 of additional copper (in addition to the
drain land) will yield little improvement in thermal performance.
PowerPAK SO-8 DUAL
The pin arrangement (drain, source, gate pins) and the pin dimensions of
the PowerPAK SO-8 dual are the same as standard SO-8 dual devices. Therefore,
the PowerPAK device connection pads match directly to those of the SO-8. As in
the single-channel package, the only exception is the extended drain
connection area. Manufacturers can likewise take immediate advantage of the
PowerPAK SO-8 dual devices by mounting them to existing SO-8 dual land
patterns.
To take the advantage of the dual PowerPAK SO-8’s thermal performance, the
minimum recommended land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay
Siliconix MOSFETs. Click on the PowerPAK 1212-8 dual in the index of this
document. The gap between the two drain pads is 24 mils. This matches the
spacing of the two drain pads on the PowerPAK SO-8 dual package.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder reflow reliability
requirements. Devices are subjected to solder reflow as a test preconditioning
and are then reliability-tested using temperature cycle, bias humidity, HAST,
or pressure pot. The solder reflow temperature profile used, and the
temperatures and time duration, are shown in figures 3 and 4.
For the lead (Pb)-free solder profile, see
www.vishay.com/doc?73257.
| Ramp-Up Rate | + 3 °C /s max. |
|---|---|
| Temperature at 150 – 200 °C | 120 s max. |
| Temperature Above 217 °C | 60 – 150 s |
| Maximum Temperature | 255 + 5/- 0 °C |
| Time at Maximum Temperature | 30 s |
| Ramp-Down Rate | + 6 °C/s max. |
THERMAL PERFORMANCE
Introduction
A basic measure of a device’s thermal performance is the junction-to-case
thermal resistance, R , or the junction-to-foot thermal resistance, R thJF
thJC This parameter is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device only, in other words,
independent of the properties of the object to which the device is mounted.
Table 1 shows a comparison of the DPAK, PowerPAK SO-8, and standard SO-8. The
PowerPAK has thermal performance equivalent to the DPAK, while having an order
of magnitude better thermal performance over the SO-8.
TABLE 1 – DPAK AND POWERPAK SO-8 EQUIVALENT STEADY STATE PERFORMANCE
| DPAK| PowerPAK SO-8| Standard SO-8
---|---|---|---
Thermal Resistance RthJC| 1.2 °C/W| 1 °C/W| 16 °C/W
Thermal Performance on Standard SO-8 Pad Pattern
Because of the common footprint, a PowerPAK SO-8 can be mounted on an existing
standard SO-8 pad pattern.
The question then arises as to the thermal performance of the PowerPAK device
under these conditions. A characterization was made comparing a standard SO-8
and a PowerPAK device on a board with a trough cut out underneath the PowerPAK
drain pad. This configuration restricted the heat flow to the SO-8 land pads.
The results are shown in figure 5.
Because of the presence of
the trough, this result suggests a minimum performance improvement of 10 °C/W
by using a PowerPAK SO-8 in a standard SO-8 PC board mount.
The only concern when mounting a PowerPAK on a standard SO-8 pad pattern is
that there should be no traces running between the body of the MOSFET. Where
the standard SO-8 body is spaced away from the pc board, allowing traces to
run underneath, the PowerPAK sits directly on the pc board.
Thermal Performance – Spreading Copper
Designers may add additional copper, spreading copper, to the drain pad to aid
in conducting heat from a device. It is helpful to have some information about
the thermal performance for a given area of spreading copper. Figure 6 shows
the thermal resistance of a PowerPAK SO-8 device mounted on a 2-in. 2-in.,
four-layer FR-4 PC board.
The two internal layers and the backside layer are solid copper. The internal
layers were chosen as solid copper to model the large power and ground planes
common in many applications. The top layer was cut back to a smaller area and
at each step junction-to-ambient thermal resistance measurements were taken.
The results indicate that an area above 0.3 to 0.4 square inches of spreading
copper gives no additional thermal performance improvement. A subsequent
experiment was run where the copper on the back-side was reduced, first to 50
% in stripes to mimic circuit traces, and then totally removed. No significant
effect was observed.
SYSTEM AND ELECTRICAL
IMPACT OF PowerPAK SO-8
In any design, one must take into account the change in MOSFET R DS(on) with
temperature (figure 7). Fig. 7 MOSFET R DS(on) vs. Temperature
A MOSFET generates internal heat due to the current passing through the
channel. This self-heating raises the junction temperature of the device above
that of the PC board to which it is mounted, causing increased power
dissipation in the device. A major source of this problem lies in the large
values of the junction-to-foot thermal resistance of the SO-8 package.
PowerPAK SO-8 minimizes the junction-to-board thermal resistance to where the
MOSFET die temperature is very close to the temperature of the PC board.
Consider two devices mounted on a PC board heated to 105 °C by other
components on the board (figure 8).
Suppose each device is
dissipating 2.7 W. Using the junction-to-foot thermal resistance
characteristics of the PowerPAK SO-8 and the standard SO-8, the die
temperature is determined to be 107 °C for the PowerPAK (and for DPAK) and 148
°C for the standard SO-8. This is a 2 °C rise above the board temperature for
the PowerPAK and a 43 °C rise for the standard SO-8. Referring to figure 7, a
2 °C difference has minimal effect on R DS(on) whereas a 43 °C difference has
a significant effect on R DS(on).
Minimizing the thermal rise above the board temperature by DS(on) using
PowerPAK has not only eased the thermal design but it has allowed the device
to run cooler, keep r low, and permits the device to handle more current than
the same MOSFET die in the standard SO-8 package.
CONCLUSIONS
PowerPAK SO-8 has been shown to have the same thermal performance as the DPAK
package while having the same footprint as the standard SO-8 package. The
PowerPAK SO-8 can hold larger die approximately equal in size to the maximum
that the DPAK can accommodate implying no sacrifice in performance because of
package limitations. Recommended PowerPAK SO-8 land patterns are provided to
aid in PC board layout for designs using this new package.
Thermal considerations have indicated that significant advantages can be
gained by using PowerPAK SO-8 devices in designs where the PC board was laid
out for the standard SO-8. Applications experimental data gave thermal
performance data showing minimum and typical thermal performance in a SO-8
environment, plus information on the optimum thermal performance obtainable
including spreading copper. This further emphasized the DPAK equivalency.
PowerPAK SO-8 therefore has the desired small size characteristics of the SO-8
combined with the attractive thermal characteristics of the DPAK package.
RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single
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Revision: 01-Jan-2024
Document Number: 91000
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