VISHAY IRFB11N50A Power Mosfet Instruction Manual

: June 17, 2024
: VISHAY

Table of Contents

IRFB11N50A
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IRFB11N50A

www.vishay.com Vishay Siliconix

Power MOSFET

TO-220AB

N-Channel MOSFET

PRODUCT SUMMARY

VDS (V)|

500

RDS(on) (Ω)|

VGS = 10 V

|

0.52

Qg (max.) (nC)|

52

Qgs (nC)|

13

Qgd (nC)|

18

Configuration|

Single

FEATURES

Low gate charge Qg results in simple drive requirement
Improved gate, avalanche, and dynamic dV/dt ruggedness
Fully characterized capacitance and avalanche voltage and current
Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

Note

This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details

APPLICATIONS

Switch mode power supply (SMPS)
Uninterruptible power supply
High speed power switching

APPLICABLE OFF LINE SMPS TOPOLOGIES

Two transistor forward
Half and full bridge
Power factor correction boost

ORDERING INFORMATION

Package| TO-220AB
Lead (Pb)-free| IRFB11N50APbF
Lead (Pb)-free and halogen-free| IRFB11N50APbF-BE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER|

SYMBOL

| LIMIT|

UNIT

Drain-source voltage|

VDS

| 500|

V

Gate-source voltage|

VGS

|

± 30

Continuous drain current| VGS at 10 V| TC = 25 °C|

ID

| 11|

A

TC = 100 °C|

7.0

Pulsed drain current a|

IDM

|

44

Linear derating factor| |

1.3

|

W/°C

Single pulse avalanche energy b|

EAS

| 275|

mJ

Repetitive avalanche current a|

IAR

| 11|

A

Repetitive avalanche energy a|

EAR

| 17|

mJ

Maximum power dissipation| TC = 25 °C|

PD

| 170|

W

Peak diode recovery dV/dt c|

dV/dt

| 6.9|

V/ns

Operating junction and storage temperature range|

TJ, Tstg

| -55 to +150|

°C

Soldering recommendations (peak temperature) d| For 10 s| |

300

Mounting torque| 6-32 or M3 screw| |

10

|

lbf · in

1.1

|

N · m

Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 4.5 mH, RG = 25 Ω, IAS = 11 A (see fig. 12)
c. ISD ≤ 11 A, dI/dt ≤ 140 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case

THERMAL RESISTANCE

PARAMETER|

SYMBOL

| TYP.| MAX.|

UNIT

Maximum junction-to-ambient|

RthJA

| –| 62|

°C/W

Case-to-sink, flat, greased surface|

RthCS

| 0.50|

–

Maximum junction-to-case (drain)|

RthJC

| –|

0.75

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER|

SYMBOL

| TEST CONDITIONS| MIN.| TYP.| MAX.|

UNIT

Static
Drain-source breakdown voltage|

VDS

| VGS = 0 V, ID = 250 μA| 500| –| –| V
Gate-source threshold voltage|

VGS(th)

| VDS = VGS, ID = 250 μA| 2.0| –| 4.0| V
Gate-source leakage|

IGSS

| VGS = ± 30 V| –| –| ± 100| nA
Zero gate voltage drain current|

IDSS

| VDS = 500 V, VGS = 0 V| –| –| 25| μA
VDS = 400 V, VGS = 0 V, TJ = 150 °C| –| –| 250
Drain-source on-state resistance|

RDS(on)

| VGS = 10 V| ID = 6.6 Ab| –| –| 0.52| Ω
Forward transconductance|

gfs

| VDS = 50 V, ID = 6.6 A| 6.1| –| –| S
Dynamic
Input capacitance|

Ciss

| VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5| –| 1423| –| pF
Output capacitance| Coss| –| 208| –
Reverse transfer capacitance| Crss| –| 8.1| –
Output capacitance|

Coss

| VGS = 0 V| VDS = 1.0 V, f = 1.0 MHz| –| 2000| –
VDS = 400 V, f = 1.0 MHz| –| 55| –
Effective output capacitance| Coss eff.| VDS = 0 V to 400 V| –| 97| –
Total gate charge| Qg| VGS = 10 V| ID = 11 A, VDS = 400 V
see fig. 6 and 13 b| –| –| 52| nC
Gate-source charge| Qgs| –| –| 13
Gate-drain charge| Qgd| –| –| 18
Turn-on delay time|

td(on)

| VDD = 250 V, ID = 11 A,
RG = 9.1 Ω, RD = 22 Ω, see fig. 10b| –| 14| –| ns
Rise time| tr| –| 35| –
Turn-off delay time| td(off)| –| 32| –
Fall time| tf| –| 28| –
Gate input resistance| Rg| f = 1 MHz, open drain| 0.5| –| 3.2| Ω
Drain-Source Body Diode Characteristics
Continuous source-drain diode current| IS| MOSFET symbol showing the integral reverse p – n junction diode| –| –| 11| A
Pulsed diode forward current a| ISM| –| –| 44
Body diode voltage|

VSD

| TJ = 25 °C, IS = 11 A, VGS = 0 Vb| –| –| 1.5| V
Body diode reverse recovery time| trr| TJ = 25 °C, IF = 11 A, dI/dt = 100 A/μsb| –| 510| 770| ns
Body diode reverse recovery charge| Qrr| –| 3.4| 5.1| μC
Forward turn-on time| ton| Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
c. Coss effective is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

20 µs Pulse Width
TJ = 25 °C

Fig. 1 – Typical Output Characteristics

20 µs Pulse Width
TJ = 150 °C

Fig. 2 – Typical Output Characteristics

TJ = 150 °C
TJ = 25 °C
20 µs Pulse Width
VDS = 50 V

Fig. 3 – Typical Transfer Characteristics

I D = 11 A
V GS = 10 V

Fig. 4 – Normalized On-Resistance vs. Temperature

V GS = 0 V, f = 1 MHz
C iss = C gs + C gd , C ds Shorted
C rss = C gd
C oss = C ds + C gd

Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage

I D = 11 A
V DS = 400 V
V DS = 250 V
V DS = 100 V
For test circuit see figure 13

Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage

TJ = 150 °C
TJ = 25 °C
VGS = 0 V

Fig. 7 – Typical Source-Drain Diode Forward Voltage

Operation in this area limited by R DS(on)
T C = 25 °C
TJ = 150 °C
Single Pulse

Fig. 8 – Maximum Safe Operating Area

Fig. 9 – Maximum Drain Current vs. Case Temperature

Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

Fig. 10a – Switching Time Test Circuit

Fig. 10b – Switching Time Waveforms

VISHAY IRFB11N50A Power Mosfet - Fig. 11

Single Pulse
(Thermal Response)
Notes:
1. Duty Factor, D = t 1 /t 2
2. Peak TJ = P DM x Z thJC + T C

Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 12a – Unclamped Inductive Test Circuit

Fig. 12b – Unclamped Inductive Waveforms

Fig. 12c – Maximum Avalanche Energy vs. Drain Current

Fig. 12d – Typical Drain-to-Source Voltage vs. Avalanche Current

Charge

Fig. 13a – Basic Gate Charge Waveform

Current regulator
Same type as D.U.T.
Current sampling resistors

Fig. 13b – Gate Charge Test Circuit

Peak Diode Recovery dV/dt Test Circuit

Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance current transformer
• dV/dt controlled by R g
• Driver same type as D.U.T.
• I SD controlled by duty factor “D”
• D.U.T. – device under test

VISHAY IRFB11N50A Power Mosfet - Fig. 14b

Driver gate drive
D.U.T. ISD waveform
Reverse recovery current
D.U.T. VDS waveform
Re-applied voltage
Inductor current
Body diode forward drop
Diode recovery dV/dt
Body diode forward current

Note
a. VGS = 5 V for logic level devices

Fig. 14 – For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91094.

S21-0867-Rev. C, 16-Aug-2021 Document Number: 91094

For technical questions, contact: hvm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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Revision: 01-Jan-2023 Document Number: 91000

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