VISHAY IRF830S Power MOSFET Owner’s Manual

VISHAY IRF830S Power MOSFET

PRODUCT SUMMARY

• I2PAK (TO-262)

• D2PAK (TO-263)

• N-Channel MOSFET

FEATURES

• Surface mount

• Available in tape and reel

• Dynamic dV/dt rating

• Repetitive avalanche rated

• Fast switching

• Ease of paralleling

• Simple drive requirements

• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912
  Note

• This datasheet provides information about parts that are RoHS-compliant and / or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details.

DESCRIPTION

Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness.
The D2PAK (TO-263) is a surface mount power package capable of accommodating die size up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2PAK (TO-263) is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface mount application.

ORDERING INFORMATION

Package| D2PAK (TO-263)| D2PAK (TO-263)| I2PAK (TO-262)
Lead (Pb)-free and halogen-free| SiHF830S-GE3| SiHF830STRL-GE3 a| SiHF830L-GE3
Lead (Pb)-free| IRF830SPbF| IRF830STRLPbF a| IRF830LPbF

Note

a. See device orientation.

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| LIMIT| UNIT
Drain-Source Voltage| VDS| 500| V
Gate-Source Voltage| VGS| ± 20
Continuous Drain Current| VGS at 10 V| TC = 25 °C| ID| 4.5| A
TC = 100 °C| 2.9
Pulsed Drain Current a| IDM| 18
Linear Derating Factor|  | 0.59| W/°C
Linear Derating Factor (PCB mount) e| 0.025
Single Pulse Avalanche Energy b| EAS| 280| mJ
Avalanche Current a| IAR| 4.5| A
Repetitive Avalanche Energy a| EAR| 7.4| mJ
Maximum Power Dissipation| TC = 25 °C| PD| 74| W
Maximum Power Dissipation (PCB mount) e| TA = 25 °C| 3.1
Peak Diode Recovery dV/dt c| dV/dt| 3.5| V/ns
Operating Junction and Storage Temperature Range| TJ, Tstg| -55 to +150| °C
Soldering Recommendations (Peak temperature) d| for 10 s|  | 300

Notes

• a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
• b. VDD = 50 V, starting TJ = 25 °C, L = 24 mH, Rg = 25 <, IAS = 4.5 A (see fig. 12).
• c. ISD < 4.5 A, dI/dt < 75 A/μs, VDD< VDS, TJ < 150 °C.
• d. 1.6 mm from case.
• e. When mounted on 1″ square PCB (FR-4 or G-10 material).

THERMAL RESISTANCE RATINGS

PARAMETER| SYMBOL| TYP.| MAX.| UNIT
Maximum Junction-to-Ambient| RthJA| –| 62| °C/W
Maximum Junction-to-Ambient (PCB mount) a| RthJA| –| 40
Maximum Junction-to-Case (Drain)| RthJC| –| 1.7

Note

• a. When mounted on 1″ square PCB (FR-4 or G-10 material).

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.| MAX.| UNIT
Static
Drain-Source Breakdown Voltage| VDS| VGS = 0, ID = 250 μA| 500| –| –| V
VDS Temperature Coefficient| DVDS/TJ| Reference to 25 °C, ID = 1 mA| –| 0.61| –| V/°C
Gate-Source Threshold Voltage| VGS(th)| VDS = VGS, ID = 250 μA| 2.0| –| 4.0| V
Gate-Source Leakage| IGSS| VGS = ± 20 V| –| –| ± 100| nA
Zero Gate Voltage Drain Current| IDSS| VDS = 500 V, VGS = 0 V| –| –| 25| μA
VDS = 400 V, VGS = 0 V, TJ = 125 °C| –| –| 250
Drain-Source On-State Resistance| RDS(on)| VGS = 10 V| ID = 2.7 Ab| –| –| 1.5| W
Forward Transconductance| gfs| VDS = 50 V, ID = 2.7 Ab| 2.5| –| –| S
Dynamic
Input Capacitance| Ciss| VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5| –| 610| –| pF
Output Capacitance| Coss| –| 160| –
Reverse Transfer Capacitance| Crss| –| 68| –
Total Gate Charge| Qg| VGS = 10 V| ID = 3.1 A, VDS = 400 V, see fig. 6 and 13b| –| –| 38| nC
Gate-Source Charge| Qgs| –| –| 5.0
Gate-Drain Charge| Qgd| –| –| 22
Turn-On Delay Time| td(on)| VDD = 250 V, ID = 3.1 A, Rg = 12 W, RD = 79 W, see fig. 10b| –| 8.2| –| ns
Rise Time| tr| –| 16| –
Turn-Off Delay Time| td(off)| –| 42| –
Fall Time| tf| –| 16| –
Internal Drain Inductance| LD| Between lead, D 6 mm (0.25″) from package and center of          G die contact S

| –| 4.5| –| nH
Internal Source Inductance| LS| –| 7.5| –
Gate Input Resistance| Rg| f = 1 MHz, open drain| 0.5| –| 2.7| W
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current| IS| MOSFET symbol D showing the integral reverse G p – n junction diode S
| –| –| 4.5| A
Pulsed Diode Forward Current| ISM| –| –| 18
Body Diode Voltage| VSD| TJ = 25 °C, IS = 4.5 A, VGS = 0 Vb| –| –| 1.6| V
Body Diode Reverse Recovery Time| trr| TJ = 25 °C, IF = 3.1 A, dI/dt = 100 A/μsb| –| 320| 640| ns
Body Diode Reverse Recovery Charge| Qrr| –| 1.0| 2.0| μC
Forward Turn-On Time| ton| Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Notes

• a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
• b. Pulse width < 300 μs; duty cycle < 2 %.

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

• Fig. 1 – Typical Output Characteristics, TC = 25 °C
  

• Fig. 2 – Typical Output Characteristics, TC = 150 °C
  

• Fig. 3 – Typical Transfer Characteristics
  

• Fig. 4 – Normalized On-Resistance vs. Temperature
  

• Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage
  

• Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage
  

• Fig. 7 – Typical Source-Drain Diode Forward Voltage
  

• Fig. 8 – Maximum Safe Operating Area
  

• Fig. 9 – Maximum Drain Current vs. Case Temperature
  

• Fig. 10a – Switching Time Test Circuit
  

• Fig. 10b – Switching Time Waveforms
  

• Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case
  

• Fig. 12a – Unclamped Inductive Test Circuit
  

• Fig. 12b – Unclamped Inductive Waveforms
  

• Fig. 12c – Maximum Avalanche Energy vs. Drain Current
  

Peak Diode Recovery dV/dt Test Circuit

Fig. 14 – For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91064.

TO-263AB (HIGH VOLTAGE)

ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured at the outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.

I2PAK (TO-262) (HIGH VOLTAGE)

ECN: S-82442-Rev. A, 27-Oct-08 DWG: 5977

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost extremes of the plastic body.
3. Thermal pad contour optional within dimension E, L1, D1, and E1.
4. Dimension b1 and c1 apply to base metal only.

RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead

• Recommended Minimum Pads Dimensions in Inches/(mm)
  

Disclaimer

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Revision: 01-Jan-2024
Document Number: 91000

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References

• Vishay Intertechnology: Passives & Discrete Semiconductors
• IRF830S, SiHF830S, IRF830L, SiHF830L MOSFETs | Vishay

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