VISHAY SiDR5802EP N-Channel 80 V (D-S) 175 °C MOSFET Owner’s Manual
- June 16, 2024
- VISHAY
Table of Contents
VISHAY SiDR5802EP N-Channel 80 V (D-S) 175 °C MOSFET
Product Information
Specifications
- Manufacturer: Vishay Siliconix
- Model: SiDR5802EP
- Configuration: N-Channel MOSFET
- Package: PowerPAK SO-8DC
- Lead (Pb)-free and halogen-free
- Maximum Drain-Source Voltage (VDS): 28.6 V
- Maximum Drain-Source On-State Resistance (RDS(on)): 0.0029 Ω at VGS = 10 V, 0.0040 Ω at VGS = 7.5 V
- Typical Gate Charge (Qg): 28 nC
- Maximum Continuous Drain Current (ID): 153 A
Features
- Single N-Channel MOSFET
- Lead (Pb)-free and halogen-free package
- High power dissipation capabilities
Applications
- Power electronics
- Switching circuits
- Motor control
Thermal Resistance Ratings
- Maximum Junction-to-Ambient: 15°C/W
- Maximum Junction-to-Case (Drain): 0.8°C/W
- Maximum Junction-to-Case (Source): 1.1°C/W
Product Usage Instructions
Installation
- Ensure proper handling of the lead (Pb)-free and halogen-free package.
- Mount the PowerPAK SO-8DC package on a 1 x 1 FR4 board using surface-mount techniques.
- Refer to the solder profile provided in the manual for proper soldering conditions.
- Do not use manual soldering with a soldering iron for leadless components.
Operating Conditions
- Maximum Junction Temperature (TJ): -55°C to +175°C
- Storage Temperature Range (Tstg): -55°C to +175°C
Electrical Characteristics
| Parameter | Symbol | Value |
|---|---|---|
| Drain-Source Breakdown Voltage | VDS | 28.6 V |
| Gate-Source Threshold Voltage | VGS(th) | 6.8 V |
| Drain-Source On-State Resistance | RDS(on) | 0.0029 Ω at VGS = 10 V, 0.0040 Ω at |
VGS = 7.5 V
Gate-Source Leakage| IGSS| 5.25 μA
Zero Gate Voltage Drain Current| IDSS| –
Forward Transconductance| gfs| –
Input Capacitance| Ciss| –
Output Capacitance| Coss| –
Reverse Transfer Capacitance| Crss| –
Total Gate Charge| Qg| 28 nC
Gate-Source Charge| Qgs| –
Gate-Drain Charge| Qgd| –
Output Charge| Qoss| –
Gate Resistance| Rg| –
Turn-On Delay Time| td(on)| –
Rise Time| tr| –
Turn-Off Delay Time| td(off)| –
Fall Time| tf| –
Continuous Source-Drain Diode Current| IS| –
Body Diode Voltage| VSD| –
Body Diode Reverse Recovery Time| trr| –
Body Diode Reverse Recovery Charge| Qrr| –
Reverse Recovery Fall Time| ta| –
Reverse Recovery Rise Time| tb| –
FAQ
Q: What is the maximum drain-source voltage (VDS) of the SiDR5802EP?
A: The maximum drain-source voltage (VDS) of the SiDR5802EP is 28.6 V.
Q: What is the maximum continuous drain current (ID) of the SiDR5802EP?
A: The maximum continuous drain current (ID) of the SiDR5802EP is 153 A.
Q: Can I use manual soldering with a soldering iron for leadless components?
A: No, manual soldering with a soldering iron is not recommended for leadless components like the SiDR5802EP.
PowerPAK® SO-8DC
FEATURES
- TrenchFET® Gen V power MOSFET
- Very low RDS – Qg figure-of-merit (FOM)
- Tuned for the lowest RDS – Qoss FOM
- 100 % Rg and UIS tested
- Material categorization: for definitions of compliance please see www.vishay.com/doc?99912
APPLICATIONS
- Synchronous rectification
- Primary side switch
- DC/DC converters
- OR-ing and hot swap switch
- Power supplies
- Motor drive control
- Battery management
PRODUCT SUMMARY
VDS (V)| 80
RDS(on) max. (W) at VGS = 10 V| 0.0029
RDS(on) max. (W) at VGS = 7.5 V| 0.0040
Qg typ. (nC)| 28
ID (A)| 153
Configuration| Single
ORDERING INFORMATION
Package| PowerPAK SO-8DC
Lead (Pb)-free and halogen-free| SIDR5802EP-T1-RE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER| SYMBOL| LIMIT| UNIT
Drain-source voltage| VDS| 80| V
Gate-source voltage| VGS| ± 20
Continuous drain current (TJ = 150 °C)
| TC = 25 °C|
ID
| 153|
A
TC = 70 °C| 128
TA = 25 °C| 34.2
TA = 70 °C| 28.6 a, b
Pulsed drain current (t = 100 μs)| IDM| 300
Continuous source-drain diode current| TC = 25 °C| IS| 136
TA = 25 °C| 6.8 a, b
Single pulse avalanche current| L = 0.1 mH| IAS| 45
Single pulse avalanche energy| EAS| 101| mJ
Maximum power dissipation
| TC = 25 °C|
PD
| 150|
W
TC = 70 °C| 105
TA = 25 °C| 7.5 a, b
TA = 70 °C| 5.25 a, b
Operating junction and storage temperature range| TJ, Tstg| -55 to +175| °C
Soldering recommendations (peak temperature) c, d| | 260
Notes
- a. Surface mounted on 1″ x 1″ FR4 board
- b. t = 10 s
- c. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection
- d. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components
THERMAL RESISTANCE RATINGS
PARAMETER| SYMBOL| TYPICAL| MAXIMUM| UNIT
Maximum junction-to-ambient a, b| t £ 10 s| RthJA| 15| 20|
°C/W
Maximum junction-to-case (drain)| Steady state| RthJC| 0.8| 1
Maximum junction-to-case (source)| Steady state| RthJC| 1.1| 1.4
Notes
- Surface mounted on 1″ x 1″ FR4 board
- Maximum under steady state conditions is 54 °C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.|
MAX.| UNIT
Static
Drain-source breakdown voltage| VDS| VGS = 0 V, ID = 1 mA| 80| –| –| V
VDS temperature coefficient| DVDS/TJ| ID = 10 mA| –| 62| –| mV/°C
VGS(th) temperature coefficient| DVGS(th)/TJ| ID = 250 μA| –| -8.7| –
Gate-source threshold voltage| VGS(th)| VDS = VGS, ID = 250 μA| 2| –| 4| V
Gate-source leakage| IGSS| VDS = 0 V, VGS = ± 20 V| –| –| 100| nA
Zero gate voltage drain current| IDSS| VDS = 64 V, VGS = 0 V| –| –| 1| μA
VDS = 64 V, VGS = 0 V, TJ = 70 °C| –| –| 15
Drain-source on-state resistance a| RDS(on)| VGS = 10 V, ID = 20 A| –| 0.0024|
0.0029| W
VGS = 7.5 V, ID = 20 A| –| 0.00325| 0.0040
Forward transconductance a| gfs| VDS = 15 V, ID = 20 A| –| 49| –| S
Dynamic b
Input capacitance| Ciss|
VDS = 40 V, VGS = 0 V, f = 1 MHz
| –| 3020| –|
pF
Output capacitance| Coss| –| 1285| –
Reverse transfer capacitance| Crss| –| 11| –
Total gate charge| Qg| VDS = 40 V, VGS = 10 V, ID = 20 A| –| 37.3| 60|
nC
VDS = 40 V, VGS = 7.5 V, ID = 20 A
| –| 28| 42
Gate-source charge| Qgs| –| 16.5| –
Gate-drain charge| Qgd| –| 3.2| –
Output charge| Qoss| VDS = 40 V, VGS = 0 V| –| 116| –
Gate resistance| Rg| f = 1 MHz| 0.4| 1.1| 1.9| W
Turn-on delay time| td(on)|
VDD = 50 V, RL = 2.5 W, ID @ 20 A, VGEN = 10 V, Rg = 1 W
| –| 16| 32|
ns
Rise time| tr| –| 11| 24
Turn-off delay time| td(off)| –| 26| 52
Fall time| tf| –| 12| 24
Turn-on delay time| td(on)|
VDD = 50 V, RL = 2.5 W, ID @ 20 A, VGEN = 7.5 V, Rg = 1 W
| –| 21| 46
Rise time| tr| –| 16| 32
Turn-off delay time| td(off)| –| 25| 50
Fall time| tf| –| 13| 26
Drain-Source Body Diode Characteristics
Continuous source-drain diode current| IS| TC = 25 °C| –| –| 136| A
Pulse diode forward current| ISM| | –| –| 300
Body diode voltage| VSD| IS = 5 A, VGS = 0 V| –| 0.73| 1.1| V
Body diode reverse recovery time| trr|
IF = 20 A, di/dt = 100 A/μs, TJ = 25 °C
| –| 60| 120| ns
Body diode reverse recovery charge| Qrr| –| 74| 148| nC
Reverse recovery fall time| ta| –| 28| –| ns
Reverse recovery rise time| tb| –| 32| –
Notes
- Pulse test; pulse width £ 300 μs, duty cycle £ 2 %
- Guaranteed by design, not subject to production testing
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
Note
a. The power dissipation PD is based on TJ max. = 175 °C, using junction-to-
case thermal resistance, and is more useful in settling the upper dissipation
limit for cases where additional heatsinking is used. It is used to determine
the current rating, when this rating falls below the package limit
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62010.
Disclaimer
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Revision: 01-Jan-2023
Document Number: 91000
References
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