VISHAY IRFZ34 Power MOSFET Owner’s Manual
- June 13, 2024
- VISHAY
Table of Contents
VISHAY IRFZ34 Power MOSFET
Instructions
The IRFZ34 is a power MOSFET designed for various commercial and industrial applications. 2. The TO-220AB package is recommended for use with power dissipation levels up to approximately 50 W. 3. Ensure proper thermal management as the IRFZ34 has thermal resistance ratings: – Maximum junction- to-ambient: 62 °C/W – Case-to-sink, flat, greased surface: 1.7 °C/W – Maximum junction-to-case (drain): 0.50 °C/W 4. The IRFZ34 is an N-channel MOSFET, meaning it can handle negative voltages and is commonly used for switching applications. 5. The maximum drain-source voltage (VDS) is 60 V. 6. The on- resistance (RDS(on)) of the IRFZ34 is 46 Ω, which determines its power ****
PRODUCT SUMMARY
VDS (V)| 60
RDS(on) (Ù)| VGS = 10 V| 0.050
Qg (Max.) (nC)| 46
Qgs (nC)| 11
Qgd (nC)| 22
Configuration| Single
Power MOSFET
FEATURES
- Dynamic dV/dt rating
- 175 °C operating temperature
- Fast switching
- Ease of paralleling
- Simple drive requirements
- Material categorization: for definitions of compliance please see www.vishay.com/doc?99912
Note
- This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details
DESCRIPTION
Third generation power MOSFETs from Vishay provide the designer with the best
combination of fast switching, ruggedized device design, low on-resistance and
cost-effectiveness.
The TO-220AB package is universally preferred for all commercial-industrial
applications at power dissipation levels to approximately 50 W. The low
thermal resistance and low package cost of the TO-220AB contribute to its wide
acceptance throughout the industry.
ORDERING INFORMATION
Package| TO-220AB
Lead (Pb)-free| IRFZ34PbF
Lead (Pb)-free and halogen-free| IRFZ34PbF-BE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
| SYMBOL| LIMIT|
UNIT
Drain-source voltage| VDS| 60| V
Gate-source voltage| VGS| ± 20
Continuous drain current| VGS at 10 V| TC = 25 °C| ID| 30|
A
TC = 100 °C| 21
Pulsed drain current a| IDM| 120
Linear derating factor| | 0.59| W/°C
Single pulse avalanche energy b| EAS| 200| mJ
Maximum power dissipation| TC = 25 °C| PD| 88| W
Peak diode recovery dV/dt c| dV/dt| 4.5| V/ns
Operating junction and storage temperature range| TJ, Tstg| -55 to +175| °C
Soldering recommendations (peak temperature) d| For 10 s| | 300 d
Mounting torque| 6-32 or M3 screw| | 10| lbf · in
1.1| N · m
Notes
- Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
- VDD = 25 V, starting TJ = 25 °C, L = 259 μH, Rg = 25 Ω, IAS = 30 A (see fig. 12)
- ISD ≤ 30 A, dI/dt ≤ 200 A/μs, VDD ≤ VDS, TJ ≤ 175 °C
- 1.6 mm from case
THERMAL RESISTANCE RATINGS
PARAMETER| SYMBOL| TYP.| MAX.|
UNIT
Maximum junction-to-ambient| RthJA| –| 62|
°C/W
Case-to-sink, flat, greased surface| RthCS| 0.50| –
Maximum junction-to-case (drain)| RthJC| –| 1.7
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.| MAX.|
UNIT
Static
Drain-source breakdown voltage| VDS| VGS = 0 V, ID = 250 μA| 60| –| –| V
VDS temperature coefficient| ÄVDS/TJ| Reference to 25 °C, ID = 1 mA| –| 0.065|
–| V/°C
Gate-source threshold voltage| VGS(th)| VDS = VGS, ID = 250 μA| 2.0| –| 4.0| V
Gate-source leakage| IGSS| VGS = ± 20 V| –| –| ± 100| nA
Zero gate voltage drain current| IDSS| VDS = 60 V, VGS = 0 V| –| –| 25| μA
VDS = 48 V, VGS = 0 V, TJ = 150 °C| –| –| 250
Drain-source on-state resistance| RDS(on)| VGS = 10 V| ID = 18 Ab| –| –|
0.050| Ù
Forward transconductance| gfs| VDS = 25 V, ID = 18 A| 9.3| –| –| S
Dynamic
Input capacitance| Ciss| VGS = 0 V, VDS = 25 V,
f = 1.0 MHz, see fig. 5
| –| 1200| –|
pF
Output capacitance| Coss| –| 600| –
Reverse transfer capacitance| Crss| –| 100| –
Total gate charge| Qg|
VGS = 10 V
|
ID = 30 A, VDS = 48 V,
see fig. 6 and 13b
| –| –| 46|
nC
Gate-source charge| Qgs| –| –| 11
Gate-drain charge| Qgd| –| –| 22
Turn-on delay time| td(on)|
VDD = 30 V, ID = 30 A,
Rg = 12 Ù, RD = 1.0 Ù, see fig. 10b
| –| 13| –|
ns
Rise time| tr| –| 100| –
Turn-off delay time| td(off)| –| 29| –
Fall time| tf| –| 52| –
Internal drain inductance| LD| Between lead, D
6 mm (0.25″) from package and center of
G
die contact
S
| –| 4.5| –|
nH
Internal source inductance| LS| –| 7.5| –
Drain-Source Body Diode Characteristics
Continuous source-drain diode current| IS| MOSFET symbol
D
showing the
integral reverse G
p – n junction diode S
| –| –| 30|
A
Pulsed diode forward current a| ISM| –| –| 120
Body diode voltage| VSD| TJ = 25 °C, IS = 30 A, VGS = 0 Vb| –| –| 1.6| V
Body diode reverse recovery time| trr| TJ = 25 °C, IF = 30 A, dI/dt = 100
A/ms| –| 120| 230| ns
Body diode reverse recovery charge| Qrr| –| 0.7| 1.4| nC
Forward turn-on time| ton| Intrinsic turn-on time is negligible (turn-on is
dominated by LS and LD)
Notes
-
* Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)- Pulse width ≤ 300 μs; duty cycle ≤ 2 %
TYPICAL CHARACTERISTICS ( 25 °C, unless otherwise noted)
Fig. 1Typical Output Characteristics, TC = 25 °C
Fig. 2Typical Output Characteristics, TC = 175 °C
Fig. 3 – Typical Transfer Characteristics
Fig. 4 – Normalized On-Resistance vs. Temperature
Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 – Typical Source-Drain Diode Forward Voltage
Fig. 8 – Maximum Safe Operating Area
Fig. 9 – Maximum Drain Current vs. Case Temperature
Fig. 10b – Switching Time Waveforms
Fig. 11 –
Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig. 12a – Unclamped Inductive Test Circuit
Fig. 12b – Unclamped Inductive Waveforms
Fig. 12c – Maximum Avalanche Energy vs. Drain Current
Fig. 13a – Basic Gate Charge Waveform
Fig. 13b – Gate Charge Test
Peak Diode Recovery dV/dt Test Circuit
Circuit layout considerations
- Low stray inductance
- Ground plane
- Low leakage inductance current transformer
- dV/dt controlled by Rg
- Driver same type as D.U.T.
- ISD controlled by duty factor “D”
- D.U.T. – device under test
Note
a. VGS = 5 V for logic level devices
Fig. 14 – For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91290.
| DIM. | MILLIMETERS | INCHES |
|---|---|---|
| MIN. | MAX. | MIN. |
| A | 4.24 | 4.65 |
| b | 0.69 | 1.02 |
| b(1) | 1.14 | 1.78 |
| c | 0.36 | 0.61 |
| D | 14.33 | 15.85 |
| E | 9.96 | 10.52 |
| e | 2.41 | 2.67 |
| e(1) | 4.88 | 5.28 |
| F | 1.14 | 1.40 |
| H(1) | 6.10 | 6.71 |
| J(1) | 2.41 | 2.92 |
| L | 13.36 | 14.40 |
| L(1) | 3.33 | 4.04 |
| Ø P | 3.53 | 3.94 |
| Q | 2.54 | 3.00 |
ECN: E21-0621-Rev. D, 04-Nov-2021 DWG: 6031
Note
M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM
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