VISHAY SiHF12N60E E Series Power MOSFET Owner’s Manual

: June 13, 2024
: VISHAY

Table of Contents

VISHAY SiHF12N60E E Series Power MOSFET
Product Information
E Series Power MOSFET
TYPICAL CHARACTERISTIC S (25 °C, unless otherwise noted)
TO-220 FULLPAK (High Voltage)
References
Read User Manual Online (PDF format)
Download This Manual (PDF format)

VISHAY SiHF12N60E E Series Power MOSFET

VISHAY-SiH-12N60E-E-Series-Power-MOSFET-product

Product Information

Product Name: SiHF12N60E
Manufacturer: Vishay Silicone
Product Type: E Series Power MOSFET
Package Type: TO-220 FULLPAK
Channel Type: N-Channel MOSFET
Drain-Source Voltage: 650 V
Gate-Source Voltage: 10 V
Linear Derating Factor: 0.38

www.vishay.com

E Series Power MOSFET

TO-220 FULLPAK

VISHAY-SiH-12N60E-E-Series-Power-MOSFET-02

PRODUCT SUMMARY

ORDERING INFORMATION

Package| TO-220 FULLPAK
Lead (Pb)-free and Halogen-free| SiHF12N60E-GE3
Lead (Pb)-free| SiHF12N60E-E3

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| LIMIT| UNIT
Drain-Source Voltage| VDS| 600| V
Gate-Source Voltage| VGS| ± 30
Continuous Drain Current (TJ = 150 °C) e| VGS at 10 V| TC = 25 °C| ID| 12|

A

TC = 100 °C| 7.8
Pulsed Drain Current a| IDM| 27
Linear Derating Factor| | 0.26| W/°C
Single Pulse Avalanche Energy b| EAS| 117| mJ
Maximum Power Dissipation| PD| 33| W
Operating Junction and Storage Temperature Range| TJ, Tstg| -55 to +150| °C
Drain-Source Voltage Slope| TJ = 125 °C| dV/dt| 70| V/ns
Reverse Diode dV/dt d| 5
Soldering Recommendations (Peak temperature) c| For 10 s| | 300| °C
Mounting Torque| M3 screw| | 0.6| Nm

Notes

Repetitive rating; pulse width limited by maximum junction temperature.
VDD = 50 V, starting TJ = 25 °C, L = 11.6 mH, Rg = 25 IAS = 4.5 A.
1.6 mm from case.
SD D, dI/dt = 100 A/μs, starting TJ = 25 °C.
Limited by maximum junction temperature.

FEATURES

Low figure-of-merit (FOM) Ron x Qg
Low input capacitance (Ciss)
Reduced switching and conduction losses
Ultra low gate charge (Qg)
Avalanche energy rated (UIS)
Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

APPLICATIONS

Server and telecom power supplies
Switch mode power supplies (SMPS)
Power factor correction power supplies (PFC)
Lighting
High-intensity discharge (HID)
Fluorescent ballast lighting
Industrial
Welding
Induction heating
Motor drives
Battery chargers
Renewable energy
Solar (PV inverters)

For technical questions, contact: hvm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

THERMAL RESISTANCE RATINGS

PARAMETER| SYMBOL| TYP.| MAX.| UNIT
Maximum Junction-to-Ambient| RthJA| –| 65| °C/W
Maximum Junction-to-Case (Drain)| RthJC| –| 3.8
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.| MAX.| UNIT
Static
Drain-Source Breakdown Voltage| VDS| VGS = 0 V, ID = 250 μA| 600| –| –| V
VDS Temperature Coefficient| DVDS/TJ| Reference to 25 °C, ID = 1 mA| –| 0.71| –| V/°C
Gate-Source Threshold Voltage (N)| VGS(th)| VDS = VGS, ID = 250 μA| 2| –| 4| V
Gate-Source Leakage| IGSS| VGS = ± 20 V| –| –| ± 100| nA
VGS = ± 30 V| –| –| ± 1| μA
Zero Gate Voltage Drain Current| IDSS| VDS = 600 V, VGS = 0 V| –| –| 1| μA
VDS = 480 V, VGS = 0 V, TJ = 125 °C| –| –| 10
Drain-Source On-State Resistance| RDS(on)| VGS = 10 V| ID = 6 A| –| 0.32| 0.38| W
Forward Transconductance| gfs| VDS = 40 V, ID = 8 A| –| 3.8| –| S
Dynamic
Input Capacitance| Ciss| VGS = 0 V, VDS = 100 V,

f = 1 MHz

| –| 937| –|

pF

VDS = 0 V to 480 V, VGS = 0 V

| –| 41| –
Effective Output Capacitance, Time Related b| Co(tr)| –| 136| –
Total Gate Charge| Qg|

VGS = 10 V

| ID = 6 A, VDS = 480 V| –| 29| 58| nC
Gate-Source Charge| Qgs| –| 6| –
Gate-Drain Charge| Qgd| –| 13| –
Turn-On Delay Time| td(on)| VDD = 480 V, ID = 6 A, VGS = 10 V, Rg = 9.1 W| –| 14| 28| ns
Rise Time| tr| –| 19| 38
Turn-Off Delay Time| td(off)| –| 35| 70
Fall Time| tf| –| 19| 38
Gate Input Resistance| Rg| f = 1 MHz, open drain| –| 1.1| –| W
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current| IS| MOSFET symbol D showing the integral reverse G p – n junction diode S| –| –| 12|

A

Pulsed Diode Forward Current| ISM| –| –| 48
Diode Forward Voltage| VSD| TJ = 25 °C, IS = 6 A, VGS = 0 V| –| –| 1.2| V
Reverse Recovery Time| trr| TJ = 25 °C, IF = IS = 6 A, dI/dt = 100 A/μs, VR = 25 V| –| 350| –| ns
Reverse Recovery Charge| Qrr| –| 4| –| μC
Reverse Recovery Current| IRRM| –| 19| –| A

Notes

Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.

TYPICAL CHARACTERISTIC S (25 °C, unless otherwise noted)

VISHAY-SiH-12N60E-E-Series-Power-MOSFET-03

VDS, Drain-to-Source Voltage (V)

Fig. 1 – Typical Output Characteristics

VDS, Drain-to-Source Voltage (V)

Fig. 2 – Typical Output Characteristics

Gate-to-Source Voltage (V)

Fig. 3 – Typical Transfer Characteristics

TJ, Junction Temperature (°C)

Fig. 4 – Normalized On-Resistance vs. Temperature

VDS, Drain-to-Source Voltage (V)

Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 – Coss and Eoss vs. VDS

Qg, Total Gate Charge (nC)

Fig. 7 – Typical Gate Charge vs. Gate-to-Source Voltage

VSD, Source-Drain Voltage (V)

Fig. 8 – Typical Source-Drain Diode Forward Voltage

VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified

Fig. 9 – Maximum Safe Operating Area

TJ, Case Temperature (°C)

Fig. 10 – Maximum Drain Current vs. Case Temperature

TJ, Junction Temperature (°C)

Fig. 11 – Temperature vs. Drain-to-Source Voltage

Fig. 12 – Normalized Thermal Transient Impedance, Junction-to-Case

Fig. 13 – Switching Time Test Circuit

Fig. 14 – Switching Time Waveforms

Fig. 15 – Unclamped Inductive Test Circuit

Fig. 16 – Unclamped Inductive Waveforms

Fig. 17 – Basic Gate Charge Waveform

Current sampling resistors

Fig. 18 – Gate Charge Test Circuit

Peak Diode Recovery dV/dt Test Circuit

Circuit layout considerations
Low stray inductance
Ground plane
Low leakage inductance current transformer
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. – device under test

Driver gate drive

Note VGS = 5 V for logic level devices

Fig. 19 – For N-Channel

TO-220 FULLPAK (High Voltage)

OPTION 1: FACILITY CODE = 9

| MILLIMETERS
---|---
DIM.| MIN.| NOM.| MAX.
A| 4.60| 4.70| 4.80
b| 0.70| 0.80| 0.91
b1| 1.20| 1.30| 1.47
b2| 1.10| 1.20| 1.30
C| 0.45| 0.50| 0.63
D| 15.80| 15.87| 15.97
e| 2.54 BSC
E| 10.00| 10.10| 10.30
F| 2.44| 2.54| 2.64
G| 6.50| 6.70| 6.90
L| 12.90| 13.10| 13.30
L1| 3.13| 3.23| 3.33
Q| 2.65| 2.75| 2.85
Q1| 3.20| 3.30| 3.40
Ø R| 3.08| 3.18| 3.28

Notes

To be used only for process drawing
These dimensions apply to all TO-220 FULLPAK lead frame versions 3 leads
All critical dimensions should C meet Cpk > 1.33
All dimensions include burrs and plating thickness
No chipping or package damage
Facility code will be the 1st character located at the 2nd row of the unit marking

OPTION 2: FACILITY CODE = Y

| MILLIMETERS| INCHES
---|---|---
DIM.| MIN.| MAX.| MIN.| MAX.
A| 4.570| 4.830| 0.180| 0.190
A1| 2.570| 2.830| 0.101| 0.111
A2| 2.510| 2.850| 0.099| 0.112
b| 0.622| 0.890| 0.024| 0.035
b2| 1.229| 1.400| 0.048| 0.055
b3| 1.229| 1.400| 0.048| 0.055
c| 0.440| 0.629| 0.017| 0.025
D| 8.650| 9.800| 0.341| 0.386
d1| 15.88| 16.120| 0.622| 0.635
d3| 12.300| 12.920| 0.484| 0.509
E| 10.360| 10.630| 0.408| 0.419
e| 2.54 BSC| 0.100 BSC
L| 13.200| 13.730| 0.520| 0.541
L1| 3.100| 3.500| 0.122| 0.138
n| 6.050| 6.150| 0.238| 0.242
Ø P| 3.050| 3.450| 0.120| 0.136
u| 2.400| 2.500| 0.094| 0.098
V| 0.400| 0.500| 0.016| 0.020
ECN: E19-0180-Rev. D, 08-Apr-2019 DWG: 5972

Notes

To be used only for process drawing
These dimensions apply to all TO-220 FULLPAK lead frame versions 3 leads
All critical dimensions should C meet Cpk > 1.33
All dimensions include burrs and plating thickness
No chipping or package damage
Facility code will be the 1st character located at the 2nd row of the unit marking

Disclaimer

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