VISHAY IRF830A Power MOSFET Instruction Manual

: June 10, 2024
: VISHAY

Table of Contents

FEATURES
APPLICATIONS
TYPICAL SMPS TOPOLOGIES
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Package Information
Legal Disclaimer Notice
- Disclaimer
Customer Support
References
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VISHAY IRF830A Power MOSFET

VISHAY IRF830A Power MOSFET

FEATURES

Low gate charge Qg results in simple drive requirement
Improved gate, avalanche and dynamic dV/dt ruggedness
Fully characterized capacitance and avalanche voltage and current
Effective Coss specified
Material categorization: for definitions of compliance please see www.vishay.com/doc?99912
Note
This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details

APPLICATIONS

Switch mode power supply (SMPS)
Uninterruptable power supply
High speed power Switching

TYPICAL SMPS TOPOLOGIES

Two transistor forward
Half bridge
Full bridge

PRODUCT SUMMARY

VDS (V)| 500
RDS(on) (Ù)| VGS = 10 V| 1.4
Qg max. (nC)| 24
Qgs (nC)| 6.3
Qgd (nC)| 11
Configuration| Single
ORDERING INFORMATION

Package| TO-220AB
Lead (Pb)-free| IRF830APbF
Lead (Pb)-free and halogen-free| IRF830APbF-BE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| LIMIT| UNIT
Drain-source voltage| VDS| 500| V
Gate-source voltage| VGS| ± 30
Continuous drain current| VGS at 10 V| TC = 25 °C| ID| 5.0|

A

TC = 100 °C| 3.2
Pulsed drain current a| IDM| 20
Linear derating factor| | 0.59| W/°C
Single pulse avalanche energy b| EAS| 230| mJ
Repetitive avalanche current a| IAR| 5.0| A
Repetitive avalanche energy a| EAR| 7.4| mJ
Maximum power dissipation| TC = 25 °C| PD| 74| W
Peak diode recovery dV/dt c| dV/dt| 5.3| V/ns
Operating junction and storage temperature range| TJ, Tstg| -55 to +150| °C
Soldering recommendations (peak temperature) d| For 10 s| | 300
Mounting torque| 6-32 or M3 screw| | 10| lbf · in
1.1| N · m

Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 18 mH, Rg = 25 Ω, IAS = 5.0 A (see fig. 12)
c. ISD ≤ 5.0 A, dI/dt ≤ 370 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case

THERMAL RESISTANCE RATINGS

PARAMETER| SYMBOL| TYP.| MAX.| UNIT
Maximum junction-to-ambient| RthJA| –| 62| °C/W
Case-to-sink, flat, greased surface| RthCS| 0.50| –
Maximum junction-to-case (drain)| RthJC| –| 1.7
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.| MAX.| UNIT
Static
Drain-source breakdown voltage| VDS| VGS = 0 V, ID = 250 μA| 500| –| –| V
VDS temperature coefficient| ÄVDS/TJ| Reference to 25 °C, ID = 1 mA| –| 0.60| –| V/°C
Gate-source threshold voltage| VGS(th)| VDS = VGS, ID = 250 μA| 2.0| –| 4.5| V
Gate-source leakage| IGSS| VGS = ± 30 V| –| –| ± 100| nA
Zero gate voltage drain current| IDSS| VDS = 500 V, VGS = 0 V| –| –| 25| μA
VDS = 400 V, VGS = 0 V, TJ = 125 °C| –| –| 250
Drain-source on-state resistance| RDS(on)| VGS = 10 V| ID = 3.0 A b| –| –| 1.4| Ù
Forward transconductance| gfs| VDS = 50 V, ID = 3.0 A b| 2.8| –| –| S
Dynamic
Input capacitance| Ciss| VGS = 0 V, VDS = 25 V,

f = 1.0 MHz, see fig. 5

| –| 620| –|

pF

see fig. 6 and 13 b

| –| –| 24|

nC

Gate-source charge| Qgs| –| –| 6.3
Gate-drain charge| Qgd| –| –| 11
Turn-on delay time| td(on)| VDD = 250 V, ID = 5.0 A,

Rg = 14 Ù, RD = 49 Ù, see fig. 10 b

| –| 10| –|

ns

Rise time| tr| –| 21| –
Turn-off delay time| td(off)| –| 21| –
Fall time| tf| –| 15| –
Gate input resistance| Rg| f = 1 MHz, open drain| 1.7| –| 10.7| Ù
Drain-Source Body Diode Characteristics
Continuous source-drain diode current| IS| MOSFET symbol showing the integral reverse p – n junction diode | –| –| 5.0|

A

Pulsed diode forward current a| ISM| –| –| 20
Body diode voltage| VSD| TJ = 25 °C, IS = 5.0 A, VGS = 0 V b| –| –| 1.5| V
Body diode reverse recovery time| trr| TJ = 25 °C, IF = 5.0 A, dI/dt = 100 A/μs b| –| 430| 650| ns
Body diode reverse recovery charge| Qrr| –| 1.62| 2.4| μC
Forward turn-on time| ton| Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 – Typical Output Characteristics

Typical Output Characteristics

Fig. 2 – Typical Output Characteristics

Typical Output Characteristics

Fig. 3 – Typical Transfer Characteristics

Typical Transfer Characteristics

Fig. 4 – Normalized On-Resistance vs. Temperature

Normalized On-Resistance vs. Temperature

Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage

Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage

Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 – Typical Source-Drain Diode Forward Voltage

Typical Source-Drain Diode Forward Voltage

Fig. 8 – Maximum Safe Operating Area

Maximum Safe Operating Area

Fig. 9 – Maximum Drain Current vs. Case Temperature

Maximum Drain Current vs. Case Temperature

Fig. 10a – Switching Time Test Circuit

Switching Time Test Circuit

Fig. 10b – Switching Time Waveforms

Switching Time Waveforms

Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case

Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 12a – Unclamped Inductive Test Circuit

Unclamped Inductive Test Circuit

Fig. 12b – Unclamped Inductive Waveforms

Unclamped Inductive Waveforms

Fig. 12c – Maximum Avalanche Energy vs. Drain Current

Maximum Avalanche Energy vs. Drain Current

Fig. 12d – Basic Gate Charge Waveform

Basic Gate Charge Waveform

Fig. 13a – Typical Drain-to-Source Voltage vs. Avalanche Current

Typical Drain-to-Source Voltage vs. Avalanche Current

Fig. 13b – Gate Charge Test Circuit

Gate Charge Test Circuit

Peak Diode Recovery dV/dt Test Circuit

Peak Diode Recovery dV/dt Test Circuit

Fig. 14 – For N-Channel

For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91061.

Package Information

TO-220-1

TO-220-1

DIM.	MILLIMETERS	INCHES
MIN.	MAX.	MIN.
A	4.24	4.65
b	0.69	1.02
b(1)	1.14	1.78
c	0.36	0.61
D	14.33	15.85
E	9.96	10.52
e	2.41	2.67
e(1)	4.88	5.28
F	1.14	1.40
H(1)	6.10	6.71
J(1)	2.41	2.92
L	13.36	14.40
L(1)	3.33	4.04
Ø P	3.53	3.94
Q	2.54	3.00

ECN: E21-0621-Rev. D, 04-Nov-2021 DWG: 6031

Note
• M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM

Legal Disclaimer Notice

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www.vishay.com/doc?91000