VISHAY Si5902BDC Dual N-Channel 30 V D-S MOSFET Instructions

Dual N-Channel 30 V (D-S) MOSFET
Si5902BDC
Vishay Siliconix

Si5902BDC Dual N-Channel 30 V D-S MOSFET

PRODUCT SUMMARY

V DS (V)| R DS(on) ( W )| I D (A)| Q g (Typ.)
30| 0.065 at VGS = 10 V| 4a| 2 nC
0.100 at VGS = 4.5 V| 4a

Ordering Information: Si5902BDC-T1-E3 (Lead (Pb)-free)
Si5902BDC-T1-GE3 (Lead (Pb)-free and Halogen-free)

FEATURES

• Halogen-free According to IEC 61249-2-21 Definition
• TrenchFET® Power MOSFET
• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

• Load Switch for Portable Applications
• DC/DC Converter

RoHS COMPLIANT
HALOGEN FREE Available

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter| Symbol| Limit| Unit
Drain-Source Voltage| VDS| 30| V
Gate-Source Voltage| VGS| ± 20
Continuous Drain Current (TJ = 150 °C)| TC = 25 °C| ID| 4a| A
TC = 85 °C| 3.8a
TA = 25 °C| 3.7b, c
TA = 85 °C| 2.6b, c
Pulsed Drain Current| IDM| 10
Continuous Source-Drain Diode Current| TC = 25 °C| IS| 2.6
TA = 25 °C| 1.3b, c

Maximum Power Dissipation

| TC = 25 °C| PD| 3.12|

W

TC = 85 °C| 2.0
TA = 25 °C| 1.5b, c
TA = 85 °C| 0.8b, c
Operating Junction and Storage Temperature Range| TJ, Tstg| – 55 to 150| °C
Soldering Recommendations (Peak Temperature)d,e| | 260
THERMAL RESISTANCE RATINGS

Parameter| Symbol| Typical| Maximum| Unit
Maximum Junction-to-Ambientb,f| t ≤5s| RthJA| 70| 85| °C/W
Maximum Junction-to-Foot (Drain)| Steady State| RthJF| 33| 40

Notes:
a. Package limited.
b. Surface mounted on 1″ x 1″ FR4 board.
c. t = 5 s.
d. See Solder Profile (www.vishay.com/ppg?73257). The 1206-8 ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 120 °C/W.

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter| Symbol| Test Conditions| Min.| Typ.| Max.| Unit
Static
Drain-Source Breakdown Voltage| VDS| VGS = 0 V, ID = 250 µA| 30| | | V
VDS Temperature Coefficient| DVDS/TJ| ID = 250 µA| | 27| | mV/°C
VGS(th) Temperature Coefficient| VGS(th)/TJ| | – 5|
Gate-Source Threshold Voltage| VGS(th)| VDS = VGS, ID = 250 µA| 1.5| | 3| V
Gate-Source Leakage| IGSS| VDS = 0 V, VGS = ± 20 V| | | ± 100| nA
Zero Gate Voltage Drain Current| IDSS| VDS = 30 V, VGS = 0 V| | | 1| µA
VDS = 30 V, VGS = 0 V, TJ = 85 °C| | | 5
On-State Drain Currenta| ID(on)| VDS ³ 5 V, VGS = 10 V| 10| | | A
Drain-Source On-State Resistancea| RDS(on)| VGS = 10 V, ID = 3.1 A| | 0.053| 0.065| W
VGS = 4.5 V, ID = 1 A| | 0.081| 0.100
Forward Transconductancea| gfs| VDS = 15 V, ID = 3.1 A| | 5| | S
Dynamic b
Input Capacitance| Ciss|

VDS = 15 V, VGS = 0 V, f = 1 MHz

| | 220| | pF
Output Capacitance| Coss| | 50|
Reverse Transfer Capacitance| Crss| | 25|
Total Gate Charge| Qg| VDS = 15 V, VGS = 10 V, ID = 3.6 A| | 4.5| 7| nC
VDS = 15 V, VGS = 4.5 V, ID = 3.6 A| | 2| 3
Gate-Source Charge| Qgs| | 0.7|
Gate-Drain Charge| Qgd| | 0.7|
Gate Resistance| Rg| f = 1 MHz| | 3| | W
Turn-On Delay Time| td(on)| VDD = 15 V, RL = 5.8 W
ID @ 2.6 A, VGEN = 4.5 V, Rg = 1 W| | 15| 25| ns
Rise Time| tr| | 80| 120
Turn-Off Delay Time| td(off)| | 12| 20
Fall Time| tf| | 25| 40
Turn-On Delay Time| td(on)| VDD = 15 V, RL = 5.8 W
ID @ 2.6 A, VGEN = 10 V, Rg = 1 W| | 4| 8
Rise Time| tr| | 12| 20
Turn-Off Delay Time| td(off)| | 10| 15
Fall Time| tf| | 5| 10
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current| IS| TC = 25 °C| | | 2.6| A
Pulse Diode Forward Current| ISM| | | | 10
Body Diode Voltage| VSD| IS = 2.6 A, VGS = 0 V| | 0.8| 1.2| V
Body Diode Reverse Recovery Time| trr| IF = 2.6 A, dI/dt = 100 A/µs, TJ = 25 °C| | 30| 50| ns
Body Diode Reverse Recovery Charge| Qrr| | 20| 40| nC
Reverse Recovery Fall Time| ta| | 23| | ns
Reverse Recovery Rise Time| tb| | 7|

Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

• The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit.

1206-8 ChipFET®

NOTES:

1. All dimensions are in millimeaters.
2. Mold gate burrs shall not exceed 0.13 mm per side.
3. Leadframe to molded body offset is horizontal and vertical shall not exceed 0.08 mm.
4. Dimensions exclusive of mold gate burrs.
5. No mold flash allowed on the top and bottom lead surface.

ECN: C-03528—Rev. F, 19-Jan-04 DWG: 5547

Dual-Channel 1206-8 ChipFET® Power MOSFET Recommended Pad Pattern and Thermal Performance

INTRODUCTION

New Vishay Siliconix ChipFETs in the leadless 1206-8 package feature the same outline as popular 1206-8 resistors and capacitors but provide all the performance of true power semiconductor devices. The 1206-8 ChipFET has the same footprint as the body of the LITTLE FOOT® TSOP-6, and can be thought of as a leadless TSOP-6 for purposes of visualizing board area, but its thermal performance bears comparison with the much larger SO-8.
This technical note discusses the dual ChipFET 1206-8 pin-out, package outline, pad patterns, evaluation board layout, and thermal performance.

PIN-OUT

Figure 1 shows the pin-out description and Pin 1 identification for the dual- channel 1206-8 ChipFET device. The pin-out is similar to the TSOP-6 configuration, with two additional drain pins to enhance power dissipation and thus thermal performance. The legs of the device are very short, again helping to reduce the thermal path to the external heatsink/pcb and allowing a larger die to be fitted in the device if necessary.

For package dimensions see the 1206-8 ChipFET package outline drawing (http://www.vishay.com/doc?71151).

BASIC PAD PATTERNS

The basic pad layout with dimensions is shown in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286). This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The pad pattern with copper spreading shown in Figure 2 improves the thermal area of the drain connections (pins 5 and 6, pins 7 and 8) while remaining within the confines of the basic footprint. The drain copper area is 0.0019 sq. in. or 1.22 sq. mm. This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the dual device.
The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further.
An example of this method is implemented on the Vishay Siliconix Evaluation Board described in the next section (Figure 3).

THE VISHAY SILICONIX EVALUATION BOARD FOR THE DUAL 1206-8
The dual ChipFET 1206-08 evaluation board measures 0.6 in by 0.5 in. Its copper pad pattern consists of an increased pad area around each of the two drain leads on the top-side— approximately 0.0246 sq. in. or 15.87 sq. mm—and vias added through to the underside of the board, again with a maximized copper pad area of approximately the board-size dimensions, split into two for each of the drains. The outer package outline is for the 8-pin DIP, which will allow test sockets to be used to assist in testing.
The thermal performance of the 1206-8 on this board has been measured with the results following on the next page. The testing included comparison with the minimum recommended footprint on the evaluation board-size pcb and the industry standard one-inch square FR4 pcb with copper on both sides of the board.

THERMAL PERFORMANCE

Junction-to-Foot Thermal Resistance (the Package Performance)
Thermal performance for the 1206-8 ChipFET measured as junction-to-foot thermal resistance is 30ºC/W typical, 40ºC/W maximum for the dual device. The “foot” is the drain lead of the device as it connects with the body. This is identical to the dual SO-8 package R jf performance, a feat made possible by shortening the leads to the point where they become only a small part of the total footprint area.

Junction-to-Ambient Thermal Resistance (dependent on pcb size)
The typical R ja for the dual-channel 1206-8 ChipFET is 90º C/W steady state, identical to the SO-8. Maximum ratings are 110ºC/W for both the 1206-8 and the SO-8. Both packages have comparable thermal performance on the 1” square pcb footprint with the 1206-8 dual package having a quarter of the body area, a significant factor when considering board area.

Testing

To aid comparison further, Figure 4 illustrates ChipFET 1206-8 dual thermal performance on two different board sizes and three different pad patterns.The results display the thermal performance out to steady state and produce a graphic account on how an increased copper pad area for the drain connections can enhance thermal performance. The measured steady state values of R ja for the Dual 1206-8 ChipFET are :

1. Minimum recommended pad pattern (see Figure  2) on the evaluation board size of 0.5 in x 0.6 in.| 185ºC/W
   ---|---
2. The evaluation board with the pad pattern described on Figure  3.| 128ºC/W
3. Industry standard 1” square pcb with maximum copper both sides.| 90ºC/W

The results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. In this example, a 57ºC/W reduction was achieved without having to increase the size of the board. If increasing board size is an option, a further 38ºC/W reduction was obtained by maximizing the copper from the drain on the larger 1” square PCB.

SUMMARY

The thermal results for the dual-channel 1206-8 ChipFET package display identical power dissipation performance to the SO-8 with a footprint reduction of 80%. Careful design of the package has allowed for this performance to be achieved. The short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the TSOP-6 body size.
ASSOCIATED DOCUMENT
1206-8 ChipFET Single Thermal performance, AN811, (http://www.vishay.com/doc?71126).

RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET®

Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non- infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts.
Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.
Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of any of the products, services or opinions of the corporation, organization or individual associated with the third-party website.
Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website or for that of subsequent links.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
© 2024 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 01-Jan-2024
Document Number: 91000
For technical questions, contact:
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Downloaded from Arrow.com.

References

• Vishay Intertechnology: Passives & Discrete Semiconductors
• Vishay Intertechnology: Passives & Discrete Semiconductors

Read User Manual Online (PDF format)

Read User Manual Online (PDF format)  >>

Download This Manual (PDF format)

Download this manual  >>