VISHAY IRFD220 Power Mosfet Owner’s Manual
- June 1, 2024
- VISHAY
Table of Contents
VISHAY IRFD220 Power Mosfet
FEATURES
- Dynamic dV/dt rating
- Repetitive avalanche rated
- For automatic insertion
- End stackable
- Fast switching
- Ease of paralleling
- Simple drive requirements
- Material categorization: for definitions of compliance please see www.vishay.com/doc?99912
DESCRIPTION
Third generation power MOSFETs from Vishay provide the designer with the best
combination of fast switching, ruggedized device design, low on-resistance and
cost-effectiveness.
The 4 pin DIP package is a low cost machine-insertable case style which can be
stacked in multiple combinations on standard 0.1″ pin centers. The dual drain
serves as a thermal link to the mounting surface for power dissipation levels
up to 1 W.
PRODUCT SUMMARY
VDS (V)| 200
RDS(on) (Ù)| VGS = 10 V| 0.80
Qg (Max.) (nC)| 14
Qgs (nC)| 3.0
Qgd (nC)| 7.9
Configuration| Single
ORDERING INFORMATION
Package| HVMDIP
Lead (Pb)-free| IRFD220PbF
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER| SYMBOL| LIMIT| UNIT
Drain-source voltage| VDS| 200| V
Gate-source voltage| VGS| ± 20
Continuous drain current| VGS at 10 V| TA = 25 °C| ID| 0.80| A
TA = 100 °C| 0.50
Pulsed drain current a| IDM| 6.4
Linear derating factor| | 0.0083| W/°C
Single pulse avalanche energy b| EAS| 260| mJ
Repetitive avalanche current a| IAR| 5.2| A
Repetitive avalanche energy a| EAR| 0.10| mJ
Maximum power dissipation| TA = 25 °C| PD| 1.0| W
Peak diode recovery dV/dt c| dV/dt| 5.0| V/ns
Operating junction and storage temperature range| TJ, Tstg| -55 to +150| °C
Soldering recommendations (peak temperature)| For 10 s| | 300d
Notes
- a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
- b. VDD = 50 V, starting TJ = 25 °C, L = 152 mH, Rg = 25 Ω, IAS = 1.6 A (see fig. 12)
- c. ISD ≤ 5.2 A, dI/dt ≤ 95 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
- d. 1.6 mm from case
THERMAL RESISTANCE RATINGS
PARAMETER| SYMBOL| TYP.| MAX.| UNIT
Maximum Junction-to-Ambient| RthJA| –| 120| °C/W
SPECIFICATIONS
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.|
MAX.| UNIT
Static
Drain-Source Breakdown Voltage| VDS| VGS = 0 V, ID = 250 μA| 200| –| –| V
VDS Temperature Coefficient| ÄVDS/TJ| Reference to 25 °C, ID = 1 mA| –| 0.29|
–| V/°C
Gate-Source Threshold Voltage| VGS(th)| VDS = VGS, ID = 250 μA| 2.0| –| 4.0| V
Gate-Source Leakage| IGSS| VGS = ± 20 V| –| –| ± 100| nA
Zero Gate Voltage Drain Current| IDSS| VDS = 200 V, VGS = 0 V| –| –| 25| μA
VDS = 160 V, VGS = 0 V, TJ = 125 °C| –| –| 250
Drain-Source On-State Resistance| RDS(on)| VGS = 10 V| ID = 0.48 Ab| –| –|
0.80| Ù
Forward Transconductance| gfs| VDS = 50 V, ID = 0.48 Ab| 0.60| –| –| S
Dynamic
Input Capacitance| Ciss| VGS = 0 V, VDS = 25 V,
f = 1.0 MHz, see fig. 5| –| 260| –| pF
Output Capacitance| Coss| –| 100| –
Reverse Transfer Capacitance| Crss| –| 30| –
Total Gate Charge| Qg| VGS = 10 V| ID = 4.8 A, VDS = 160 V, see fig.6 and 13b|
–| –| 14| nC
Gate-Source Charge| Qgs| –| –| 3.0
Gate-Drain Charge| Qgd| –| –| 7.9
Turn-On Delay Time| td(on)| VDD = 100 V, ID = 4.8 A, Rg = 18 Ù, RD = 19 Ù, see
fig. 10b| –| 7.2| –| ns
Rise Time| tr| –| 22| –
Turn-Off Delay Time| td(off)| –| 19| –
Fall Time| tf| –| 13| –
Internal Drain Inductance| LD| Between lead,
6 mm (0.25″) from
package and center of
die contact
| –| 4.0| –| nH
Internal Source Inductance| LS| –| 6.0| –
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current| IS| MOSFET symbol
showing the
integral reverse
p – n junction diode
| –| –| 0.80| A
Pulsed Diode Forward Currenta| ISM| –| –| 6.4
Body Diode Voltage| VSD| TJ = 25 °C, IS = 0.80 A, VGS = 0 Vb| –| –| 1.8| V
Body Diode Reverse Recovery Time| trr| TJ = 25 °C, IF = 4.8 A, dI/dt = 100
A/μsb| –| 150| 300| ns
Body Diode Reverse Recovery Charge| Qrr| –| 0.91| 1.8| μC
Forward Turn-On Time| ton| Intrinsic turn-on time is negligible (turn-on is
dominated by LS and LD)
Notes
- a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
- b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
-
Fig. 1 – Typical Output Characteristics, TA = 25 °C
-
Fig. 2 – Typical Transfer Characteristics
-
Fig. 1 – Typical Output Characteristics, TA = 150 °C
-
Fig. 3 – Normalized On-Resistance vs. Temperature
-
Fig. 4 – Typical Capacitance vs. Drain-to-Source Voltage
-
Fig. 6 – Typical Source-Drain Diode Forward Voltage
-
Fig. 5 – Typical Gate Charge vs. Gate-to-Source Voltage
-
Fig. 7 – Maximum Safe Operating Area
-
Fig. 8 – Maximum Drain Current vs. Ambient Temperature
-
Fig. 10a – Switching Time Test Circuit
-
Fig. 10b – Switching Time Waveforms
-
Fig. 9 – Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
-
Fig. 12a – Unclamped Inductive Test Circuit
-
Fig. 12b – Unclamped Inductive Waveforms
-
Fig. 12c – Maximum Avalanche Energy vs. Drain Current
-
Fig. 13a – Basic Gate Charge Waveform
-
Fig. 13b – Gate Charge Test Circuit
Peak Diode Recovery dV/dt Test Circuit -
Fig. 10 – For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91131.
HVM DIP (High voltage)
| INCHES| MILLIMETERS
---|---|---
DIM.| MIN.| MAX.| MIN.| MAX.
A| 0.310| 0.330| 7.87| 8.38
E| 0.300| 0.425| 7.62| 10.79
L| 0.270| 0.290| 6.86| 7.36
ECN: X10-0386-Rev. B, 06-Sep-10 DWG: 5974
Note
- Package length does not include mold flash, protrusions or gate burrs. Package width does not include interlead flash or protrusions.
Disclaimer
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References
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