VISHAY IRF840LCS Power MOSFET Owner’s Manual

: June 1, 2024
: VISHAY

Table of Contents

VISHAY IRF840LCS Power MOSFET
FAQ
FEATURES
DESCRIPTION
PRODUCT SUMMARY
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE RATINGS
SPECIFICATIONS
TYPICAL CHARACTERISTICS
Package Information
Legal Disclaimer Notice
References
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VISHAY IRF840LCS Power MOSFET

Specifications

Product Name: IRF840LCS, IRF840LCL, SiHF840LCS, SiHF840LCL
Manufacturer: Vishay Siliconix
Type: Power MOSFET
Package: I2PAK (TO-262), D2PAK (TO-263)
Configuration: N-Channel MOSFET
Drain-Source Voltage (VDS): 500V (VGS = 10V)
RDS(on): 39Ω
Maximum Gate Charge (Qg max.): 19nC
Features: Single configuration

Product Description These devices offer improved performance, ruggedness, and reliability for switching applications. Ordering Information Package Lead (Pb)-free and Halogen-free options available. Thermal Resistance Ratings

Maximum Junction-to-Ambient: 40°C/W (PCB mounted, steady-state)
Maximum Junction-to-Case (Drain): 1.0°C/W

Parameter Testing Conditions For detailed parameter testing conditions, please refer to the provided datasheet.

FAQ

Q: Are these MOSFETs RoHS-compliant? A: The datasheet provides information about RoHS-compliant and non-RoHS-compliant parts. Please refer to the datasheet for specific details.

Q: What is the recommended operating temperature range? A: The operating junction and storage temperature range can be found in the specifications section of the manual.

Q: Where can I find soldering recommendations for these MOSFETs? A: Soldering recommendations, including peak temperature and duration, are provided in the ordering information section of the manual.

FEATURES

Ultra low gate charge
Reduced gate drive requirement
Enhanced 30 V VGS rating
Reduced Ciss, Coss, Crss
Extremely high frequency operation
Repetitive avalanche rated
Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

Note

This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details

DESCRIPTION

This series of low charge power MOSFETs achiev e significantly lower gate charge then conventional Powe r MOSFETs. Utilizing the new LCDMOS (low charge device Power MOSFETs) technology, the device improvements ar e achieved without added product cost, allowing for reduce d gate drive requirements and total system savings. In addition, reduced switching losses and improved efficiency are achievable in a variety of high frequency applications. Frequencies of a few MHz at high current are possible usin g the new low charge Power MOSFETs. These device improvements combined with the proven ruggedness and reliability that characterize Power MOSFETs offer the designer a new power transistor standard for switching applications.

VISHAY-IRF840LCS-Power-MOSFET-FIG-1

PRODUCT SUMMARY

ORDERING INFORMATION

Note

a. See device orientation

ABSOLUTE MAXIMUM RATINGS

(TC = 25 °C, unless otherwise noted)

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| LIMIT| UNIT
Drain-Source Voltage| VDS| 500| V
Gate-Source Voltage| VGS| ± 30
Continuous Drain Current| VGS at 10 V| TC = 25 °C| ID| 8.0|

A

TC = 100 °C| 5.1
Pulsed Drain Current a, e| IDM| 28
Linear Derating Factor| | 1.0| W/°C
Single Pulse Avalanche Energy b, e| EAS| 510| mJ
Avalanche Current a| IAR| 8.0| A
Repetitive Avalanche Energy a| EAR| 13| mJ
Maximum Power Dissipation| TC = 25 °C| PD| 125| W
TA = 25 °C| 3.1
Peak Diode Recovery dV/dt c, e| dV/dt| 3.5| V/ns
Operating Junction and Storage Temperature Range| TJ, Tstg| -55 to +150| °C
Soldering Recommendations (Peak temperature) d| For 10 s| | 300

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 14 mH, Rg = 25 Ω, IAS = 8.0 A (see fig. 12)
c. ISD ≤ 8.0 A, dI/dt ≤ 100 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case
e. Uses IRF840LC, SiHF840LC data and test conditions

THERMAL RESISTANCE RATINGS

PARAMETER| SYMBOL| TYP.| MAX.| UNIT
Maximum Junction-to-Ambient (PCB mounted, steady-state) a| RthJA| –| 40|

°C/W

Maximum Junction-to-Case (Drain)| RthJC| –| 1.0

Note
a. When mounted on 1″ square PCB (FR-4 or G-10 material)

SPECIFICATIONS

(TJ = 25 °C, unless otherwise noted)

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.| MAX.| UNIT
Static
Drain-Source Breakdown Voltage| VDS| VGS = 0, ID = 250 μA| 500| –| –| V
VDS Temperature Coefficient| DVDS/TJ| Reference to 25 °C, ID = 1 mA c| –| 0.63| –| V/°C
Gate-Source Threshold Voltage| VGS(th)| VDS = VGS, ID = 250 μA| 2.0| –| 4.0| V
Gate-Source Leakage| IGSS| VGS = ± 20 V| –| –| ± 100| nA
Zero Gate Voltage Drain Current| IDSS| VDS = 500 V, VGS = 0 V| –| –| 25| μA
VDS = 400 V, VGS = 0 V, TJ = 125 °C| –| –| 250
Drain-Source On-State Resistance| RDS(on)| VGS = 10 V| ID = 4.8 A b| –| –| 0.85| W
Forward Transconductance| gfs| VDS = 50 V, ID = 4.8 A b| 4.0| –| –| S
Dynamic
Input Capacitance| Ciss| VGS = 0 V, VDS = 25 V,

f = 1.0 MHz, see fig. 5 c

| –| 1100| –|

pF

Output Capacitance| Coss| –| 170| –
Reverse Transfer Capacitance| Crss| –| 18| –
Total Gate Charge| Qg|

VGS = 10 V

|

ID = 8.0 A, VDS = 400 V,

see fig. 6 and 13 b, c

| –| –| 39|

nC

Gate-Source Charge| Qgs| –| –| 10
Gate-Drain Charge| Qgd| –| –| 19
Turn-On Delay Time| td(on)|

VDD = 250 V, ID = 8.0 A,

Rg = 9.1 W, RD = 30 W, see fig. 10 b, c

| –| 12| –|

ns

Rise Time| tr| –| 25| –
Turn-Off Delay Time| td(off)| –| 27| –
Fall Time| tf| –| 19| –
Gate Input Resistance| Rg| f = 1 MHz, open drain| 0.7| –| 3.7| W
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current| IS| MOSFET symbol

D

showing the

integral reverse

G

p – n junction diode

S

| –| –| 8.0|

A

Pulsed Diode Forward Current a| ISM| –| –| 28
Body Diode Voltage| VSD| TJ = 25 °C, IS = 8.0 A, VGS = 0 V b| –| –| 2.0| V
Body Diode Reverse Recovery Time| trr| TJ = 25 °C, IF = 8.0 A, dI/dt = 100 A/μs b, c| –| 490| 740| ns
Body Diode Reverse Recovery Charge| Qrr| –| 3.0| 4.5| μC
Forward Turn-On Time| ton| Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
c. Uses SiHF840LC data and test conditions

TYPICAL CHARACTERISTICS

(25 °C, unless otherwise noted)

VISHAY-IRF840LCS-Power-MOSFET-FIG-2 VISHAY-
IRF840LCS-Power-MOSFET-FIG-3

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91068.

Package Information

TO-263AB (HIGH VOLTAGE)

VISHAY-IRF840LCS-Power-MOSFET-FIG-9

Notes

Dimensioning and tolerancing per ASME Y14.5M-1994.
Dimensions are shown in millimeters (inches).
Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured at the outmost extremes of the plastic body at datum A.
Thermal PAD contour optional within dimension E, L1, D1 and E1.
Dimension b1 and c1 apply to base metal only.
Datum A and B to be determined at datum plane H.
Outline conforms to JEDEC outline to TO-263AB.

I2PAK (TO-262) (HIGH VOLTAGE)

VISHAY-IRF840LCS-Power-MOSFET-FIG-10

Notes

Dimensioning and tolerancing per ASME Y14.5M-1994.
Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost extremes of the plastic body.
Thermal pad contour optional within dimension E, L1, D1, and E1.
Dimension b1 and c1 apply to base metal only.

RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead

Legal Disclaimer Notice

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Revision: 01-Jan-2024

Document Number: 91000

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