VISHAY IRF510S Power Mosfet Instruction Manual

VISHAY IRF510S Power Mosfet

Product Information

• Product Name: IRF510S, SiHF510S
• Manufacturer: Vishay Siliconix
• Product Type: Power MOSFET
• Package Type: D2PAK (TO-263)
• Channel Type: N-Channel MOSFET

Product Summary:

Features:

• Third generation power MOSFETs
• Fast switching
• Ruggedized device design
• Low on-resistance
• Cost-effectiveness

Description:
The IRF510S and SiHF510S are power MOSFETs from Vishay Siliconix. These MOSFETs provide a combination of fast switching, ruggedized device design, low on-resistance, and cost-effectiveness. The D2PAK (TO-263) package is a surface-mount power package capable of accommodating die sizes up to HEX-4. It offers the highest power capability and the lowest possible on-resistance among existing surface-mount packages. The D2PAK (TO-263) is suitable for high current applications due to its low internal connection resistance and can dissipate up to 2.0 W in a typical surface-mount application.

Thermal Resistance Ratings:

Product Usage Instructions

1. Select the appropriate IRF510S or SiHF510S MOSFET based on the required VDS (drain-source voltage), RDS(on) (on-resistance), Qg max. (maximum gate charge), Qgs (gate-source charge), Qgd (gate-drain charge), and configuration.
2. Ensure proper thermal management by considering the thermal resistance ratings provided. Use appropriate heatsinks or cooling mechanisms to prevent overheating.
3. Follow the recommended soldering recommendations for peak temperature and duration when mounting the MOSFETs on a PCB.
4. Connect the drain, gate, and source terminals of the MOSFET according to the desired circuit configuration and application requirements.
5. Apply the appropriate VGS (gate-source voltage) to control the operation of the MOSFET. Refer to the gate-source threshold voltage (VGS(th)) for guidance.
6. Consider the maximum continuous drain current (ID) and pulsed drain current (IDM) limits to prevent overloading the MOSFET.
7. Take into account the linear derating factor when operating the MOSFET at high temperatures or in PCB mount configurations.
8. Ensure proper input and output capacitance, reverse transfer capacitance, and gate input resistance for optimal performance.
9. Take note of the maximum power dissipation and peak diode recovery dv/dt ratings to avoid exceeding the MOSFET’s capabilities.
10. Observe the operating junction and storage temperature range to prevent damage to the MOSFET.

Power MOSFET

PRODUCT SUMMARY

VDS (V)| 100
RDS(on) (W)| VGS = 10 V| 0.54
Qg max. (nC)| 8.3
Qgs (nC)| 2.3
Qgd (nC)| 3.8
Configuration| Single

FEATURES

• Surface-mount
• Available in tape and reel
• Dynamic dv/dt rating
• Repetitive avalanche rated
• 175 °C operating temperature
• Fast switching
• Ease of paralleling
• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

Note

• This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details

DESCRIPTION

Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness.
The D2PAK (TO-263) is a surface-mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface-mount package. The D2PAK (TO-263) is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface-mount application.

ORDERING INFORMATION

Package| D2PAK (TO-263)| D2PAK (TO-263)| D2PAK (TO-263)
Lead (Pb)-free and halogen-free| SiHF510S-GE3| SiHF510STRL-GE3 a| SiHF510STRR- GE3 a
Lead (Pb)-free| IRF510SPbF| IRF510STRLPbF a| IRF510STRRPbF a

Note

• See device orientation

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| LIMIT| UNIT
Drain-source voltage| VDS| 100| V
Gate-source voltage| VGS| ± 20
Continuous drain current| VGS at 10 V| TC = 25 °C| ID| 5.6|

A

TC = 100 °C| 4.0
Pulsed drain current a| IDM| 20
Linear derating factor| | 0.29| W/°C
Linear derating factor (PCB mount) e| 0.025
Single pulse avalanche energy b| EAS| 75| mJ
Avalanche current a| IAR| 5.6| A
Repetitive avalanche energy a| EAR| 4.3| mJ
Maximum power dissipation| TC = 25 °C| PD| 43| W
Maximum power dissipation (PCB mount) e| TA = 25 °C| 3.7
Peak diode recovery dv/dt c| dv/dt| 5.5| V/ns
Operating junction and storage temperature range| TJ, Tstg| -55 to +175| °C
Soldering recommendations (peak temperature) d| For 10 s| | 300

Notes

• Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
• VDD = 25 V, starting TJ = 25 °C, L = 4.8 mH, Rg = 25 , IAS = 5.6 A (see fig. 12)
• ISD  5.6 A, di/dt  75 A/μs, VDD  VDS, TJ  175 °C
• 1.6 mm from case
• When mounted on 1″ square PCB (FR-4 or G-10 material)

THERMAL RESISTANCE RATINGS

PARAMETER| SYMBOL| TYP.| MAX.| UNIT
Maximum junction-to-ambient| RthJA| –| 62|

°C/W

Maximum junction-to-ambient (PCB mount) a| RthJA| –| 40
Maximum junction-to-case (drain)| RthJC| –| 3.5

Note

• When mounted on 1″ square PCB (FR-4 or G-10 material)

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.| MAX.| UNIT
Static
Drain-source breakdown voltage| VDS| VGS = 0, ID = 250 μA| 100| –| –| V
VDS temperature coefficient| DVDS/TJ| Reference to 25 °C, ID = 1 mA| –| 0.12| –| V/°C
Gate-source threshold voltage| VGS(th)| VDS = VGS, ID = 250 μA| 2.0| –| 4.0| V
Gate-source leakage| IGSS| VGS = ± 20 V| –| –| ± 100| nA
Zero gate voltage drain current| IDSS| VDS = 100 V, VGS = 0 V| –| –| 25| μA
VDS = 80 V, VGS = 0 V, TJ = 150 °C| –| –| 250
Drain-source on-state resistance| RDS(on)| VGS = 10 V| ID = 3.4 A b| –| –| 0.54| W
Forward transconductance| gfs| VDS = 50 V, ID = 3.4 A b| 1.3| –| –| S
Dynamic
Input capacitance| Ciss| VGS = 0 V, VDS = 25 V,

f = 1.0 MHz, see fig. 5

| –| 180| –|

pF

Output capacitance| Coss| –| 81| –
Reverse transfer capacitance| Crss| –| 15| –
Total gate charge| Qg|

VGS = 10 V

|

ID = 5.6 A, VDS = 80 V,

see fig. 6 and fig. 13 b

| –| –| 8.3|

nC

Gate-source charge| Qgs| –| –| 2.3
Gate-drain charge| Qgd| –| –| 3.8
Turn-on delay time| td(on)|

VDD = 50 V, ID = 5.6 A,

Rg = 24 W, RD = 8.4 W, see fig. 10 b

| –| 6.9| –|

ns

Rise time| tr| –| 16| –
Turn-off delay time| td(off)| –| 15| –
Fall time| tf| –| 9.4| –
Gate input resistance| Rg| f = 1 MHz, open drain| 2.5| –| 11.6| W
Internal drain inductance| LD| Between lead,
6 mm (0.25″) from package and center of die contact|

G

|

D

S

| | –| 4.5| –|

nH

Internal source inductance| LS| –| 7.5| –
Drain-Source Body Diode Characteristics
Continuous source-drain diode current| IS| MOSFET symbol showing the integral reverse
p – n junction diode|

G

| |

D

S

| –| –| 5.6|

A

Pulsed diode forward current a| ISM| –| –| 20
Body diode voltage| VSD| TJ = 25 °C, IS = 5.6 A, VGS = 0 V b| –| –| 2.5| V
Body diode reverse recovery time| trr| TJ = 25 °C, IF = 5.6 A, di/dt = 100 A/μs b| –| 100| 200| ns
Body diode reverse recovery charge| Qrr| –| 0.44| 0.88| μC
Forward turn-on time| ton| Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Notes

• Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
• Pulse width  300 μs; duty cycle 2 %

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 – Typical Output Characteristics, TC = 25 °C

Fig. 2 – Typical Output Characteristics, TC = 175 °C

Fig. 3 – Typical Transfer Characteristics

Fig. 4 – Normalized On-Resistance vs. Temperature

Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 – Typical Source-Drain Diode Forward Voltage

Fig. 8 – Maximum Safe Operating Area

Fig. 9 – Maximum Drain Current vs. Case Temperature

Fig. 10a – Switching Time Test Circuit

Fig. 10b – Switching Time Waveforms

Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 12a – Unclamped Inductive Test Circuit

Fig. 12b – Unclamped Inductive Waveforms

Fig. 12c – Maximum Avalanche Energy vs. Drain Current

Fig. 13a – Basic Gate Charge Waveform

Fig. 13b – Gate Charge Test Circuit

Fig. 14 – For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91016.

TO-263AB (HIGH VOLTAGE)

| MILLIMETERS| INCHES| | | MILLIMETERS| INCHES
---|---|---|---|---|---|---
DIM.| MIN.| MAX.| MIN.| MAX.| DIM.| MIN.| MAX.| MIN.| MAX.
A| 4.06| 4.83| 0.160| 0.190| D1| 6.86| –| 0.270| –
A1| 0.00| 0.25| 0.000| 0.010| E| 9.65| 10.67| 0.380| 0.420
b| 0.51| 0.99| 0.020| 0.039| E1| 6.22| –| 0.245| –
b1| 0.51| 0.89| 0.020| 0.035| e| 2.54 BSC| 0.100 BSC
b2| 1.14| 1.78| 0.045| 0.070| H| 14.61| 15.88| 0.575| 0.625
b3| 1.14| 1.73| 0.045| 0.068| L| 1.78| 2.79| 0.070| 0.110
c| 0.38| 0.74| 0.015| 0.029| L1| –| 1.65| –| 0.066
c1| 0.38| 0.58| 0.015| 0.023| L2| –| 1.78| –| 0.070
c2| 1.14| 1.65| 0.045| 0.065| L3| 0.25 BSC| 0.010 BSC
D| 8.38| 9.65| 0.330| 0.380| L4| 4.78| 5.28| 0.188| 0.208
ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured at the outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.

RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead

Recommended Minimum Pads Dimensions in Inches/(mm)

Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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References

• applications.no
• Vishay Intertechnology: Passives & Discrete Semiconductors
• IRF510S, SiHF510S MOSFETs | Vishay
• IRF510S, SiHF510S MOSFETs | Vishay

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