VISHAY IRF9Z34 Power MOSFET Owner’s Manual

June 9, 2024
VISHAY

VISHAY IRF9Z34 Power MOSFET

VISHAY IRF9Z34 Power MOSFET 

PRODUCT SUMMARY

VDS (V) -60
RDS(on) (Ù) VGS = -10 V
Qg max. (nC) 34
Qgs (nC) 9.9
Qgd (nC) 16
Configuration Single

FEATURES

  • Dynamic dV/dt rating
  • Repetitive avalanche rated
  • P-channel
  • 175 °C operating temperature
  • Fast switching
  • Ease of paralleling
  • Simple drive requirements
  • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

Note

  • This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details.

DESCRIPTION

Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness.
The TO-220AB package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 W. The low thermal resistance and low package cost of the TO-220AB contribute to its wide acceptance throughout the industry.

ORDERING INFORMATION

Package| TO-220AB
Lead (Pb)-free| IRF9Z34PbF
Lead (Pb)-free and halogen-free| IRF9Z34PbF-BE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| LIMIT| UNIT
Drain-source voltage| VDS| -60| V
Gate-source voltage| VGS| ± 20
Continuous drain current| VGS at 10 V| TC = 25 °C| ID| -18| A
TC = 100 °C| -13
Pulsed drain current a| IDM| -72
Linear derating factor|  | 0.59| W/°C
Single pulse avalanche energy b| EAS| 370| mJ
Repetitive avalanche current a| IAR| -18| A
Repetitive avalanche energy a| EAR| 8.8| mJ
Maximum power dissipation| TC = 25 °C| PD| 88| W
Peak diode recovery dV/dt c| dV/dt| -4.5| V/ns
Operating junction and storage temperature range| TJ, Tstg| -55 to +175| °C
Soldering recommendations (peak temperature) d| For 10 s|  | 300
Mounting torque| 6-32 or M3 screw|  | 10| lbf · in
1.1| N · m

Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = -25 V, starting TJ = 25 °C, L = 1.3 mH, Rg = 25 Ω, IAS = -18 A (see fig. 12)
c. ISD ≤ -18 A, dI/dt ≤ 170 A/μs, VDD ≤ VDS, TJ ≤ 175 °C
d. 1.6 mm from case

THERMAL RESISTANCE RATINGS

PARAMETER| SYMBOL| TYP.| MAX.| UNIT
Maximum junction-to-ambient| RthJA| –| 62| °C/W
Case-to-sink, flat, greased surface| RthCS| 0.50| –
Maximum junction-to-case (drain)| RthJC| –| 1.7
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.| MAX.| UNIT
Static
Drain-source breakdown voltage| VDS| VGS = 0 V, ID = -250 μA| -60| –| –| V
VDS temperature coefficient| ÄVDS/TJ| Reference to 25 °C, ID = -1 mA| –| -0.060| –| V/°C
Gate-source threshold voltage| VGS(th)| VDS = VGS, ID = 250 μA| -2.0| –| -4.0| V
Gate-source leakage| IGSS| VGS = ± 20 V| –| –| ± 100| nA

Zero gate voltage drain current

|

IDSS

| VDS = -60 V, VGS = 0 V| –| –| -100|

μA

VDS = -48 V, VGS = 0 V, TJ = 150 °C| –| –| -500
Drain-source on-state resistance| RDS(on)| VGS = -10 V| ID = -11 A b| –| –| 0.14| Ù
Forward transconductance| gfs| VDS = -25 V, ID = -11 A b| 5.9| –| –| S
Dynamic
Input capacitance| Ciss| VGS = 0 V, VDS = -25 V,

f = 1.0 MHz, see fig. 5

| –| 1100| –|

pF

Output capacitance| Coss| –| 620| –
Reverse transfer capacitance| Crss| –| 100| –
Total gate charge| Qg|

VGS = -10 V

|

ID = -1 8 A, VDS = -48 V,

see fig. 6 and 13 b

| –| –| 34|

nC

Gate-source charge| Qgs| –| –| 9.9
Gate-drain charge| Qgd| –| –| 16
Turn-on delay time| td(on)|

VDD = -30 V, ID = -18 A,

Rg = 12 Ù, RD = 1.5 Ù, see fig. 10 b

| –| 18| –|

ns

Rise time| tr| –| 120| –
Turn-off delay time| td(off)| –| 20| –
Fall time| tf| –| 58| –

Gate input resistance

|

LD

| Between lead
6 mm (0.25″) from package and center of die contact |

|

4.5

|

|

nH

Internal drain inductance

| LS|

|

7.5

|

Internal source inductance| Rg| f = 1 MHz, open drain| 0.7| –| 3.9| Ù
Drain-Source Body Diode Characteristics
Continuous source-drain diode current| IS| MOSFET symbol  showing the integral reverse  p -n junction diode | –| –| -18|

A

Pulsed diode forward current a| ISM| –| –| -72
Body diode voltage| VSD| TJ = 25 °C, IS = -18 A, VGS = 0 V b| –| –| -6.3| V
Body diode reverse recovery time| trr| TJ = 25 °C, IF = -18 A, dI/dt = 100 A/μs b| –| 100| 200| ns
Body diode reverse recovery charge| Qrr| –| 0.28| 0.52| μC
Forward turn-on time| ton| Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 – Typical Output Characteristics, TC = 25 °C

Typical Output Characteristics, TC = 25 °C

Fig. 2 – Typical Output Characteristics, TC = 175 °C

Typical Output Characteristics, TC = 175 °C

Fig. 3 – Typical Transfer Characteristics

Typical Transfer Characteristics

Fig. 4 – Normalized On-Resistance vs. Temperature

Normalized On-Resistance vs. Temperature 

Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage

Typical Capacitance vs. Drain-to-Source Voltage 

Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage

Typical Gate Charge vs. Gate-to-Source Voltage 

Fig. 7 – Typical Source-Drain Diode Forward Voltage

Typical Source-Drain Diode Forward Voltage

Fig. 8 – Maximum Safe Operating Area

Maximum Safe Operating Area

Fig. 9 – Maximum Drain Current vs. Case Temperature

Maximum Drain Current vs. Case Temperature 

Fig. 10a – Switching Time Test Circuit

Switching Time Test Circuit 

Fig. 10b – Switching Time Waveforms

Switching Time Waveforms

Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case

Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 12a – Unclamped Inductive Test Circuit

Unclamped Inductive Test Circuit

Fig. 12b – Unclamped Inductive Waveforms

Unclamped Inductive Waveforms

Fig. 12c – Maximum Avalanche Energy vs. Drain Current

Maximum Avalanche Energy vs. Drain Current 

Fig. 13a – Basic Gate Charge Waveform

Basic Gate Charge Waveform

Fig. 13b – Gate Charge Test Circuit

Gate Charge Test Circuit

Peak Diode Recovery dV/dt Test Circuit

Peak Diode Recovery dV/dt Test Circuit

Fig. 14 – For P-Channel

For P-Channel 

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91092

Package Information

TO-220-1

Package Information

DIM.|

MILLIMETERS

|

INCHES

---|---|---
MIN.| MAX.| MIN.| MAX.
A| 4.24| 4.65| 0.167| 0.183
b| 0.69| 1.02| 0.027| 0.040
b(1)| 1.14| 1.78| 0.045| 0.070
c| 0.36| 0.61| 0.014| 0.024
D| 14.33| 15.85| 0.564| 0.624
E| 9.96| 10.52| 0.392| 0.414
e| 2.41| 2.67| 0.095| 0.105
e(1)| 4.88| 5.28| 0.192| 0.208
F| 1.14| 1.40| 0.045| 0.055
H(1)| 6.10| 6.71| 0.240| 0.264
J(1)| 2.41| 2.92| 0.095| 0.115
L| 13.36| 14.40| 0.526| 0.567
L(1)| 3.33| 4.04| 0.131| 0.159
Ø P| 3.53| 3.94| 0.139| 0.155
Q| 2.54| 3.00| 0.100| 0.118
ECN: E21-0621-Rev. D, 04-Nov-2021 DWG: 6031

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