VISHAY IRFD120 100V N Channel Dil Mosfet Instructions
- June 8, 2024
- VISHAY
Table of Contents
VISHAY IRFD120 100V N Channel Dil Mosfet
Power MOSFET
PRODUCT SUMMARY
VDS (V)| 100
RDS(on) (W)| VGS = 10 V| 0.27
Qg (Max.) (nC)| 16
Qgs (nC)| 4.4
Qgd (nC)| 7.7
Configuration| Single
FEATURES
- Dynamic dV/dt rating
- Repetitive avalanche rated
- For automatic insertion
- End stackable
- 175 °C operating temperature
- Fast switching
- Ease of paralleling
- Material categorization: for definitions of compliance please see www.vishay.com/doc?99912
DESCRIPTION
Third generation power MOSFETs from Vishay provide the designer with the best
combination of fast switching, ruggedized device design, low on-resistance and
cost-effectiveness.
The 4 pin DIP package is a low cost machine-insertab le case style which can
be stacked in multiple combinations on standard 0.1″ pin centers.
The dual drain serves as a thermal link to the mounting surface for power
dissipation levels up to 1 W.
ORDERING INFORMATION
Package| HVMDIP
Lead (Pb)-free| IRFD120PbF
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER| SYMBOL| LIMIT| UNIT
Drain-source voltage| VDS| 100|
V
Gate-source voltage| VGS| ± 20
Continuous drain current
| VGS at 10 V| TA = 25 °C| ID| 1.3|
A
TA = 100 °C| 0.94
Pulsed drain current a| IDM| 10
Linear derating factor| | 0.0083| W/°C
Single pulse avalanche energy b| EAS| 100| mJ
Repetitive avalanche current a| IAR| 1.3| A
Repetitive avalanche energy a| EAR| 0.13| mJ
Maximum power dissipation| TA = 25 °C| PD| 1.3| W
Peak diode recovery dV/dt c| dV/dt| 5.5| V/ns
Operating junction and storage temperature range| TJ, Tstg| -55 to +175|
°C
Soldering recommendations (peak temperature)| For 10 s| | 300d
Notes
- Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
- VDD = 25 V, starting TJ = 25 °C, L = 22 mH, Rg = 25 Ω, IAS = 2.6 A (see fig. 12)
- ISD ≤ 9.2 A, dI/dt ≤ 110 A/µs, VDD ≤ VDS, TJ ≤ 175 °C
- 1.6 mm from case
THERMAL RESISTANCE RATINGS
PARAMETER| SYMBOL| TYP.| MAX.| UNIT
Maximum Junction-to-Ambient| RthJA| –| 120| °C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER| SYMBOL| TEST CONDITIONS| MIN.| TYP.| MAX.| UNIT
Static
Drain-Source Breakdown Voltage| VDS| VGS = 0 V, ID = 250 μA| 100| –| –| V
VDS Temperature Coefficient| DVDS/TJ| Reference to 25 °C, ID = 1 mA| –| 0.13|
–| V/°C
Gate-Source Threshold Voltage| VGS(th)| VDS = VGS, ID = 250 μA| 2.0| –| 4.0| V
Gate-Source Leakage| IGSS| VGS = ± 20 V| –| –| ± 100| nA
Zero Gate Voltage Drain Current|
IDSS
| VDS = 100 V, VGS = 0 V| –| –| 25|
μA
VDS = 80 V, VGS = 0 V, TJ = 150 °C| –| –| 250
Drain-Source On-State Resistance| RDS(on)| VGS = 10 V| ID = 0.78 Ab| –| –|
0.27| W
Forward Transconductance| gfs| VDS = 50 V, ID = 0.78 Ab| 0.80| –| –| S
Dynamic
Input Capacitance| Ciss| VGS = 0 V VDS = 25 V
f = 1.0 MHz, see fig. 5
| –| 360| –|
pF
Output Capacitance| Coss| –| 150| –
Reverse Transfer Capacitance| Crss| –| 34| –
Total Gate Charge| Qg|
VGS = 10 V
|
ID = 9.2 A, VDS = 80 V
see fig. 6 and 13b
| –| –| 16|
nC
Gate-Source Charge| Qgs| –| –| 4.4
Gate-Drain Charge| Qgd| –| –| 7.7
Turn-On Delay Time| td(on)| VDD = 50 V, ID = 9.2 A
Rg = 18 W, RD = 5.2 W, see fig. 10b
| –| 6.8| –|
ns
Rise Time| tr| –| 27| –
Turn-Off Delay Time| td(off)| –| 18| –
Fall Time| tf| –| 17| –
Internal Drain Inductance
| LD| Between lead, D
6 mm (0.25″) from package and center of G die contact S|
–
|
4.0
|
–
|
nH
Internal Source Inductance| LS|
–
|
6.0
|
–
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
| IS| MOSFET symbol D
showing the integral reverse G
p – n junction diode S|
–
|
–
|
1.3
|
A
Pulsed Diode Forward Currenta| ISM|
–
|
–
|
10
Body Diode Voltage| VSD| TJ = 25 °C, IS = 1.3 A, VGS = 0 Vb| –| –| 2.5| V
Body Diode Reverse Recovery Time| trr| TJ = 25 °C, IF = 9.2 A, dI/dt = 100
A/μsb| –| 130| 260| ns
Body Diode Reverse Recovery Charge| Qrr| –| 0.65| 1.3| μC
Forward Turn-On Time| ton| Intrinsic turn-on time is negligible (turn-on is
dominated by LS and LD)
Notes
- Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
- Pulse width ≤ 300 µs; duty cycle ≤ 2 %
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
Peak Diode Recovery dV/dt Test Circuit
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91128.
HVM DIP (High voltage)
| INCHES| MILLIMETERS
---|---|---
DIM.| MIN.| MAX.| MIN.| MAX.
A| 0.310| 0.330| 7.87| 8.38
E| 0.300| 0.425| 7.62| 10.79
L| 0.270| 0.290| 6.86| 7.36
ECN: X10-0386-Rev. B, 06-Sep-10 DWG: 5974
Note
- Package length does not include mold flash, protrusions or gate burrs. Package width does not include interplead flash or protrusions.
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References
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