GOWIN IPUG1046-1.0E Adder Subtractor IP User Guide
- September 28, 2024
- GOWIN
Table of Contents
IPUG1046-1.0E Adder Subtractor IP
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Product Information
Specifications
Product Name: Gowin Adder Subtractor IP
Trademark: Guangdong Gowin Semiconductor
Corporation
Version: IPUG1046-1.0E
Date: 05/09/2024
Product Usage Instructions
About This Guide
Purpose: The purpose of Gowin Adder Subtractor
IP User Guide is to help users learn the features and usage of the
product by providing descriptions of functions, ports, timing, GUI,
and reference design.
Related Documents
The manual provides information based on Gowin Software
V1.9.8.11-1. Users are advised to adjust information according to
the software version in use.
Terminology and Abbreviations
ALU: Arithmetic Logical Unit
LUT: Look-up Table
IP: Intellectual Property
Support and Feedback
For technical support, customers can contact Gowin Semiconductor
via the website or email provided.
Product Features
Overview
Gowin Adder Subtractor IP is designed to perform integer
addition and subtraction operations with fewer logic resources. It
supports both signed and unsigned integer operations.
Features
- Supports addition and subtraction operations for both signed
and unsigned integers.
Gowin Adder Subtractor IP Overview
Logic Resource: Please refer to detailed specifications.
Delivered Documents: Design Files, Verilog Reference Design,
Verilog TestBench, Synthesis Software, Application Software (Gowin
Software V1.9.8.11 and above).
Note: Click on the provided link for supported
devices information.
FAQ (Frequently Asked Questions)
Q: What software version is recommended for using Gowin Adder
Subtractor IP?
A: It is recommended to use Gowin Software V1.9.8.11 and above
for optimal performance.
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Gowin Adder Subtractor IP
User Guide
IPUG1046-1.0E, 05/09/2024
Copyright © 2024 Guangdong Gowin Semiconductor Corporation. All Rights
Reserved.
is a trademark of Guangdong Gowin Semiconductor Corporation and is registered
in China, the U.S. Patent and Trademark Office, and other countries. All other
words and logos identified as trademarks or service marks are the property of
their respective holders. No part of this document may be reproduced or
transmitted in any form or by any means, electronic, mechanical, photocopying,
recording or otherwise, without the prior written consent of GOWINSEMI.
Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or
implied) and is not responsible for any damage incurred to your hardware,
software, data, or property resulting from usage of the materials or
intellectual property except as outlined in the GOWINSEMI Terms and Conditions
of Sale. GOWINSEMI may make changes to this document at any time without prior
notice. Anyone relying on this documentation should contact GOWINSEMI for the
current documentation and errata.
Revision History
Date 05/09/2024
Version 1.0E
Description Initial version published.
Contents
Contents
Contents ………………………………………………………………………………………………………………………………….. i List of Figures
…………………………………………………………………………………………………………………………. ii List of Tables
…………………………………………………………………………………………………………………………. iii 1 About This Guide
…………………………………………………………………………………………………………………. 1
1.1 Purpose ……………………………………………………………………………………………………………………… 1 1.2 Related
Documents ……………………………………………………………………………………………………… 1 1.3 Terminology and
Abbreviations ……………………………………………………………………………………… 1 1.4 Support and Feedback
…………………………………………………………………………………………………. 2 2
Overview………………………………………………………………………………………………………………………………. 3 2.1
Features……………………………………………………………………………………………………………………… 3 2.2 Max. Frequency
…………………………………………………………………………………………………………… 3 2.3 Latency
………………………………………………………………………………………………………………………. 3 2.4 Resource
Utilization……………………………………………………………………………………………………… 4 3 Functional Description
…………………………………………………………………………………………………………. 5 3.1 Structure and Function
…………………………………………………………………………………………………. 5 3.2 Data Setting
………………………………………………………………………………………………………………… 5 3.3 Function Selection
……………………………………………………………………………………………………….. 5 4 Port Description
…………………………………………………………………………………………………………………… 6 5 Timing Description
……………………………………………………………………………………………………………….. 7 6 GUI Configuration
………………………………………………………………………………………………………………… 8 6.1 IP
Generation………………………………………………………………………………………………………………. 8 6.2 Configuration
Interface ……………………………………………………………………………………………. 9 7 Reference Design
……………………………………………………………………………………………………………….. 10
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List of Figures
List of Figures
Figure 3-1 Gowin Adder Subtractor IP Interface…………………………………………………………………….. 5
Figure 5-1 Adder Subtractor Signal Timing …………………………………………………………………………… 7
Figure 6-1 Open the IP via Toolbar Icon……………………………………………………………………………….. 8
Figure 6-2 Gowin Adder Subtractor IP Configuration Interface
……………………………………………….. 9
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List of Tables
List of Tables
Table 1-1 Terminology and Abbreviations …………………………………………………………………………….. 2
Table 2-1 Gowin Adder Subtractor IP Overview …………………………………………………………………….. 3
Table 2-2 Resource Utilization …………………………………………………………………………………………….. 4 Table
4-1Gowin Adder Subtractor IP IO List …………………………………………………………………………. 6
IPUG1046-1.0E
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1 About This Guide
1.1 Purpose
1 About This Guide
1.1 Purpose
The purpose of Gowin Adder Subtractor IP User Guide is to help you learn the
features and usage of this product by providing the descriptions of functions,
ports, timing, GUI and reference design, etc. The software screenshots and the
supported products listed in this manual are based on Gowin Software
V1.9.8.11-1. As the software is subject to change without notice, some
information may not remain relevant and may need to be adjusted according to
the software that is in use.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI website. You can find
the related documents at www.gowinsemi.com: DS100, GW1N series of FPGA
Products Data Sheet DS117, GW1NR series of FPGA Products Data Sheet DS821,
GW1NS series of FPGA Products Data Sheet DS861, GW1NSR series of FPGA Products
Data Sheet DS102, GW2A series of FPGA Products Data Sheet DS226, GW2AR series
of FPGA Products Data Sheet DS971, GW2AN-18X & 9X Data Sheet DS976, GW2AN-55
Data Sheet SUG100, Gowin Software User Guide
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1 About This Guide
1.3 Terminology and Abbreviations
1.3 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown in Table 1-1.
Table 1-1 Terminology and Abbreviations
Terminology and Abbreviations
Meaning
ALU
Arithmetic Logical Unit
LUT
Look-up Table
IP
Intellectual Property
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive technical support.
If you have any questions, comments, or suggestions, please feel free to
contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: support@gowinsemi.com
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2 Overview
2.1 Features
2 Overview
Gowin Adder Subtractor IP is designed to realize integer addition and subtraction operations with less logic resources, supporting addition and subtraction operations for both signed and unsigned integers.
Table 2-1 Gowin Adder Subtractor IP Overview
Gowin Adder Subtractor IP
Logic Resource
Please refer to Table 2-2.
Delivered Doc.
Design Files
Verilog
Reference Design
Verilog
TestBench
Verilog
Test and Design Flow
Synthesis Software
GowinSythesis
Application Software
Gowin Software (V1.9.8.11 and above)
Note!
For the devices supported, you can click here to get the information.
2.1 Features
Supports addition and subtraction operations for both signed and unsigned
integers
The input data width ranges from 2 to 96 bits Supports input/output carry
Supports configurable output latency
2.2 Max. Frequency
The max. frequency of Gowin Adder and Subtractor IP is mainly determined by
speed grade of the selected devices.
2.3 Latency
IPUG1046-1.0E
The latency of Gowin Adder Subtractor IP is determined by the
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2 Overview
2.4 Resource Utilization
configuration parameters.
2.4 Resource Utilization
Gowin Adder and Subtractor IP can be implemented by Verilog. Its performance and resource utilization may vary when the design is employed in different devices, or at different densities, speeds, or grades.
Take GW2A-55 FPGA as an example. See Table 2-2 for the resource utilization. For the applications on the other GOWINSEMI devices, please refer to the later release.
Table 2-2 Resource Utilization
Device
Speed Grade Resource Name Resource Utilization
Registers
746
GW2A-55 C8/I7
LUTs ALUs
24 5609
I/O Buf
296
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3 Functional Description
3.1 Structure and Function
3 Functional Description
3.1 Structure and Function
Gowin Adder and Subtractor IP can realize addition and subtraction operations
for both signed and unsigned integers. And you can configure parameters as
required when generating the module. The diagram is as shown in Figure 3-1.
Figure 3-1 Gowin Adder Subtractor IP Interface
3.2 Data Setting
The input data can be configured as Signed and Unsigned on the GUI, and the
bit width of the input data can be configured separately. The maximum bit
width is 96 bits, and the minimum bit width is 2 bits.
3.3 Function Selection
You can select the operating mode through GUI, including Adder, Subtractor,
and Adder/Subtractor.
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4 Port Description
4 Port Description
The details of Gowin Adder and Subtractor IP I/O ports are shown in Table 4-1, and the interface diagram is as shown in Figure 3-1.
Table 4-1 Gowin Adder Subtractor IP IO List
Signal
I/O
Description
clk
Input
Clock signal (optional)
rstn
Input
Reset signal, active-low (optional)
data_a
Input
Input a
data_b
Input
Input b
cin
Input
Input carry (optional)
add_sub
Input
Select addition or subtraction (optional)
cout
Output
Output carry (optional)
result
Output
Output data
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5 Timing Description
5 Timing Description
This section describes the timing of Gowin Adder and Subtractor IP. Adder and
Subtractor signal timing is as shown in Figure 5-1.
Figure 5-1 Adder Subtractor Signal Timing
Note! data a width = 8, data b width = 8, Latency=10.
As shown in the diagram, when the latency is set to 10, the result of adding
or subtracting the first input data will be outputted after 10 clock cycles.
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6 GUI Configuration
6.1 IP Generation
6 GUI Configuration
6.1 IP Generation
Click “Tools > IP Core Generator > DSP and Mathematics” to call and configure
Adder Subtractor; toolbar icon is also available to open the IP as shown in
Figure 6-1.
Figure 6-1 Open the IP via Toolbar Icon
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6 GUI Configuration
6.2 Configuration Interface
6.2 Configuration Interface
Gowin Adder Subtractor IP configuration interface is shown in Figure 6-2.
Figure 6-2 Gowin Adder Subtractor IP Configuration Interface
This manual takes GW2A-55 chip and GW2A-LV55PG484C8/I7 part number as an
example.
You can configure the path of generated IP core folder in the “Create In” text
box.
You can configure the generated IP file name in the “File Name” text box.
You can configure the generated IP module name in the “Module Name” text box.
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7 Reference Design
7 Reference Design
Please refer to the related test cases in Gowin Adder Subtractor IP RefDesign.
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References
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- IP and Reference Design | Gowin
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