GOWIN IPUG769-1.1E Video Frame Buffer IP User Guide

Gowin Video Frame Buffer IP

User Guide

IPUG769-1.1E, 03/31/2023

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Disclaimer

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Revision History

• The description of “One Frame Address Space” parameter updated.
• Interface screenshots updated.

1 About This Guide

1.1 Purpose

The purpose of Gowin Video Frame Buffer IP is to help you learn the features and usage of Gowin Video Frame Buffer IP by providing the descriptions of features, functions, ports, timing, GUI and reference design, etc.

1.2 Related Documents

You can find the related documents at www.gowinsemi.com:

• DS100, GW1N series of FPGA Products Data Sheet
• DS117, GW1NR series of FPGA Products Data Sheet
• DS821, GW1NS series of FPGA Products Data Sheet
• DS861, GW1NSR series of FPGA Products Data Sheet
• DS881, GW1NSER series of FPGA Products Data Sheet
• DS891, GW1NRF series FPGA Products Data Sheet
• DS102, GW2A series of FPGA Products Data Sheet
• DS226, GW2AR series of FPGA Products Data Sheet
• DS961, GW2ANR series of FPGA Products Data Sheet
• DS976, GW2A-55 Data Sheet
• SUG100, Gowin Software User Guide

1.3 Terminology and Abbreviations

Table 1-1 shows the abbreviations and terminology used in this manual.

Table 1-1 Terminology and Abbreviations

1.4 Support and Feedback

Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Overview

2.1 Overview

Video Frame Buffer is used to receive parallel video input data, then cache it to memory, and output parallel video data at the same time, thus realizing the frame cache.
Gowin Video Frame Buffer IP is located between VESA standard video input/output interface and the memory interface controller IP, so that you can realize the video frame buffer based on memory.

Table 2-1 Gowin Video Frame Buffer IP

Gowin Video Frame Buffer IP

Logic Resource| Please refer to Table 2-2.
Delivered Doc.
Design Files| Verilog (encrypted)
Reference Design| Verilog
TestBench| Verilog
Test and Design Flow
Synthesis Software| GowinSynthesis
Application Software| Gowin Software (V1.9.7.01Beta and above)

Note!
For the devices supported, you can click here to get the information.

2.2 Features

• Supports VESA standard interface
• Supports 16/24/32 bits width
• Supports Gowin DDR3/PSRAM/HyperRAM Memory Interface IP

2.3 Resource Utilization

Gowin Video Frame Buffer IP can be implemented by Verilog. Its performance and resource utilization may vary when the design is employed in different devices, or at different densities, speeds, or grades. Take GW2A-18 FPGA as an instance, and the resource utilization is as shown in Table 2-2 and Table 2-3.

Table 2-2 Gowin Video Frame Buffer IP Resource Utilization

Table 2-3 Number of BSRAM

3 Functional Description

3.1 Block Diagram

Gowin Video Frame Buffer with IP is used to implement video input and output frame buffer based on external memory. The system diagram is as shown in Figure 3-1.

Figure 3-1 Block Diagram

3.2 Implementation Principle

3.2.1 Circuit

Video frame buffer system includes video source, video sink, video frame buffer, memory interface IP and external memory.
Video Frame Buffer includes four parts: input line buffer circuit, output line buffer circuit, base address circuit and arbiter circuit. The circuit structure is shown in Figure 3-2.

Figure 3-2 Block Diagram

The input line buffer circuit receives parallel video input data and caches it to the input FIFO line buffer. A write request is sent to the arbiter controller when the data in the FIFO reaches the preset threshold. When the arbiter controller responds to the request, it starts sending write data, addresses and commands.
The output line buffer circuit sets a read threshold and sends a request to the arbiter when the data in the output FIFO line buffer is below this threshold. When the arbiter responds to the request, the arbiter starts sending read commands and addresses and stores the received data in the output FIFO. When the output FIFO receives the DE signal of the output video, that is, the FIFO read enable signal, the output FIFO outputs the video data.
Three-frame buffer is usually used to avoid image tearing. A three-frame buffer includes one frame in write, one frame in read, and one frame in transition, which can be indicated by read/read pointers, and the read/write pointers respectively points to the start address of the frame buffer, that is, the base address of each frame. The base address control circuit is to control the read/write pointers. If you do not choose three frame buffer, read and write operations are in the same address space.
The arbiter circuit is to receive and arbitrate the memory read/write access requests from the input line buffer control circuit and the output line buffer control circuit. At the same time, the data interface of input line buffer control circuit and output line buffer control circuit is connected to the user data interface of memory interface IP.

3.2.2 Bandwidth Estimation

In order to make a video frame buffer system work properly, it must ensure that the video input/output bandwidths and memory bandwidths meet certain conditions. Take PSRAM memory as an example.
Assume that the input video horizontal resolution is Hin, vertical resolution is Vin, field frequency is Fvsin Hz, pixel bit width Nin bit; output video horizontal resolution is Hout, vertical resolution is Vout, field frequency is Fvsout, pixel bit width Nout bit; PSRAM clock frequency is Fclk MHz, data bit width D bit, double edge data transmission (i.e. data bandwidth needs to be multiplied by 2), read and write operation efficiency e%.
The bandwidth estimation method is as follows:

• Video input bandwidth Win = Hin Vin Fvsin *Nin (bit/s)
• Video output bandwidth Wout = Hout Vout Fvsout *Nout (bit/s)
• Memory theoretical bandwidth Wmem = Fclk D 2 (bit/s)
• Memory effective bandwidth Wmeme = Fclk D 2 * e% (bit/s)

Note!
The video frame buffer system can only work properly when Wmeme > (Win+Wout).

For example, the input video format 1280×720@60Hz, pixel format RGB565, pixel bit width 16bit; output video format 1280×720@60Hz, pixel format RGB565, pixel bit width 16bit; PSRAM clock frequency 166MHz, data bit width 16bit, read/write operation efficiency 60%.

• Win = 128072060*16= 884,736,000bit/s = 0.824Gbit/s
• Wout = 128072060*16= 884,736,000bit/s = 0.824Gbit/s
• Wmeme = 166MHz162*60% = 3187Mbit/s = 3.112Gbit/s

Note!
The efficiency of read/write operation depends on the bandwidth efficiency of PSRAM and video.

Since 3.112Gbit/s > (0.824Gbit/s + 0.824Gbit/s), the video frame buffer system can work properly.

3.3 Port List

The IO ports of Gowin Video Frame Buffer IP are shown in Figure 3-3.

Figure 3-3 Ports Diagram

Ports vary slightly depending on the parameters.
The details of I/O ports are shown in Table 3-1.

Table 3-1 I/O List

Video Frame Buffer IP as reference.
2| I_dma_clk| I | Memory W/R clock signal
3| I_wr_halt| I | Write pointer halt signal, 1: halt;
Valid in three-frame buffer mode
4| I_rd_halt| I | Read pointer halt signal, 1: halt;
Valid in three-frame buffer mode
5| I_vin0_clk| I | Input video clock signal
6| I_vin0_vs_n| I | Input vs, negative polarity.
7| I_vin0_de| I | Input data valid signal
8| I_vin0_data| I | Input video data signal
9| O_vin0_fifo_full| O| Input FIFO full signal
10| I_vout0_clk| I | Output video clock signal
11| I_vout0_vs_n| I | Output vs, negative polarity.
12| I_vout0_de| I | Output data read enable signal
13| O_vout0_den| O| Output data valid signal, 2 clock cycles delayed than I_vout0_de signal
14| O_vout0_data| O| Output video data signal
15| O_vout0_fifo_empty| O| Output FIFO empty signal
DDR3 interface (1)
16| I_cmd_ready| I | Memroy interface receives commands and addresses at high level
17| O_cmd| O| Command channel
18| O_cmd_en| O| Command and address enable signal
19| O_app_burst_number| O| Input port of continuous burst times
20| O_addr| O| Address input
21| I_wr_data_rdy| I | MC can receive the user data at high level
22| O_wr_data_en| O| wr_data enable signal
23| O_wr_data_end| O| High level indicates that the current clock cycle is the last cycle of this wr_data.
24| O_wr_data| O| Write data channel
25| O_wr_data_mask| O| Provides the mask signal for wr_data
26| I_rd_data_valid| I | rd_data valid signal
27| I_rd_data_end| I | High-level indicates the end cycle of the current rd_data.
28| I_rd_data| I | Read data channel
29| I_init_calib_complete| I | Initialization completed signal
PSRAM/HyperRAM Interface (2)
31| O_cmd| O| Command channel
32| O_cmd_en| O| Command and address enable signal
33| O_addr| O| Address input
34| O_wr_data| O| Write data channel
35| O_data_mask| O| Write data mask signal
36| I_rd_data_valid| I| Read data valid signal
37| I_rd_data| I| Read data channel
38| I_init_calib| I| Initialization completed signal

Note!

• For DDR3 ports description, you can see IPUG281, Gowin DDR3 Memory Interface IP User Guide.
• For PSRAM ports description, you can see IPUG943, Gowin PSRAM HS Memory Interface IP User Guide.
• For HyperRAM ports description, you can see IPUG944, Gowin HyperRam Memory Interface IP User Guide.

3.4 Parameter Configuration

Table 3-2 Gowin Video Frame Buffer IP Parameters

interface address width
3| Data Width| 32/64/128/256| 128| Memory interface IP user interface address width
4| Write Burst Length | 64/128| 64| Continuous burst write length
5| Read Burst Length| 64/128| 64| Continuous burst read length
6| Write Video Width| 16/24/32| 16| Write video data width
7| Read Video Width| 16/24/32| 16| Read video data width
8| One Frame Address Space| 0x00000001~0xFFFFFF FF| 0x00800000| One frame address space; the data bit width of address depends on memory type.
9| Use Three Frame Buffer| Yes/No| Yes| Use three frame buffer or not
10| Write FIFO Depth| 1024/2048/4096| 2048| Write FIFO depth, 32 bits
11| Read FIFO Depth| 1024/2048/4096| 2048| Read FIFO depth, 32 bits
12| Read FIFO Burst Mult| 2/4/8/16| 4| Read FIFO threshold value, which is a multiple of the read burst length.

3.5 Timing Description

This section describes the timing of Gowin Video Frame Buffer IP.

3.5.1 Video Interface Timing

The timing diagram of video interface is as shown in Figure 3-4.

Figure 3-4 Timing Diagram of Video Interface

Note!
I_vin0_de must be continuous within a line.

The timing diagram of video output interface is as shown in Figure 3-5.

Figure 3-5 Video Output Interface Timing

Note!
I_vout0_de must be continuous within a line.

3.5.2 Memory interface IP user interface Timing

• For the read and write timing of DDR3 memory interface IP, you can see IPUG281, Gowin DDR3 Memory Interface IP User Guide.
• For the read and write timing of PSRAM memory interface IP, you can see IPUG943, Gowin PSRAM HS Memory Interface IP User Guide.
• For the read and write timing of HyperRAM memory interface IP, you can see IPUG944, Gowin HyperRam Memory Interface IP User Guide.

4 GUI

You can invoke and configure Video Frame Buffer IP using IP core generator tool in the IDE.

1. Open IP Core Generator
After creating the project, click the “Tools” tab in the upper left, select and open the IP Core Generator from the drop-down list, as shown in Figure 4-1.

Figure 4-1 Open IP Core Generator

2. Open Video Frame Buffer IP Core
Click “Multimedia” and double click “Video Frame Buffer” to open the configuration interface, as shown in Figure 4-2.

Figure 4-2 Open Video Frame Buffer IP Core

3. Video Frame Buffer IP Core Ports
On the left of the configuration interface is the ports diagram of Video Frame Buffer IP core, as shown in Figure 4-3.

Figure 4-3 Ports Diagram of Video Frame Buffer IP

4. Configure Basic Information
See the project basic information in the configuration interface. Take GW2A- 18C and PBGA484 package as an example. The “Module Name” displays the top- level file name of the generated project, and the default is “Video_Frame_Buffer_Top”. You can modify the name. The “File Name” displays the folder generated by the IP core, which contains the files required by Video Frame Buffer IP core, and the default is “video_frame_buffer”. You can modify the path.”Create In” displays the path of IP core folder. The default is “project pathsrcvideo_frame_buffer”. You can modify the path.

Figure 4-4 Basic Information Configuration Interface

5. Options
You can configure memory type and video data format in the Options.

Figure 4-5 Options

5 Reference Design

This chapter introduces the usage and constructure of the reference design instance of Video Frame Buffer IP. Please see the Video Frame Buffer Reference Design for details at Gowinsemi website.

5.1 Design Instance 1

Take DK-VIDEO-GW2A18-PG484V1.2 as an example, and the diagram is as shown in Figure 5-1. For details of DK-VIDEO-GW2A18-PG484V1.2 development board, click here to get.

Figure 5-1 Reference Design 1 Diagram

In the reference design, the test pattern video signal is generated through testpattern module and input to Video Frame Buffer. Video Frame Buffer is connected to DDR3 controller IP, and syn_gen module generates output video timing. Read the video data from the Video Frame Buffer and output it to HDMI2 TX. Connect the HDMI cable to the display and you can see the internal test pattern. Test pattern includes color pattern, grid pattern, grayscale pattern and pure color pattern.

5.2 Design Instance 2

Take DK-GoAI-GW2AR18-QN88P V1.1 as an example, the diagram is as shown in Figure 5-2. For details of DK-GoAI-GW2AR18-QN88P V1.1 development board, click here to get.

Figure 5-2 Reference Design 2 Diagram

In the reference design, the test pattern video signal is generated through testpattern module and input to Video Frame Buffer. Video Frame Buffer is connected to PSRAM controller IP, and syn_gen module generates output video timing. Read the video data from the Video Frame Buffer and output it to the HDMI (J4) port. Connect the HDMI cable to the display and you can see the internal test pattern. Test pattern includes color pattern, grid pattern, grayscale pattern and pure color pattern.

5.3 Design Instance 3

Take DK-GoAI-GW1NSR4C-QN48 V1.1 as an example, the diagram is as shown in Figure 5-3. For details of DK-GoAI-GW1NSR4C-QN48 V1.1 development board, click here to get.

Figure 5-3 Reference Design 3 Diagram

In the reference design, the test pattern video signal is generated through test pattern module and input to Video Frame Buffer. Video Frame Buffer is connected to HyperRAM controller IP, and syn_gen module generates output video timing. Read the video data from the Video Frame Buffer and output it to the HDMI (J4) port. Connect the HDMI cable to the display and you can see the internal test pattern. Test pattern includes color pattern, grid pattern, grayscale pattern and pure color pattern.

6 File Delivery

The delivery files for the Gowin Video Frame Buffer IP include the documents, the design source code, and the reference design.

6.1 Documents

The documents mainly contain the user guide in PDF.

Table 6-1 Documents List

this one.

6.2 Design Source Code (Encryption)

The encrypted code file contains the RTL encrypted code of the Gowin Video Frame Buffer IP which is used for GUI in order to cooperate with Gowin software to generate the IP core required by you.

Table 6-2 Design Source Code List

with interface information, encrypted.

6.3 Reference Design

The Ref. Design folder contains the netlist file, user reference design, constraints file, top-level file and the project file, etc.

Table 6-3 Gowin VFB DDR3 RefDesign Folder List

The Ref. Design folder contains the netlist file, user reference design, constraints file, top-level file and the project file, etc.

Table 6-4 Gowin VFB PSRAM RefDesign Folder List

The Ref. Design folder contains the netlist file, user reference design, constraints file, top-level file and the project file, etc.

Table 6-5 Gowin VFB HyperRAM RefDesign Folder List

IPUG769-1.1E

References

• Home|GOWIN Semiconductor
• 广东高云半导体科技股份有限公司
• Home|GOWIN Semiconductor
• Gowin | Starter Kits and Development Boards | Support | GOWIN Semiconductor Corp.
• IP and Reference Design | Gowin

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