GOWIN IPUG548-1.11E SPDIF Receiver IP User Guide

Gowin SPDIF Receiver IP
User Guide
IPUG548-1.11E,04/22/2021

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Revision History

About This Guide

1.1 Purpose
Gowin SPDIF Receiver IP user guide describes the features, diagram, signal definition, parameter, operation, timing, and GUI of the product. It aims to help users learn the usage of Gowin SPDIF Receiver IP to accelerate product development.

1.2 Related Documents
The latest user guides are available on the Gowin website. See the related documents at www.gowinsemi.com.

• DS100, GW1N series of FPGA Products Data Sheet
• DS226, GW2AR series of FPGA Products Data Sheet
• DS102, GW2A series of FPGA Products Data Sheet

1.3 Terminology and Abbreviation
The terminology and abbreviations used in this manual are shown in Table 1-1.
Table 1-1 Abbreviations and Terminology

1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail:support@gowinsemi.com

Functional Description

2.1 Overview
SPDIF (Sony/Philips Digital Interface Format) is a kind of digital audio transmission interface. It usually outputs by using optical fiber and a coaxial line. The audio signal can be output to a decoder to maintain high fidelity, and it is widely used in DTS (Digital Theatre System).
In order to better serve FPGA users, reduce the difficulty of the system development and improve the speed of product development, a general SPDIF receiver controller with low power is designed to realize the function of SPDIF protocol and BMC encoding. Gowin SPDIF receiver IP can be applied to Gowin all FPGA products by using Gowin software.

2.1.1 Features

• The input working clock rate of the controller shall not be less than 512Fs (FS is the audio sampling rate);
• The data and clock are recovered by asynchronous sampling data with a high-speed clock；
• SPDIF recovery clock is an eighth of the input working clock of the controller;
• Supports 8KHz~192Khz sample rate;
• Supports bit width of 16bit~24bit;
• Supports IEC60958 (SPDIF) and AES3 PCM data transmission;
• Locked time not greater than 1Fs;
• Lower power consumption；
• Can be synthesized.

2.1.2 Performance Reference
The frequency of Gowin SPDIF Receiver IP is mainly determined by the max. frequency of the selected device. The specific device performance test is shown below.
Table 2-1 Performance Reference

2.2 System Diagram
The user logic of SPDIF Receiver controller mainly includes data, control, clock, reset, and other signals, and the transmitting only has input data.

2.3 Operating Pricinple
2.3.1 Block Diagram

The SPDIF Receiver controller includes SPDIF Unpacking, BMC decode, SPDIF Phase detect, and IDDR modules.

• Spdif Unpacking: Unpack the received Spdif data and transmit it to the user port;
• BMC decode: Decode the data transmitted from spdif;
• Spdif Phase detect: Detect the phase of the data transmitted from spdif;
• IDDR: Realize 1:2 serial-parallel conversion.

2.3.2 SPDIF Frame Structure

The SPDIF block is composed of 192 frames, and each frame is composed of 2 subframes, which are divided into Channel A and Channel B, respectively corresponding to the left and right channels. The length of subframe data is 32 bits, including Preamble, Aux. Data, Audio Data, and four bits information and check codes. A subframe is 4 Bytes, a frame is 8 Bytes, and a Block is 192 x 8 = 1536 Bytes.

1. Sync Preamble
   There are X, Y, and Z, which respectively indicate that the subframe is the beginning of Channel 1, Channel 2, and Block.

2. Auxiliary
   Currently, these four bits are used to store additional sample bits when the audio data exceeds 20 bits. For example, when 24 bits of sample data are to be transmitted, they are used to store the last four bits of audio data.

3. Audio Sample Word
   Store the actual sample data with a length of 20 bits and transmit it in LSB priority mode. When the sample is less than 20 bits, the unused LSB bits should be set to zero.

4. Validity Bit
   This bit is used to identify whether the data in the subframe is correct. If it sets to 0, it means that the data in the subframe is correct and can be received; otherwise, if the bit is 1, it means that the receiving end should ignore the subframe.

5. User Bit
   This bit is user-defined bit. Each group of samples transmits one bit. 192 groups of samples are transmitted to form 192 bits of information, and each channel has a group of 192 bits of user information.

6. Channel Status Bit
   This bit is the same as the user bit, and each group of samples transmits one bit. Finally, each channel has a group of 192 bits of channel status information. This 192 bits channel status information is divided into professional and consumer, which is determined by the first bit. When it is set to 1, it is in professional mode, and when it is set to 0, it is in consumer mode.

7. Parity Bit
   Parity Check is a simple error check method that uses Even Parity Check to determine if an odd number of bits is wrong.

2.3.3 BMC Encoding

Biphase Mark Code, or BMC, belongs to a phase modulation encoding method, which is used to mix clock signal and data signal for transmission. Its principle is to use a double clock frequency of transmission bit rate as a benchmark. An original data is split into two parts. When the data is 1, shift the electrical level (0-1 – > 1-0) for one time in the clock cycle to make the data into two data with different levels, to be10 or 01; When the data is 0, it does not need to shift levels, to be11 or 00. At the same time, the level at the beginning of each bit should be different from the level at the end of the previous bit, so that the receiver can determine the boundary of each bit.

2.3.4 Controller Operating Flow
SPDIF Receiver controller operation process is as follows:

1. Before the controller enters into the operation state, the user logic initializes the internal register and state machine by sending a reset signal.
2. The controller will recover the data received from IDDR by detecting 10 or 01 in the input clock;
3. BMC decodes the spdif data processed by the phase-detection module;
4. Carry out protocol analysis according to SPDIF protocol, and verify the data.
5. Send audio data, user bit, validity bit, channel status bit, and indicator signals to the user interface.

2.4 Signal Description
2.4.1 Signals of User Logic 

Table 2-2 Signals of User Logic

The I/O direction of all the signals takes the controller as a reference.

2| I_clk| I| Clock
3| O_audio_d| O| Audio data
4| O_user_bit| O| User bit data
5| O_chan_status_bit| O| Channel Status Bit data
6| O_spdif_data_en| O| Data valid signal
7| O_sub_frame0_flag| O| Sub Frame0 start flag
8| O_sub_frame1_flag| O| Sub Frame1 start flag
9| O_block_start_flag| O| Block start flag

10

| ****

O_parity_check_error

| ****

O

| Parity check error (high level indicating error code of current subframe)
11| O_lock_flag| O| Lock flag

2.4.2 Signals of Receiver
Table 2-3 Signal of Receiver

all the signals takes the controller as reference.

2.5 Parameter
This section introduces the GUI parameter of Gowin SPDIF Receiver IP.
Table 2-4 GUI Paramrter

2.6 Interface Timing
The user logic timing is as follows:

Note!

• After enabling the clock to enable the signal, the controller needs to be reset first;
• All input and output are aligned with the clock rising edge;
• All data enable and flag signals are in one clock cycle, and the data and data enable align to output.
• O_spdif_recovery_clk is 1/8 of the input working clock.

Application

3.1 Overview
This chapter describes how to configure parameters in the GUI and generate SPDIF Receiver IP module.

3.2 Application Diagram

3.3 GUI

1. Start the Gowin Software and open a project, as shown below:
2. Click “IP Core Generator” from the “Tools” menu, as shown below. Click “SPDIF RX” and use the default parameters. Click “OK” to generate SPDIF_RX_Top Module.
3. Instantiate the “SPDIF_RX_Top” module in the user application, as shown below.

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References

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