GOWIN IPUG781-1.4E USB 2.0 SoftPHY IP User Guide

: June 5, 2024
: GOWIN

Table of Contents

GOWIN IPUG781-1.4E USB 2.0 SoftPHY IP
About This Guide
Introduction
Functional Description
- USB 2.0 Soft PHY Block Diagram
- USB 2.0 Soft PHY External Circuit Connection
Signal Description
Interface Configuration
References
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Download This Manual (PDF format)

GOWIN IPUG781-1.4E USB 2.0 SoftPHY IP

About This Guide

Purpose

The purpose of Gowin USB 2.0 Soft PHY IP User Guide is to help you learn the features and usage of this IP by providing the descriptions of functions, signals, and interface configuration.

The latest user guides are available on the GOWINSEMI Website. You can find the related documents at: www.gowinsemi.com.

DS100, GW1N series of FPGA Products Data Sheet
DS117, GW1NR series of FPGA Products Data Sheet
DS821, GW1NS series of FPGA Products Data Sheet
DS871, GW1NSE series of FPGA Products Data Sheet
DS861, GW1NSR series of FPGA Products Data Sheet
DS891, GW1NRF series of FPGA Products Data Sheet
DS881, GW1NSER series of Bluetooth FPGA Products Data Sheet
DS102, GW2A series of FPGA Products Data Sheet
DS226, GW2AR series of FPGA Products Data Sheet
DS961, GW2ANR series of FPGA Products Data Sheet
DS976, GW2AN-55 Data Sheet
DS971, GW2AN-18X & 9X Data Sheet
SUG100, Gowin Software User Guide

Terminology and Abbreviations

The terminology and abbreviations used in this manual are as shown in Table 1-1.
Table 1-1 Terminology and Abbreviations

Terminology and Abbreviations|

Meaning

---|---

IP

| Intellectual Property
USB|

Universal Serial Bus

UTMI

| USB 2.0 Transceiver Microcell Interface
HS|

High Speed

FS

| Full Speed
LS|

Low Speed

NRZI

|

Non Return Zero Inverted

Support and Feedback

Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail: support@gowinsemi.com

Introduction

Overview

Gowin USB 2.0 Soft PHY IP is a USB physical layer transceiver that can support data reception and transmission at high speed (480Mbps), full speed (12Mbps), and low speed (1.5Mbps).
Table 2-1 Gowin USB 2.0 Soft PHY IP Overview

Gowin USB 2.0 Soft PHY IP

IP Core Application

Supported Devices|

Arora family
Little Bee family, excluding

GW1N-1/GW1N-1S/GW1NZ-1/GW1N-1P5 devices..

Logic Resource| Please refer to Table 2-3 and Table 2-4.

Delivered Doc.

Design Files| Verilog (encrypted)
Reference Design| Verilog
Test Bench| Verilog

Test and Design Flow

Synthesis Software| Gowin Synthesis
Application Software| Gowin Software (V1.9.8.05 and above)

Features

The features of Gowin USB 2.0 Soft PHY IP include:

Supports HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps).
Supports data serial and parallel conversion.
Supports bit stuffer and un stuffer.
Supports NRZI encoder and decoder.
Supports UTMI interface.

Using 5V Host Supply to Power USB Device Solution

Many solutions may to provide power to a USB device using the 5V provided over the cable from the Host without providing a separate power supply. To support cable powered USB device use cases, designers must be careful to ensure the total PCB BOM of the device does not exceed the current limitations of the USB Host as well as voltage drops over the cable.
The USB v2.0 specification, sections 7.1.2 and 7.3.2 provides information on current and voltage drop requirements expected to be supplied by a USB Host. If the total PCB BOM cannot meet the current and minimum voltage requirements of the specified host, the board can be powered with a separate power supply.
Table 2-2 DC Electrical Characteristics

Parameter

| Symbol| Condition| Min.| Max.|

Unit

---|---|---|---|---|---

Supply voltage

High-power Port

| VBUS| Note 2, Section 7.2.1| 4.75| 5.25|

V

Low-power Port

|

VBUS

| Note 2, Section 7.2.1| 4.40| 5.25|

V

Supply Current

High-power Hub Port (out)

mA

High-Power Function (in)

mA

Unconfigured Function/Hub (in)

mA

Suspended Low-power Device

µA

Resource Utilization

Gowin USB 2.0 Soft PHY IP can be implemented by Verilog. Its resource utilization may vary when the design is employed in different devices, or at different densities, speeds, or grades. Taking Gowin GW1NSR-4 and GW2AR-18 series of FPGA products as an instance, the resource utilization is as shown in Table 2-3 and Table 2-4.
Table 2-3 Resource Utilization (І)

Device| Speed Grade| Resource| Utilization|

Notes

---|---|---|---|---

GW1NSR-4

|

-5

|

LUT

| 384| ****

–

REG|

1109

ALU

| 13
BSRAM|

1

SSRAM

| 0
IO|

7

Table 2-4 Resource Utilization ( Ⅱ )

Device| Speed Grade| Resource| Utilization|

Notes

---|---|---|---|---

GW2AR-18

|

-5

| LUT| 384| ****

–

REG|

1109

ALU

| 13
BSRAM|

1

SSRAM

| 4
IO|

7

Functional Description

USB 2.0 Soft PHY Block Diagram

In the RX, after USB serial data goes through IDES8, NRZI decoder, bit un stuffer, shift Reg modules in turn, USB RX data is received, and then the data transmits to the upper module through UTMI interface. In the TX, after receiving the data transmitted by UTMI and then going through shift Reg, bit stuffer, NRZI encoder to generate the serial TX data stream, which then is sent to the USB interface via OSER8.

USB 2.0 Soft PHY External Circuit Connection

USB 2.0 Soft PHY supports high speed mode (480Mbps) . When the USB 2.0 Soft PHY is used as a USB slave device, the external circuit connection is as follows.

R1:1.5K ohm
R2:0 ohm
R3:0 ohm
R4:42 ohm
R5:42 ohm
R6:1.8K ohm
R7: 75 ohm(1N Series)，56 ohm(2A Series)
C1:1uF

Note!

You can see the followings for the IO port attribute constraints of GW2A series of FPGA.
- usb dxp io: IO_TYPE= LVCMOS33D PULL_MODE= NONE DRIVE=4;
- usb term dn_o: IO_TYPE=LVCMOS33 PULL_MODE= NONE DRIVE=8;
- usb term dp_o: IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8;
- usb pullup en_o: IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8;
- usb rxdn i: IO_TYPE=LVDS25 PULL_MODE=NONE;
- usb rxdp i: IO_TYPE=LVDS25 PULL_MODE=NONE.
You can see the followings for the IO port attribute constraints of GW1N series of FPGA.
usb dxp io: IO_TYPE= LVCMOS33D PULL_MODE= NONE DRIVE=8;
usb term dn o: IO_TYPE=LVCMOS33 PULL_MODE= NONE DRIVE=16;
usb term dp o: IO_TYPE=LVCMOS33 PULL_MODE= NONE DRIVE=16;
usb pullup en o: IO_TYPE=LVCMOS33 PULL_MODE= NONE DRIVE=8;
usb rxdn i: IO_TYPE=LVDS25 PULL_MODE=NONE;
usb rxdp i: IO_TYPE=LVDS25 PULL_MODE=NONE.
All signals related to the USB interface on the FPGA are recommended to be placed in one Bank, using adjacent assignment, and powering the I/O Bank at 3.3V
It is required that usb dxp io differential exists and is not used for the adjacent differential pair in the same Bank. Taking GW1NSR-4 as an example, Figure 3-3 shows the GW1NSR-4 Pinout. If the usb dxp io differential pair is located at G5, H5 (i.e. IOR11A/IOR11B) in the diagram, it will cause the project to report an error when implementing synthesis and layout with Gowin Software, as the adjacent differential pin IOR10A/IOR10B does not exist. If usb dxp io differential pair is located at G6/H6 (i.e. IOR3A/IOR3B), the project will synthesize and layout successfully with Gowin Software, as the adjacent differential pair exists.

Signal Description

A description of Gowin USB 2.0 Soft PHY IP signals is as shown in Table 4-1.

No.	Signal Name	I/O	Data Width	Description

1

| clk i| I| 1| Input clock signal (60MHz)

2

| fclk i| I| 1| Input clock signal (480MHz)

3

| rest i| I| 1| Asynchronous reset signal resets the state machine inside of PHY.

4

| pll locked i| I| 1| pll lock signal generating fclk i

5

| ****

utmi data out i

| ****

I

| ****

8

| Data input, 8-bit parallel data transmit bus.

6

| ****

utmi txvalid i

| ****

I

| ****

1

| Transmit data valid indicator, active-high.
7| utmi txready o| O| 1| Transmit data ready signal, indicating that PHY can receive the data to be transmitted from the controller end.
8| utmi data in o| O| 8| Data output, 8-bit parallel data receive bus.
9| utmi rxactive o| O| 1| Rx data active, indicating that PHY detects the SYNC signal and then starts receiving data.
10| utmi rxvalid o| O| 1| Rx data valid, active-high.
11| utmi rxerro o| O| 1| Receive data error, active high indicates receive error.

No.

| Signal Name| I/O| Data Width|

Description

---|---|---|---|---
12| utmi linestate o| O| 2| Line status of receive end: DM DP 2’b00：SE0
2’b01：”J”
2’b10：”K”
2’b11：SE1
13| utmi opmode i| I| 2| Operation mode selection signal: 2’b00: Normal
2’b01: No driver
2’b10: Disable bit stuffing and NRZI encoding
2’B11: Reserved

14

| ****

utmi xcvrselect i

| ****

I

| ****

2

| Transfer mode selection signal: 2’b00: HS Transfer
2’b01: FS Transfer
2’b10: LS Transfer 2’B11: Reserved
15| utmi term select i| I| 1| Termination Selection:
1’ b0: HS termination enable
1’ b1: FS / LS termination enable
16| usb dxp io| I/O| 1| USB data signal Data+
17| usb dxn io| I/O| 1| USB data signal Data-
18| usb rxdp i| I| 1| USB data signal Data+ input
19| usb rxdn i| I| 1| USB data signal Data- input
20| usb pullup en o| O| 1| 1.5K resistor pull-up control on USB data signal Data+
21| usb term dp o| I/O| 1| Termination resistor control of USB data signal Data+
22| usb term dn o| I/O| 1| Termination resistor control of USB data signal Data-

Interface Configuration

Selecting “Tools > IP Core Generator” in Gowin Software, you call and configure USB 2.0 SoftPHY.

Open IP Core Generator
After creating the project, you can click the “Tools” tab in the upper left, select and open the IP Core Generator via the drop-down list,
Open USB 2.0 Soft PHY IP Core
Select “Soft IP Core > Interface and Interconnect > USB 2.0 IP”,. Double-click to open the configuration interface.
USB 2.0 Soft PHY IP Core Configuration Interface
Figure 5-3 shows the USB 2.0 Soft PHY IP core configuration interface. The ports diagram is on the left of the configuration interface. Options are on the right.
- You can configure the file name in File Name.
- You can configure the top module name in Module Name.