Laird BL653 Series Bluetooth 5.1 802.15.4 NFC Module User Manual

: June 15, 2024
: Laird

Table of Contents

Laird BL653 Series Bluetooth 5.1 802.15.4 NFC Module
Product Information
FAQs
Copyright 2022 Laird Connectivity
Proximity Detection
Configurable Resolution
Calibration
Test Conditions
References
Read User Manual Online (PDF format)
Download This Manual (PDF format)

Laird BL653 Series Bluetooth 5.1 802.15.4 NFC Module

Laird-BL653-Series-Bluetooth-5.1-802.15.4-NFC-Module-
image

Product Information

The product is a Bluetooth module with version 2.5. It offers multiple programming options and supports 802.15.4 (Thread) radio. The module can be used with external or internal antennas. It has a programmable Tx power range of +8 dBm to -20 dBm, with an additional option of -40 dBm. The Rx sensitivity is -96 dBm (1 Mbps) and -103 dBm (125 kbps). The module has ultra-low power consumption, with a peak Rx current of 4.6 mA (DCDC on).

Specifications

Version: 2.5
Date: 10 Aug 2022
Contributor(s): Raj Khatri, Maggie Teng, Ryan Urness, Dave Drogowski, Andrew Chen
Approver: Jonathan Kaye

Usage Instructions

1. Installation

To use the Bluetooth module, follow these steps:

Ensure you have the necessary tools and equipment.
Choose the appropriate antenna type (external or internal) based on your requirements.
Connect the module to your device using UART, GPIO, ADC, PWM, FREQ output, or timers.
Install the necessary software development kit (SDK) based on your programming preference (smartBASIC or Nordic SDK).

2. Programming

The Bluetooth module supports two programming options: smartBASIC and Nordic SDK.

smartBASIC: For customers using smartBASIC, refer to the smartBASIC extensions guide available from the BL653 product page on the Laird Connectivity website.
Nordic SDK: For customers using the Nordic SDK, refer to www.nordicsemi.com for source code, precompiled libraries, and application examples.

3. Power Consumption

The Bluetooth module has ultra-low power consumption. The peak Rx current is 4.6 mA (DCDC on). Refer to Note 1 in the Power Consumption section for more details.

FAQs

Q1: What is the version of the Bluetooth module?

A1: The version of the Bluetooth module is 2.5.

Q2: What is the date of the latest update?

A2: The latest update was on 10 Aug 2022.

Q3: How can I program the Bluetooth module?

A3: The Bluetooth module supports two programming options: smartBASIC and Nordic SDK. Refer to the usage instructions for more details.

Q4: What is the power consumption of the Bluetooth module?

A4: The Bluetooth module has ultra-low power consumption, with a peak Rx current of 4.6 mA (DCDC on). Refer to the Power Consumption section for more details.

Version 2.5

Version 1.0
1.1
1.2 2.0 2.1 2.2
2.3 2.4 2.5

Date 04 Jun 2020
04 Aug 2020
13 Oct 2020 14 Dec 2020 22 Jan 2021 18 Feb 2021
26 July 2021 22 Dec 2021 10 Aug 2022

Notes Initial version Added dielectric constant of prepreg and solder mask in section 6.4 Figure12 BL653 development board PCB stack-up and L1 to L2 50-Ohms Grounded CPW RF trace design. Added 12. Reliability Tests
Updated all regulatory information
Transferred all regulatory information to a separate document Fixed equation in 5.5.2 NFC Antenna Coil Tuning Capacitors Added board image to polar plot in section 5.18 453-00039 On-board PCB Antenna Characteristics Updated Mechanical Details Removed PCB printed antenna from External Antenna Integration with 453-00041

Contributor(s) Raj Khatri
Raj Khatri
Raj Khatri Maggie Teng Ryan Urness Maggie Teng
Raj Khatri
Raj Khatri Dave Drogowski
Raj Khatri

Approver Jonathan Kaye
Jonathan Kaye
Jonathan Kaye Jonathan Kaye Jonathan Kaye Dave Drogowski
Dave Drogowski Andrew Chen Jonathan Kaye

https://www.lairdconnect.com/wirelessmodules/bluetooth-modules

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https://www.lairdconnect.com/wirelessmodules/bluetooth-modules

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https://www.lairdconnect.com/wirelessmodules/bluetooth-modules

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Every BL653 Series module is designed to simplify OEMs enablement of Bluetooth Low Energy (BLE) v5.1 and Thread (802.15.4) to small, portable, power- conscious devices. The BL653 provides engineers with considerable design flexibility in both hardware and software programming capabilities. Based on the world-leading Nordic Semiconductor nRF52833 chipset, the BL653 modules provide ultra-low power consumption with outstanding wireless range via +8 dBm of transmit power and the Long Range (CODED PHY) Bluetooth 5 feature. The BL653 is programmable via Laird Connectivity’s smartBASIC language, AT command set, Zephyr RTOS or Nordic’s software development kit (SDK).
smartBASIC is an event-driven programming language that is highly optimized for memory-constrained systems such as embedded modules. It was designed to make BLE development quicker and simpler, vastly cutting down time to market.
The Nordic SDK, on the other hand, offers developers source code (in C) and precompiled libraries containing BLE and ANT+ device profiles, wireless communication, as well as application examples.
Note: BL653 hardware provides all functionality of the nRF52833 chipset used in the module design. This is a hardware datasheet only it does not cover the software aspects of the BL653.
For customers using smartBASIC, refer to the smartBASIC extensions guide (available from the BL653 product page of the Laird Connectivity website. For customers using the Nordic SDK, refer to www.nordicsemi.com.

Bluetooth v5.1 Single mode NFC
802.15.4 (Thread) radio support External or internal antennas
Multiple programming options
smartBASIC AT command set Nordic SDK in C Zephyr RTOS Compact footprint
Programmable Tx power +8 dBm to -20 dBm, -40 dBm
Rx sensitivity -96 dBm (1 Mbps), – 103 dBm (125 kbps)
Ultra-low power consumption
Tx 4.9 mA peak (at 0 dBm, DCDC on) (See Note 1 in the Power Consumption section)
Rx: 4.6 mA peak (DCDC on) (See Note 1 in the Power Consumption section)

Standby Doze 2.6 uA typical Deep Sleep 0.6 uA (See Note 4 in the Power
Consumption section) UART, GPIO, ADC, PWM, FREQ output, timers,
I2C, SPI, I2S, PDM, and USB interfaces Fast time-to-market FCC, EU, ISED, RCM, Japan, and KC certified Full Bluetooth Declaration ID Other regulatory certifications on request No external components required Extended Industrial temperature range
(-40° C to +105° C)

https://www.lairdconnect.com/wirelessmodules/bluetooth-modules

Copyright 2022 Laird Connectivity

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Medical devices IoT Sensors Appcessories

Fitness sensors Location awareness Home automation

Categories/Feature Wireless Specification
Bluetooth®
Frequency Raw Data Rates Maximum Transmit Power Setting Minimum Transmit Power Setting Receive Sensitivity ( 37-byte packet) Link Budget (conducted)

Implementation

BT 5.1 Single mode Angle-of-arrival (AoA) and angle-of-departure (AoD) BT 5.1 4x Range (CODED PHY support) BT 5.0 2x Speed (2M PHY support) BT 5.0 LE Advertising Extensions BT 5.0 Concurrent master, slave
BLE Mesh capabilities
Diffie-Hellman based pairing (LE Secure Connections) BT 4.2 Data Packet Length Extension BT 4.2 Link Layer Privacy (LE Privacy 1.2) BT 4.2 LE Dual Mode Topology BT 4.1 LE Ping BT 4.1

2.402 – 2.480 GHz

1 Mbps BLE (over-the-air) 2 Mbps BLE (over-the-air) 125 kbps BLE (over-the- air) 500 kbps BLE (over-the-air)

+8 dBm Conducted 453-00039 (Integrated antenna)

+8 dBm Conducted 453-00041 (Trace pinconnecting to External antenna)

-40 dBm, -20 dBm (in 4 dB steps)

-16 dBm, -12 dBm, – 8 dBm, – 4 dBm, 0 dBm, 2 dBm, 4 dBm, 5 dBm, 6 dBm, 7 dBm,

BLE 1 Mbps (BER=1E-3) -96 dBm typical

BLE 2 Mbps

-92 dBm typical

BLE 125 kbps

-103 dBm typical

BLE 500 kbps

-99 dBm typical

104 dB

@ BLE 1 Mbps

111 dB

@ BLE 125 kbps

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Categories/Feature NFC
NFC-A Listen mode compliant
System Wake-On-Field function Host Interfaces and Peripherals
Total UART
USB
GPIO
ADC
PWM Output FREQ Output I2C SPI Temperature Sensor

Implementation
Based on NFC forum specification 13.56 MHz Date rate 106 kbps NFC Type 2 and Type 4 emulation Modes of Operation: Disable Sense Activated Use Cases: Touch- to-Pair with NFC NFC enabled Out-of-Band Pairing

Proximity Detection

42 x multifunction I/O lines
2 UARTs Tx, Rx, CTS, RTS DCD, RI, DTR, DSR (See Note 1 in the Module Specification Notes) Default 115200, n, 8, 1 From 1,200 bps to 1 Mbps
USB 2.0 FS (Full Speed, 12 Mbps). CDC driver/Virtual UART (baud rate TBD) Other USB drivers available via Nordic SDK
Up to 42, with configurable: I/O direction O/P drive strength (standard 0.5 mA or high 3mA/5 mA) Pull-up /pull-down Input buffer disconnect
Eight 8/10/12-bit channels 0.6 V internal reference Configurable 4, 2, 1, 1/2, 1/3, 1/4, 1/5 1/6 (default) pre-scaling Configurable acquisition time 3uS, 5uS, 10uS (default), 15uS, 20uS, 40uS. One-shot mode
PWM outputs on 16 GPIO output pins PWM output duty cycle: 0%-100% PWM output frequency: Up to 500 kHz
FREQ outputs on 16 GPIO output pins FREQ output frequency: 0 MHz-4 MHz (50% duty cycle)
Two I2C interface (up to 400 kbps) See Note 2 in the Module Specification Notes
Four SPI Master Slave interface (up to 4 Mbps) One temperature sensor Temperature range equal to the operating temperature range Resolution 0.25 degrees

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Categories/Feature RSSI Detector

Implementation
One RF received signal strength indicator ±2 dB accuracy (valid over -90 to -20 dBm) One dB resolution

I2S

One inter-IC sound interface

PDM

One pulse density modulation interface

Optional (External to the BL653 module)

External 32.768 kHz crystal

For customer use, connect +/-20 ppm accuracy crystal for more accurate protocol timing.

Profiles Supported Services

Central mode Peripheral mode Mesh (with custom models) Custom and adopted profiles

Programmability smartBASIC

FW upgrade via JTAG or UART Application download via UART or Via Over-the-Air (if SIO_02 pin is pulled high
externally)

Nordic SDK

Via JTAG

Operating Modes

smartBASIC

Self-contained Run mode Selected by nAutoRun pin status: LOW (0V). Then runs $autorun$ (smartBASIC application script) if it exists. Interactive/Development mode HIGH (VDD). Then runs via at+run (and file name of smartBASIC application script).

AT Command set

Comprehensive Hayes-style AT command set

Nordic SDK

As per Nordic SDK

Zephyr RTOS

As per www.zephyrproject.org

Supply Voltage Supply (VDD or VDD_HV) options

Normal voltage mode VDD 1.7- 3.6 V Internal DCDC converter or LDO (See Note 3 in the Module Specification Notes)
OR High voltage mode VDD_HV 2.5V-5.5V Internal LDO
(See Note 3 and Note 4 in the Module Specification Notes)

Power Consumption

Active Modes Peak Current (for maximum Tx power +8 dBm) Radio only

14.2 mA peak Tx (with DCDC)

Active Modes Peak Current (for Tx power -40 dBm) Radio only

2.3 mA peak Tx (with DCDC)

Active Modes Average Current

Depends on many factors, see Power Consumption

Ultra-low Power Modes

Standby Doze Deep Sleep

2.6 uA typical 0.6 uA

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Categories/Feature Antenna Options
Internal
External
Physical Dimensions
Weight Environmental
Operating Storage Miscellaneous Lead Free Warranty Development Tools Development Kit Approvals Bluetooth® FCC/ISED/EU/MIC/RCM/KC

Implementation
Printed PCB monopole antenna on-board 453-00039 variant Dipole antenna (with IPEX connector) Dipole PCB antenna (with IPEX connector) Connection via RF connector (IPEX MH4) 453-00041 variant (RF trace pin) See the Antenna Information sections for FCC, ISED, MIC, RCM, KC, and EU.
15.0 mm x 10 mm x 2.2 mm Pad Pitch 0.8 mm Pad Type Two rows of pads <1 gram
-40 °C to +105 °C -40 °C to +85 °C
Lead-free and RoHS-compliant One-year warranty
Development kit per module SKU (453-00039-K1 and 453-00041-K1) and free software tools
Full Bluetooth SIG Declaration ID All BL653 Series

https://www.lairdconnect.com/wirelessmodules/bluetooth-modules

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Module Specification Notes:

Note 1 DSR, DTR, RI, and DCD can be implemented in the smartBASIC application or through the Nordic SDK.

Note 2

With I2C interface selected, pull-up resistors on I2C SDA and I2C SCL must be connected externally as per I2C standard.

Note 3 Use of the internal DCDC (REG1) convertor or LDO (REG1) is decided by the underlying BLE stack.

Note 4

In High Voltage mode (VDD_HV), no external current draw (from VDD pin) is allowed (limitation of nRF52833 chipset).

Figure 1: BL653 block diagram

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Figure 2: Functional HW and SW block diagram for BL653 series BLE module

Figure 3: BL653 module pin-out (top view). Outer row pads (long red line) and inner row pads (short red line) shown

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Table 1: Pin definitions

Pin #

Pin Name

Default Function

0

GND

–

1

SWDIO

2

SIO_36

3

SWDCLK SWDCLK

4

SIO_34

5

SIO_35/ nAutoRUN

nAutoRUN

6

NC

–

7

SIO_32

8

SIO_25

9

NC

10

SIO_24

11

NC

12

SIO_21

13

SIO_20

14

NC

15

D+

16

SIO_17

17

D-

18

SIO_15

SIO_25
–
SIO_24
SIO_21 SIO_20
D+ SIO_17 D-
SIO_15

19

nRESET

20

SIO_13

21

SIO_16

22

SIO_14

23

GND

–

24

VBUS

–

25 VDD_HV

–

26

GND

–

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Alternate Function
–
–
–

In/ Out

PullUp/ Down

nRF52833 QFN Pin

–

In Pull-up AC24

In Pull-up

U24

In

Pulldown

AA24

– Pull-up

W24

nRF52833 QFN Name
SWDIO P1.04
SWDCLK
P1.02

SIO_35

In

Pulldown

Y23

P1.01

–

In Pull-up AD22

–

In Pull-up AD18

–

In Pull-up AD20

–

In Pull-up

AC17

–

In Pull-up

AD16

–

In

AD6

–

In Pull-up

AD12

–

In

AD4

–

In Pull-up

AD10

SIO_18

In Pull-up

AC13

–

In Pull-up

AD8

–

In Pull-up

AC11

–

In Pull-up

AC9

–

AD2

–

Y2

–

P1.00/ TRACEDATA0 P0.22
P0.24
P0.21 P0.20
D+ P0.17 DP0.15 P0.18/ nRESET P0.13
P0.16
P0.14 –
VBUS VDDH
–

Comment
–
–
Laird Connectivity
Devkit: FTDI USB_DTR via
jumper on J12 pin 1-2 –
–
Laird Connectivity Devkit: BUTTON4
Laird Connectivity Devkit: BUTTON3
Laird Connectivity Devkit: LED3 System Reset (Active Low) Laird Connectivity Devkit: LED1 Laird Connectivity Devkit: LED4 Laird Connectivity Devkit: LED2 4.35V 5.5V 2.5V to 5.5V –
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Pin #

Pin Name

27

SIO_11

Default Function
SIO_11

Alternate Function
–

In/ Out

PullUp/ Down

nRF52833 QFN Pin

nRF52833 QFN Name

Comment

In Pull-up

T2

P0.11/ TRACEDATA2

Laird Connectivity Devkit: BUTTON1

P0.12/

28

SIO_12

–

In Pull-up

U1

–

TRACEDATA1

UARTCLOSE()

selects DIO

29

SIO_08/ UART_RX

SIO_08

UART_RX

In Pull-up

N1

P0.08

functionality UARTOPEN() selects

UART COMMS

behavior

Laird Connectivity Devkit:

SPI EEPROM.

SPI_Eeprom_CLK,

Output:

30

SIO_41/ SPI_CLK

SIO_41

SPI_CLK

In Pull-up

R1

P1.09/ TRACEDATA3

SPIOPEN() in smartBASIC selects

SPI function, MOSI

and CLK are outputs

when in SPI master

mode.

31

VDD

–

AD14

32

SIO_40/ SPI_MOSI

SIO_40

SPI_MOSI

In Pull-up

P2

33

GND

–

SIO_04/

34

AIN2/

SPI_MISO

SIO_04

AIN2/ SPI_MISO

In Pull-up

J1

35

SIO_06/ UART_TX

SIO_06

UART_TX

Set Out High in
FW

L1

VDD P1.08
P0.04/AIN2
P0.06

1.7V to 3.6V
Laird Connectivity Devkit:
SPI EEPROM. SPI_Eeprom_MOSI,
Output SPIOPEN() in smartBASIC selects SPI function, MOSI and CLK are outputs in SPI master.
–
Laird Connectivity Devkit: SPI EEPROM.
SPI_Eeprom_MISO, Input
SPIOPEN() in smartBASIC selects SPI function; MOSI and CLK are outputs when in SPI master
mode
UARTCLOSE() selects DIO functionality
UARTOPEN() selects UART COMMS behaviour

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Pin #

Pin Name

36

SIO_26/ I2C_SDA

Default Function
SIO_26

Alternate Function
I2C_SDA

In/ Out

PullUp/ Down

nRF52833 QFN Pin

In Pull-up

G1

nRF52833 QFN Name
P0.26

37

SIO_07/ UART_CTS

SIO_07

UART_CTS IN

Pulldown

M2

P0.07/ TRACECLK

38

SIO_27/ I2C_SCL

SIO_27

I2C_SCL

In Pull-up

H2

P0.27

SIO_05/ 39 UART_RTS/
AIN3

SIO_05

UART_RTS/ AIN3

Out

Set Low in
FW

K2

40

GND

–

41

SIO_01/ XL2

SIO_01

XL2

In Pull-up

F2

P0.05/AIN3 –
P0.01/XL2

42

SIO_00/ XL1

SIO_00

43

GND

44

SIO_31/ AIN7

45

SIO_30/ AIN6

46

SIO_28/ AIN4

47

GND

48

SIO_29/ AIN5

49

SIO_03/ AIN1

SIO_31 SIO_30 SIO_28
SIO_29
SIO_03

XL1
AIN7 AIN6 AIN4
AIN5 AIN1

In Pull-up

D2

–

In Pull-up

A8

In Pull-up

B9

In Pull-up

B11

–

In Pull-up

A10

In Pull-up

B13

P0.00/XL1
P0.31/AIN7 P0.30/AIN6 P0.28/AIN4
P0.29/AIN5 P0.03/AIN1

Comment
Laird Connectivity Devkit:
I2C RTC chip I2C data line UARTCLOSE() selects DIO functionality UARTOPEN() selects UART COMMS behaviour Laird Connectivity
Devkit: I2C RTC chip I2C clock line UARTCLOSE() selects DIO functionality UARTOPEN() selects UART COMMS behavior
Laird Connectivity
Devkit: Optional 32.768kHz crystal
pad XL2 and associated load
capacitor Laird Connectivity
Devkit: Optional 32.768kHz crystal
pad XL1 and associated load
capacitor –
–
–
–
–
–
Laird Connectivity Devkit: Temp Sens
Analog

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Pin #

Pin Name

50

SIO_02/ AIN0

51

SIO_46

52

GND

53

SIO_47

54

SIO_44

55

GND

56

SIO_45

57

NFC2/ SIO_10

58

GND

59

NFC1/ SIO_09

60

NC

61

NC

62

SIO_42

63

SIO_38

64

SIO_39

65

GND

66

GND

67

GND

68

GND

69

GND

70

GND

71

GND

72

RF pad

Default Function
SIO_02
SIO_46 –
SIO_47
SIO_44
SIO_45 NFC2
NFC1
SIO_42 N/C SIO_39 –
–

Alternate Function
AIN0
–
–
SIO_10 SIO_09 –
–

In/ Out

PullUp/ Down

nRF52833 QFN Pin

IN

Pulldown

A12

In Pull-up

B15

–

In Pull-up

A14

nRF52833 QFN Name
P0.02/AIN0
P1.03 –
P0.19

In Pull-up

B17

P0.23

–

In Pull-up

A16

In

–

J24

–

In

–

L24

–

In Pull-up

A20

In Pull-up

R24

In Pull-up

P23

–

P1.05
P0.10/NFC2
–
P0.09/NFC1
P0.25 P1.06 P1.07 –
–

Comment
Pull High externally to enter VSP (Virtual Serial Port) Service.
Laird Connectivity Devkit: SPI EEPROM SPI_Eeprom_CS, Input –
–
–
–
Reserved for future use. Do not connect. Active on BL653 RF pad variant (45300041). Note11

Pin Definition Notes:
Note 1 SIO = Signal Input or Output. Secondary function is selectable in smartBASIC application or via Nordic SDK. I/O voltage level tracks VDD. AIN = Analog Input.

Note 2

At reset, all SIO lines are configured as the defaults shown above.
SIO lines can be configured through the smartBASIC application script to be either inputs or outputs with pull-ups or pull-downs. When an alternative SIO function is selected (such as I2C or SPI), the firmware does not allow the setup of internal pull-up/pull-down. Therefore, when I2C interface is selected, pull-up resistors on I2C SDA and I2C SCL must be connected externally as per I2C standard.

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Pin Definition Notes:
Note 3 JTAG (two-wire SWD interface), pin 1 (SWDIO) and pin 3 (SWDCLK).
JTAG is required because Nordic SDK applications can only be loaded using JTAG (smartBASIC firmware can be loaded using the JTAG as well as UART). We recommend that you use JTAG (2-wire interface) to handle future BL653 module smartBASIC firmware upgrades. You MUST wire out the JTAG (2-wire interface) on your host design (see Figure 7, where four lines (SWDIO, SWDCLK, GND and VDD) should be wired out. smartBASIC firmware upgrades can still be performed over the BL653 UART interface, but this is slower (60 seconds using UART vs. 10 seconds when using JTAG) than using the BL653 JTAG (2-wire interface).
Upgrading smartBASIC firmware or loading the smartBASIC applications is done using the UART interface.

Note 4 Pull the nRESET pin (pin 19) low for minimum 100 milliseconds to reset the BL653.

Note 5 The SIO_02 pin (pin 50) must be pulled high externally to enable VSP (Virtual Serial Port) which would allow OTA (over-the-air) smartBASIC application download. Refer to the latest firmware release documentation for details.

Note 6 Ensure that SIO_02 (pin 50) and AutoRUN (pin 5) are not both high (externally), in that state, the UART is bridged to Virtual Serial Port service; the BL653 module does not respond to AT commands and cannot load smartBASIC application scripts.

Note 7

Pin 5 (nAutoRUN) is an input, with active low logic. In the development kit it is connected so that the state is driven by the host’s DTR output line. The nAutoRUN pin must be externally held high or low to select between the following two BL653 operating modes:
Self-contained Run mode (nAutoRUN pin held at 0V this is the default (internal pull-down enabled)) Interactive/Development mode (nAutoRUN pin held at VDD)
The smartBASIC firmware checks for the status of nAutoRUN during power-up or reset. If it is low and if there is a smartBASIC application script named $autorun$, then the smartBASIC firmware executes the application script automatically; hence the name Self-contained Run Mode.

Note 8 The smartBASIC firmware has SIO pins as Digital (Default Function) INPUT pins, which are set PULL-UP by default. This avoids floating inputs (which can cause current consumption to drive with time in low power modes (such as Standby Doze). You can disable the PULL-UP through your smartBASIC application.

All of the SIO pins (with a default function of DIO) are inputs (apart from SIO_05 and SIO_06, which are outputs):
SIO_06 (alternative function UART_TX) is an output, set High (in the firmware). SIO_05 (alternative function UART_RTS) is an output, set Low (in the firmware). SIO_08 (alternative function UART_RX) is an input, set with internal pull-up (in the firmware). SIO_07 (alternative function UART_CTS) is an input, set with internal pull-down (in the firmware). SIO_02 is an input set with internal pull-down (in the firmware). It is used for OTA downloading of
smartBASIC applications. Refer to the latest firmware extension documentation for details. UART_RX, UART_TX, and UART_CTS are 3.3 V level logic (if VDD is 3.3 V; such as SIO pin I/O levels
track VDD). For example, when Rx and Tx are idle, they sit at 3.3 V (if VDD is 3.3 V). Conversely, handshaking pins CTS and RTS at 0V are treated as assertions.

Note 9

BL653 also allows as an option to connect an external higher accuracy (±20 ppm) 32.768 kHz crystal to the BL653 pins SIO_01/XL2 (pin 41) and SIO_00/XL1 (pin 42). This provides higher accuracy protocol timing and helps with radio power consumption in the system standby doze/deep sleep modes by reducing the time that the Rx window must be open.

Note 10

Not required for BL653 module normal operation. The on-chip 32.768kHz LFRC oscillator provides the standard
accuracy of ±500 ppm, with calibration required every 8seconds (default) to stay within ±500 ppm.
BL653 power supply options:
Option 1 Normal voltage power supply mode entered when the external supply voltage is connected to both the VDD and VDD_HV pins (so that VDD equals VDD_HV). Connect external supply within range 1.7V to 3.6V range to BL653 VDD and VDD_HV pins.

OR

Option 2 High voltage mode power supply mode (using BL653 VDD_HV pin) entered when the external supply voltage in ONLY connected to the VDDH pin and the VDD pin is not connected to any external

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Pin Definition Notes: voltage supply. Connect external supply within range 2.5V to 5.5V range to BL653 VDD_HV pin. BL653 VDD pin left unconnected. No external current draw (from VDD pin) is allowed when using High Voltage mode (VDD_HV) (limitation of nRF52833 chipset).
For either option, if you use USB interface then the BL653 VBUS pin must be connected to external supply within the range 4.35V to 5.5V. When using the BL653 VBUS pin, you MUST externally fit a 4.7uF to ground.

Note 11

RF_pad (pin72) is for the BL653 RF pad variant (453-00041) module only. If using the BL653 module RF pad variant (453-00041), customer MUST copy the 50-Ohms GCPW RF track design, MUST add series 2nH RF inductor (Murata LQG15HN2N0B02# or Murata LQG15HS2N0B02) and RF connector IPEX MHF4 Receptacle (MPN: 20449-001E) Detailed in the following section: 50-Ohms RF Trace and RF Match Series 2nH RF Inductor on Host PCB for BL653 RF Pad Variant (453-00041).

Absolute maximum ratings for supply voltage and voltages on digital and analogue pins of the module are listed in the following table; exceeding these values causes permanent damage.

Table 2: Maximum current ratings Parameter

Min

Max

Unit

Voltage at VDD pin

-0.3

+3.9 (Note 1)

V

Voltage at VDD_HV pin

-0.3

+5.8

V

VBUS

-0.3

+5.8

V

Voltage at GND pin

0

V

Voltage at SIO pin (at VDD3.6V)

-0.3

VDD +0.3

V

Voltage at SIO pin (at VDD3.6V)

-0.3

3.9

V

NFC antenna pin current (NFC1/2)

–

80

mA

Radio RF input level

–

10

dBm

Environmental

Storage temperature

-40

+85

ºC

MSL (Moisture Sensitivity Level)

–

4

–

ESD (as per EN301-489) Conductive Air Coupling

4

KV

8

KV

Flash Memory (Endurance) (Note 2)

–

10000

Write/erase cycles

Flash Memory (Retention) at 85°C

10

–

years

Flash Memory (Retention) at 105°C

3

(Limited to 1000 write /read cycles)

Flash Memory (Retention) at 105°C to 85°C, execution split

6.7

(Limited to 1000 write /read cycles, 75% execution time at 85°C

or less)

Thermal characteristics (Junction temperature)

110

years years
ºC

Maximum Ratings Notes: Note 1 The absolute maximum rating for VDD_nRF pin (max) is 3.9V for the BL653.

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Note 2 Wear levelling is used in file system.

Table 3: Power supply operating parameters Parameter VDD (independent of DCDC enable)1,4 supply range VDDPOR supply voltage needed during power on reset VDD_HV supply range4 VBUS USB supply range VDD Maximum ripple or noise2 VDD supply rise time (0V to 1.7V)3 VDD_HV supply rise time (0V to 3.7V) 3 Operating temperature range Extended operating temperature range5

Min 1.7 1.75 2.5 4.35
–
-40 +85

Typ

Max

Unit

3.3

3.6

V

3.7

5.5

V

5

5.5

V

–

10

mV

–

60

mS

100

mS

–

+85

ºC

+105

ºC

Recommended Operating Parameters Notes:

Note 1 4.7 uF internal to module on VDD. The VDD internal DCDC (REG1) convertor or LDO (REG1) is decided by the underlying BLE stack depending on the load current. Through a smartBASIC command can also tell softdevice to use DCDC always or LDO always.

Note 2 This is the maximum VDD or VDD_HV ripple or noise (at any frequency) that does not disturb the radio.

Note 3 The on-board power-on reset circuitry may not function properly for rise times longer than the specified maximum.

Note 4

BL653 power supply options:
Option 1 Normal voltage power supply mode entered when the external supply voltage is connected to both the VDD and VDD_HV pins (so that VDD equals VDD_HV). Connect external supply within range 1.7V to 3.6V range to BL653 VDD and VDD_HV pins.

OR

Option 2 High voltage mode power supply mode (using BL653 VDD_HV pin) entered when the external supply voltage in ONLY connected to the VDD_HV pin and the VDD pin is not connected to any external voltage supply. Connect external supply within range 2.5V to 5.5V range to BL653 VDD_HV pin. BL653 VDD pin left unconnected. No external current draw (from VDD pin) is allowed when using High Voltage mode (VDD_HV), limitation of the nRF52833 chip.

For either option, if you use USB interface then the BL653 VBUS pin must be connected to external supply within the range 4.35V to 5.5V. When using the BL653 VBUS pin, you MUST externally fit a 4.7uF to ground.

Note 5 To avoid surpassing the maximum die temperature (110 ºC), it is important to minimize current consumption when operating in the extended operating temperature conditions (+85 ºC to +105ºC). It is therefore recommended to use the module device on Normal Voltage mode with DCDC (REG1) enabled.

Table 4: Signal levels for interface, SIO Parameter VIH Input high voltage VIL Input low voltage VOH Output high voltage (std. drive, 0.5mA) (Note 1) (high- drive, 3mA) (Note 1) (high-drive, 5mA) (Note 2)
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Min

Typ

0.7 VDD

VSS

VDD -0.4 VDD -0.4 VDD -0.4
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All Rights Reserved

Max

Unit

VDD

V

0.3 x VDD

V

VDD

V

VDD

V

VDD

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Parameter VOL Output low voltage (std. drive, 0.5mA) (Note 1) (high-drive, 3mA) (Note 1) (high-drive, 5mA) (Note 2)
VOL Current at VSS+0.4V, Output set low (std. drive, 0.5mA) (Note 1) (high- drive, 3mA) (Note 1) (high-drive, 5mA) (Note 2)
VOL Current at VDD -0.4, Output set low (std. drive, 0.5mA) (Note 1) (high- drive, 3mA) (Note 1) (high-drive, 5mA) (Note 2)
Pull up resistance Pull down resistance Pad capacitance Pad capacitance at NFC pads

Min
VSS VSS VSS
1 3 6
1 3 6 11 11

Typ

Max

Unit

VSS+0.4

V

VSS+0.4

V

VSS+0.4

2

4

mA

–

mA

10

15

mA

2

4

mA

–

mA

9

14

mA

13

16

k

13

16

k

3

pF

4

pF

Signal Levels Notes:

Note 1 For VDD1.7V. The firmware supports high drive (3 mA, as well as standard drive).

Note 2

For VDD2.7V. The firmware supports high drive (5 mA (since VDD2.7V), as well as standard drive).
The GPIO (SIO) high reference voltage always equals the level on the VDD pin.
Normal voltage mode The GPIO high level equals the voltage supplied to the VDD pin High voltage mode The GPIO high level equals the level specified (is configurable to 1.8V, 2.1V, 2.4V,
2.7V, 3.0V, and 3.3V. The default voltage is 1.8V). In High voltage mode, the VDD pin becomes an output voltage pin. The VDD output voltage and hence the GPIO is configurable from 1.8V to 3.3V with possible settings of 1.8V, 2.1V, 2.4V, 2.7V, 3.0V, and 3.3V.

Table 5: SIO pin alternative function AIN (ADC) specification Parameter Maximum sample rate ADC Internal reference voltage

Min -1.5%

ADC pin input internal selectable scaling

ADC input pin (AIN) voltage maximum without damaging ADC w.r.t (see Note 1)

VCC

Prescaling

0V-VDD

4, 2, 1, ½, 1/3, ¼, 1/5, 1/6

Configurable Resolution

Configurable (see Note 2)
Acquisition Time, source resistance 10k Acquisition Time, source resistance 40k Acquisition Time, source resistance 100k

8-bit mode

Typ
0.6 V 4, 2, 1, 1/2, 1/3, 1/4, 1/5
1/6
VDD+0.3 10-bit mode
3 5 10

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Max 200 +1.5%

Unit kHz %
scaling

V

12-bit mode

bits

uS uS uS
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Parameter

Min

Typ

Maximum sample rate

Acquisition Time, source resistance 200k

15

Acquisition Time, source resistance 400k

20

Acquisition Time, source resistance 800k

40

Conversion Time (see Note 3)

<2

ADC input impedance (during operation) (see Note 3)

Input Resistance

1

Sample and hold capacitance at maximum gain

2.5

Max

Unit

200

kHz

uS

MOhm pF

Recommended Operating Parameters Notes:
Note 1 Stay within internal 0.6 V reference voltage with given pre-scaling on AIN pin and do not violate ADC maximum input voltage (for damage) for a given VCC, e.g. If VDD is 3.6V, you can only expose AIN pin to VDD+0.3 V. Default pre-scaling is 1/6 which configurable via smartBASIC.

Note 2

Firmware allows configurable resolution (8-bit, 10-bit or 12-bit mode) and acquisition time. BL653 ADC is a Successive Approximation type ADC (SSADC), as a result no external capacitor is needed for ADC operation. Configure the acquisition time according to the source resistance that customer has.

The sampling frequency is limited by the sum of sampling time and acquisition time. The maximum sampling time is 2us. For acquisition time of 3us the total conversion time is therefore 5us, which makes maximum sampling frequency of 1/5us = 200kHz. Similarly, if acquisition time of 40us chosen, then the conversion time is 42us and the maximum sampling frequency is 1/42us = 23.8kHz.

Note 3 ADC input impedance is estimated mean impedance of the ADC (AIN) pins.

The BL653 module comes loaded with smartBASIC firmware but does not come loaded with any smartBASIC application script (as that is dependent on customer-end application or use). Laird Connectivity provides many sample smartBASIC application scripts via a sample application folder on GitHub https://github.com/LairdCP/BL653-Applications
Therefore, it boots into AT command mode by default.

Refer to the smartBASIC extension manual for details of functionality connected to this:
nAutoRUN pin (SIO_35), see Table 6 for default VSP pin (SIO_02), see Table 7 for default SIO_38 Reserved for future use. Do not connect. See Table 8

Table 6: nAutoRUN pin Signal Name nAutoRUN /(SIO_35)

Pin # 5

I/O Comments
I Input with active low logic. Internal pull down (default).
Operating mode selected by nAutoRun pin status: Self-contained Run mode (nAutoRUN pin held at 0V) If Low (0V), runs $autorun$ if it exists Interactive/Development mode (nAutoRUN pin held at VCC) If High (VCC), runs via AT+rRUN (and file name of application)

In the development board nAutoRUN pin is connected so that the state is driven by the host’s DTR output line.

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Table 7: VSP mode Signal Name

Pin #

SIO_02

50

Table 8: SIO_38 Signal Name
SIO_38

Pin # 63

I/O

Comments

Internal pull down (default).

I

VSP mode selected by externally pulling-up SIO_02 pin:

High (VCC), then OTA smartBASIC application download is possible.

I/O

Comments

Internal pull up (default). I
Reserved for future use. Do not connect if using smartBASIC FW.

Data at VDD of 3.3 V with internal (to chipset) LDO(REG1) ON or with internal (to chipset) DCDC(REG1) ON (see Power Consumption Note 1) and 25ºC.

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Table 9: Power consumption Parameter
Active mode `peak’ current (Note 1) (Advertising or Connection)
Tx only run peak current @ Txpwr = +8 dBm Tx only run peak current @ Txpwr = +4 dBm Tx only run peak current @ Txpwr = 0 dBm Tx only run peak current @ Txpwr = -4 dBm Tx only run peak current @ Txpwr = -8 dBm Tx only run peak current @ Txpwr = -12 dBm Tx only run peak current @ Txpwr = -16 dBm Tx only run peak current @ Txpwr = -20 dBm Tx only run peak current @ Txpwr = -40 dBm

Min

Typ

Max

Unit

With DCDC [with LDO]

14.2 [30.4]

mA

9.6 [20.7]

mA

4.9 [10.3]

mA

3.8 [8.0]

mA

3.4 [7.1]

mA

3.1 [6.4]

mA

2.9 [5.9]

mA

2.7 [5.5]

mA

2.3 [4.5]

mA

Active Mode Rx only peak’ current, BLE 1Mbps (Note 1) Rx onlypeak’ current, BLE 2Mbps (Note 2)

4.6 [9.6]

mA

5.2 [10.7]

mA

Ultra-Low Power Mode 1 (Note 2) Standby Doze, 256k RAM retention

2.6

uA

Ultra-Low Power Mode 2 (Note 3) Deep Sleep (no RAM retention)
Active Mode Average current (Note 4) Advertising Average Current draw Max, with advertising interval (min) 20 mS Min, with advertising interval (max) 10240 mS Connection Average Current draw Max, with connection interval (min) 7.5 mS Min, with connection interval (max) 4000 mS
Power Consumption Notes:

0.6

uA

Note 4

uA

Note 4

uA

Note 4

uA

Note4

uA

Note 1 This is for Peak Radio Current only, but there is additional current due to the MCU. The internal DCDC convertor (REG1) or LDO (REG1) is decided by the underlying BLE stack.

Note 2

BL653 modules Standby Doze is 2.6 uA typical. When using smartBASIC firmware, Standby Doze is entered automatically (when a waitevent statement is encountered within a smartBASIC application script). In Standby Doze, all peripherals that are enabled stay on and may re-awaken the chip. Depending on active peripherals, current consumption ranges from 2.6 A to 370 uA (when UART is ON). See individual peripherals current consumption data in the Peripheral Block Current Consumption section. smartBASIC firmware has functionality to detect GPIO change with no current consumption cost, it is possible to close the UART and get to the 2.6 uA current consumption regime and still be able to detect for incoming data and be woken up so that the UART can be re-opened at expense of losing that first character.
The BL653 Standby Doze current (at 25°C) consists of the below nRF52833 blocks: nRF52 System ON IDLE current (no RAM retention) (1.1 uA) This is the base current of the CPU LFRC (0.7 uA) and RTC (0.1uA or near 0uA) running as well as 128k RAM retention (0.8 uA) This adds to
the total of 2.7 uA typical. The RAM retention is 20nA per 4k block, but this can vary to 30nA per 4k block which would make the total 2.55uA to 2.86uA.

Note 3 In Deep Sleep, everything is disabled and the only wake-up sources (including NFC to wakeup) are reset and changes on SIO or NFC pins on which sense is enabled. The current consumption seen is ~0.6 uA typical in BL653 modules.

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Power Consumption Notes: Coming out from Deep Sleep to Standby Doze through the reset vector.

Note 4

Average current consumption depends on several factors (including Tx power, VCC, accuracy of 32MHz and 32.768 kHz). With these factors fixed, the largest variable is the advertising or connection interval set.
Advertising Interval range: 20 milliseconds to 10240 mS (10485759.375 mS in BT5.1) in multiples of 0.625 milliseconds.
For an advertising event: The minimum average current consumption is when the advertising interval is large 10240 mS
(10485759.375 mS (in BT5.0) although this may cause long discover times (for the advertising event) by scanners The maximum average current consumption is when the advertising interval is small 20 mS Other factors that are also related to average current consumption include the advertising payload bytes in each advertising packet and whether it’s continuously advertising or periodically advertising. Connection Interval range (for a peripheral): 7.5 milliseconds to 4000 milliseconds in multiples of 1.25 milliseconds.
For a connection event (for a peripheral device): The minimum average current consumption is when the connection interval is large 4000 milliseconds The maximum average current consumption is with the shortest connection interval of 7.5 ms; no slave
latency.
Other factors that are also related to average current consumption include: Number packets per connection interval with each packet payload size An inaccurate 32.768 kHz master clock accuracy would increase the average current consumption.
Connection Interval range (for a central device): 2.5 milliseconds to 40959375 milliseconds in multiples of 1.25 milliseconds.

The values below are calculated for a typical operating voltage of 3V.

Table 10: UART power consumption Typ

Parameter

Min

WITH

DCDC(REG1) LDO(REG1)

UART Run current @ 115200 bps

–

450

721

UART Run current @ 1200 bps

–

450

721

Idle current for UART (no activity)

–

2.9

UART Baud rate

1.2

–

Max
1000

Table 11: SPI power consumption
Parameter
SPI Master Run current @ 2 Mbps SPI Master Run current @ 8 Mbps Idle current for SPI (no activity) SPI bit rate

Typ

Min

WITH

Max

DCDC(REG1)

LDO(REG1)

–

536

803

–

536

803

–

<1

–

8

Unit
uA uA uA kbps
Unit
uA uA uA Mbps

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Table 12: I2C power consumption
Parameter
I2C Run current @ 100 kbps I2C Run current @ 400 kbps Idle current for I2C (no activity) I2C Bit rate

Typ

Min

WITH

Max

DCDC(REG1) LDO(REG1)

–

734

994

–

734

994

–

2.5

–

100

–

400

Unit
uA uA uA kbps

Table 13: ADC power consumption Parameter
ADC current during conversion Idle current

Typ

Min

WITH

Max

DCDC(REG1) LDO(REG1)

–

1900

1350

–

0

–

Unit
uA uA

The above current consumption is for the given peripheral including the internal blocks that are needed for that peripheral for both the case when DCDC(REG1) is on and LDO (REG1) is on. The peripheral Idle current is when the peripheral is enabled but not running (not sending data or being used) and must be added to the StandByDoze current (Nordic System ON Idle current). In all cases radio is not turned on.

For asynchronous interface, like the UART (asynchronous as the other end can communicate at any time), the UART on the BL653 must be kept open (by a command in smartBASIC application script), resulting in the base current consumption penalty.
For a synchronous interface like the I2C or SPI (since BL653 side is the master), the interface can be closed and opened (by a command in smartBASIC application script) only when needed, resulting in current saving (no base current consumption penalty). There’s a similar argument for ADC (open ADC when needed).

To provide the widest scope for integration, a variety of physical host interfaces/sensors are provided. The major BL653 series module functional blocks described below.

Power management features:
System Standby Doze and Deep Sleep modes Open/Close peripherals (UART, SPI, I2C, SIO’s, ADC, NFC). Peripherals consume current when open; each peripheral
can be individually closed to save power consumption Use of the internal DCDC (REG1) convertor or LDO (REG1) is decided by the underlying BLE stack smartBASIC command allows the supply voltage to be read (through the internal ADC) Pin wake-up system from deep sleep (including from NFC pins)
Power supply features:
Supervisor hardware to manage power during reset, brownout, or power fail. 1.7V to 3.6V supply range for normal power supply (VDD pin) using internal DCDC convertor (REG1) or LDO(REG1)
decided by the underlying BLE stack. 2.5V to 5.5 supply range for High voltage power supply (VDD_HV pin) using internal LDO(REG0). 4.35V to 5.5V supply range for powering USB (VBUS pin) portion of BL653 only. The remainder of the BL653 module
circuitry must still be powered through the VDD (or VDD_HV) pin.

The BL653 module power supply internally contains the following two main supply regulator stages (Figure 4):

REG0 Connected to the VDD_HV pin
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REG1 Connected to the VDD pin The USB power supply is separate (connected to the VBUS pin).

Figure 4: BL653 power supply block diagram (adapted from the following resource: http://infocenter.nordicsemi.com/pdf/nRF52833_PS_v1.0.pdf
The BL653 power supply system enters one of two supply voltage modes, normal or high voltage mode, depending on how the external supply voltage is connected to these pins.
BL653 power supply options:
Option 1 Normal voltage power supply mode entered when the external supply voltage is connected to both the VDD and VDD_HV pins (so that VDD equals VDD_HV). Connect external supply within range 1.7V to 3.6V range to BL653 VDD and VDD_HV pins.
OR
Option 2 High voltage mode power supply mode (using BL653 VDD_HV pin) entered when the external supply voltage in ONLY connected to the VDD_HV pin and the VDD pin is not connected to any external voltage supply. Connect external supply within range 2.5V to 5.5V range to BL653 VDD_HV pin. BL653 VDD pin left unconnected. No external current draw (from VDD pin) is allowed when using High Voltage mode (VDD_HV), limitation of the nRF52833 chip.

Note:

To avoid surpassing the maximum die temperature (110 ºC), it is important to minimize current consumption when operating in the extended operating temperature conditions (+85 ºC to +105ºC). It is therefore recommended to use the module device on Normal Voltage mode with DCDC (REG1) enabled.

For either option, if you use USB interface then the BL653 VBUS pin must be connected to external supply within the range 4.35V to 5.5V. When using the BL653 VBUS pin, you MUST externally fit a 4.7uF to ground.
Table 14 summarizes these power supply options.

Table 14: BL653 powering options

Power Supply Pins and
Operating Voltage Range

OPTION 1 Normal voltage mode operation
connect?

OPTION 2 High voltage mode operation connect?

VDD (pin31) 1.7V to 3.6V

Yes (Note 1)

No (Note 2)

OPTION 1 with USB peripheral,
and normal voltage mode operation connect?
Yes

OPTION 2 with USB peripheral, and high
voltage operation connect?
No (Note 2)

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VDD_HV (pin25) No
2.5V to 5.5V VBUS (pin24)
No 4.35V to 5.5V

Yes (Note 3)

No
Yes (Note 4)

Yes (Note 5)
Yes (Note 4)

Power Supply Option Notes:
Note 1 Option 1 External supply voltage is connected to BOTH the VDD and VDD_HV pins (so that VDD equals VDD_HV). Connect external supply within range 1.7V to 3.6V range to BOTH BL653 VDD and VDD_HV pins.

Note 2

Option 2 External supply within range 2.5V to 5.5V range to the BL653 VDD_HV pin ONLY. BL653 VDD pin left unconnected.
In High voltage mode, the VDD pin becomes an output voltage pin but no current can be taken from VDD pin (limitation of the nRF52833 chip). It Additionally, the VDD output voltage is configurable from 1.8V to 3.3V with possible settings of 1.8V, 2.1V, 2.4V, 2.7V, 3.0V, and 3.3V. The default voltage is 1.8V.
The supported BL653 VDD pin output voltage range depends on the supply voltage provided on the BL653 VDD_HV pin. The minimum difference between voltage supplied on the VDD_HV pin and the voltage output on the VDD pin is 0.3 V. The maximum output voltage of the VDD pin is VDDH 0.3V.

Note 3 Depends on whether USB operation is required

Note 4 When using the BL653 VBUS pin, you must externally fit a 4.7uF capacitor to ground.

Note 5

To use the BL653 USB peripheral: 1. Connect the BL653 VBUS pin to the external supply within the range 4.35V to 5.5V. When using the BL653 VBUS pin, you MUST externally fit a 4.7uF to ground. 2. Connect the external supply to either the VDD (Option 1) or VDD_HV (Option 2) pin to operate the rest of BL653 module. When using the BL653 USB peripheral, the VBUS pin can be supplied from same source as VDD_HV (within the operating voltage range of the VBUS pin and VDD_HV pin).

The integrated high accuracy 32 MHz (±10 ppm) crystal oscillator helps with radio operation and reducing power consumption in the active modes.
The integrated on-chip 32.768 kHz LFRC oscillator (±500 ppm) provides protocol timing and helps with radio power consumption in the system StandByDoze and Deep Sleep modes by reducing the time that the RX window needs to be open.
To keep the on-chip 32.768 kHz LFRC oscillator within ±500 ppm (which is needed to run the BLE stack) accuracy, RC oscillator needs to be calibrated (which takes 33 mS) regularly. The default calibration interval is eight seconds which is enough to keep within ±500 ppm. The calibration interval ranges from 0.25 seconds to 31.75 seconds (in multiples of 0.25 seconds) and configurable via firmware
When using smartBASIC, the timer subsystem enables applications to be written which allow future events to be generated based on timeouts.
Regular Timer There are eight built-in timers (regular timers) derived from a single RTC clock which are controlled solely by smart BASIC functions. The resolution of the regular timer is 976 microseconds.
Tick Timer A 31-bit free running counter that increments every (1) millisecond. The resolution of this counter is 488 microseconds.
Refer to the smartBASIC User Guide available from the Laird Connectivity BL653 product page. For timer utilization when using the Nordic SDK, refer to http://infocenter.nordicsemi.com/index.jsp.

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24022480 MHz Bluetooth Low Energy radio BT5.1 1 Mbps, 2 Mbps, and long- range (125 kbps and 500 kbps) over-theair data rate.
Tx output power of +8 dBm programmable down to 7 dBm, 6 dBm, 5 dBm, 4 dBm, 2 dBm, 0 dBm and further down to -20 dBm in steps of 4 dB and final TX power level of -40 dBm.
Receiver (with integrated channel filters) to achieve maximum sensitivity -96 dBm @ 1 Mbps BLE, -92 dBm @2 Mbps, 103 dBm @ 125 kbps long-range and -99 dBm @500kbps long-range).
RF conducted interface available in the following two ways:
453-00039: RF connected to on-board PCB trace antenna
453-00041: RF connected to RF pad on BL653 Antenna options:
Integrated PCB trace antenna on the 453-00039
External dipole antenna connected to IPEX MH4 RF connector on host PCB. If using the BL653 module RF pad variant (453-00041), customer MUST copy the 50-Ohms GCPW RF track design, MUST add series 2nH RF inductor (Murata LQG15HN2N0B02# or Murata LQG15HS2N0B02) and RF connector IPEX MHF4 Receptacle (MPN: 20449-001E) Detailed in the following section: 50-Ohms RF Trace and RF Match Series 2nH RF Inductor on Host PCB for BL653 RF Pad Variant (453-00041).
Received Signal Strength Indicator (RSSI)
RSSI accuracy (valid range -90 to -20 dBm) is ±2 dB typical
RSSI resolution 1 dB typical

NFC support:
Based on the NFC forum specification
13.56 MHz Date rate 106 kbps NFC Type2 and Type4 tag emulation Modes of operation:
Disable Sense Activated

Touch-to Pair with NFC Launch a smartphone app (on Android) NFC enabled Out- of-Band Pairing System Wake-On-Field function
Proximity Detection

Table 15: NFC interface

Signal Name

Pin No

I/O

NFC1/SIO_09

59

I/O

NFC2/SIO_10

57

I/O

Comments
The NFC pins are by default NFC pins and an alternate function on each pin is GPIO. Refer to the smartBASIC. User manual.

From Nordic’s nRF52833 Objective Product Specification v1.0: http://infocenter.nordicsemi.com/pdf/nRF52833_PS_v1.0.pdf

The NFC antenna coil must be the connected differential between the NFC1 and NFC2 pins of the BL653. Two external capacitors should be used to tune the resonance of the antenna circuit to 13.56 MHz (Figure 5).

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Figure 5: NFC antenna coil tuning capacitors
The required external tuning capacitor value is given by the following equation:
An antenna inductance of Lant = 0.72 uH provides tuning capacitors in the range of 300 pF on each pin. The total capacitance on NFC1 and NFC2 must be matched. Cint and Cp are small usually (Cint is 4pF), so can be omitted from calculation.
Battery Protection Note: If the NFC coil antenna is exposed to a strong NFC field, the supply current may flow in the opposite direction due to parasitic diodes and ESD structures.
If the used battery does not tolerate a return current, a series diode must be placed between the battery and the BL653 to protect the battery.
Note: The BL653 has two UARTs.
The Universal Asynchronous Receiver/Transmitter (UART) offers fast, full- duplex, asynchronous serial communication with builtin flow control support (UART_CTS, UART_RTS) in HW up to one Mbps baud. Parity checking and generation for the ninth data bit are supported. UART_TX, UART_RX, UART_RTS, and UART_CTS form a conventional asynchronous serial data port with handshaking. The interface is designed to operate correctly when connected to other UART devices such as the 16550A. The signaling levels are nominal 0 V and 3.3 V (tracks VDD) and are inverted with respect to the signaling on an RS232 cable. Two-way hardware flow control is implemented by UART_RTS and UART_CTS. UART_RTS is an output and UART_CTS is an input. Both are active low. These signals operate according to normal industry convention. UART_RX, UART_TX, UART_CTS, UART_RTS are all 3.3 V level logic (tracks VDD). For example, when RX and TX are idle they sit at 3.3 V. Conversely for handshaking pins CTS, RTS at 0 V is treated as an assertion. The module communicates with the customer application using the following signals: Port/TxD of the application sends data to the module’s UART_RX signal line Port/RxD of the application receives data from the module’s UART_TX signal line

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BL653

Figure 6: UART signals

Note: The BL653 serial module output is at 3.3V CMOS logic levels (tracks VDD). Level conversion must be added to interface with an RS-232 level compliant interface.

Some serial implementations link CTS and RTS to remove the need for handshaking. We do not recommend linking CTS and RTS other than for testing and prototyping. If these pins are linked and the host sends data at the point that the BL653 deasserts its RTS signal, there is significant risk that internal receive buffers will overflow, which could lead to an internal processor crash. This will drop the connection and may require a power cycle to reset the module. We recommend that the correct CTS/RTS handshaking protocol be adhered to for proper operation.

Table 16: UART interface

Signal Name

Pin No.

SIO_06 / UART_Tx

35

SIO_08 / UART_Rx

29

SIO_05 / UART_RTS

39

SIO_07 / UART_CTS

37

I/O Comments O SIO_06 (alternative function UART_Tx) is an output, set high (in firmware). I SIO_08 (alternative function UART_Rx) is an input, set with internal pull-up (in firmware). O SIO_05 (alternative function UART_RTS) is an output, set low (in firmware). I SIO_07 (alternative function UART_CTS) is an input, set with internal pull-down (in firmware).

The UART interface is also used to load customer developed smartBASIC application script.

BL653 has USB 2.0 FS (Full Speed, 12 Mbps) hardware capability. There is a CDC driver/Virtual UART as well as other USB drivers available via Nordic SDK such as: usb_audio, usb_hid, usb_generic, usb_msc (mass storage device).

Table 17: USB interface Signal Name Pin No

D-

17

D+

15

VBUS

24

I/O Comments
I/O
I/O
When using the BL653 VBUS pin (which is mandatory when USB interface is used), Customer MUST connect externally a 4.7uF capacitor to ground. Note: You MUST power the rest of BL653 module circuitry through the VDD pin
(OPTION1) or VDD_HV pin (OPTION2).

The SPI interface is an alternate function on SIO pins.
The module is a master device that uses terminals SPI_MOSI, SPI_MISO, and SPI_CLK. SPI_CS is implemented using any spare SIO digital output pins to allow for multi-dropping.
The SPI interface enables full duplex synchronous communication between devices. It supports a three-wire (SPI_MOSI, SPI_MISO, SPI_SCK,) bidirectional bus with fast data transfers to and from multiple slaves. Individual chip select signals are necessary for each of the slave devices attached to a bus, but control of these is left to the application through use of SIO signals. I/O data is double buffered.
The SPI peripheral supports SPI mode 0, 1, 2, and 3.

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Table 18: SPI interfaces Signal Name

Pin No I/O Comments

SIO_40/SPI_MOSI

32

SIO_04/AIN2/SPI_MISO

34

SIO_41/SPI_CLK

30

O This interface is an alternate function configurable by
I smartBASIC. Default in the FW pin 56 and 53 are SIO inputs. SPIOPEN() in smartBASIC selects SPI function and changes pin 56 and 53 to outputs
O (when in SPI master mode).

Any_SIO/SPI_CS

SPI_CS is implemented using any spare SIO digital output pins to allow for

54

I multi-dropping. On Laird Connectivity devboard SIO_44 (pin54) used as

SPI_CS.

The I2C interface is an alternate function on SIO pins.
The two-wire interface can interface a bi-directional wired-OR bus with two lines (SCL, SDA) and has master /slave topology. The interface is capable of clock stretching. Data rates of 100 kbps and 400 kbps are supported.
An I2C interface allows multiple masters and slaves to communicate over a shared wired-OR type bus consisting of two lines which normally sit at VDD. The SCL is the clock line which is always sourced by the master and SDA is a bi-directional data line which can be driven by any device on the bus.

IMPORTANT: It is essential to remember that pull-up resistors on both SCL and SDA lines are not provided in the module and MUST be provided external to the module.

Table 19: I2C interface Signal Name
SIO_26/I2C_SDA
SIO_27/I2C_SCL

Pin No 36 38

I/O

Comments

I/O

This interface is an alternate function on each pin, configurable by

I/O

smartBASIC. I2COPEN() in smartBASIC selects I2C function.

The 42 SIO pins are configurable by smartBASIC application script or Nordic SDK. They can be accessed individually. Each has the following user configured features:
Input/output direction Output drive strength (standard drive 0.5 mA or high drive 5mA) Internal pull-up and pull-down resistors (13 K Ohms typical) or no pull-up/down or input buffer disconnect Wake-up from high or low-level triggers on all pins including NFC pins

The ADC is an alternate function on SIO pins, configurable by smartBASIC or Nordic SDK.
The BL653 provides access to 8-channel 8/10/12-bit successive approximation ADC in one-shot mode. This enables sampling up to 8 external signals through a front-end MUX. The ADC has configurable input and reference pre-scaling and sample resolution (8, 10, and 12 bit).

Table 20: Analog interface Signal Name
SIO_05/UART_RTS/AIN3 Analog Input SIO_04/AIN2/SPI_MISO Analog Input
SIO_03/AIN1 Analog Input SIO_02/AIN0 Analog Input
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Pin No I/O Comments

39

I

This interface is an alternate function on each pin,

34

I

configurable by smartBASIC. AIN configuration

49

I

selected using GpioSetFunc() function.

50

I

Configurable 8, 10, 12-bit resolution.

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Signal Name SIO_31/AIN7 Analog Input SIO_30/AIN6 Analog Input SIO_29/AIN5 Analog Input SIO_28/AIN4 Analog Input

Pin No I/O Comments

44

I

Configurable voltage scaling 4, 2, 1/1, 1/3, 1/3, 1/4,

45

I

1/5, 1/6(default).

Configurable acquisition time 3uS, 5uS, 10uS(default),

48

I

15uS, 20uS, 40uS.

46

I

Full scale input range (VDD)

The PWM output is an alternate function on ALL (GPIO) SIO pins, configurable by smartBASIC or the Nordic SDK.
The PWM output signal has a frequency and duty cycle property. Frequency is adjustable (up to 1 MHz) and the duty cycle can be set over a range from 0% to 100%.
PWM output signal has a frequency and duty cycle property. PWM output is generated using dedicated hardware in the chipset. There is a trade-off between PWM output frequency and resolution.
For example:
PWM output frequency of 500 kHz (2 uS) results in resolution of 1:2 PWM output frequency of 100 kHz (10 uS) results in resolution of 1:10 PWM output frequency of 10 kHz (100 uS) results in resolution of 1:100 PWM output frequency of 1 kHz (1000 uS) results in resolution of 1:1000

The FREQ output is an alternate function on 16 (GPIO) SIO pins, configurable by smartBASIC or Nordic SDK. Note: The frequency driving each of the 16 SIO pins is the same but the duty cycle can be independently set for each pin. FREQ output signal frequency can be set over a range of 0Hz to 4 MHz (with 50% mark-space ratio).

Table 21: nRESET pin Signal Name Pin No I/O Comments

nRESET

19

I

BL653 HW reset (active low). Pull the nRESET pin low for minimum 100 mS for the BL653 to reset.

The BL653 Firmware hex file consists of four elements:
smartBASIC runtime engine Nordic Softdevice Master Bootloader
Laird Connectivity BL653 smartBASIC firmware (FW) image part numbers are referenced as w.x.y.z (ex. V30.x.y.z). The BL653 smartBASIC runtime engine and Softdevice combined image can be upgraded by the customer over the UART interface.
You also have the option to use the two-wire SWD (JTAG) interface, during production, to clone the file system of a Golden preconfigured BL653 to others using the Flash Cloning process. This is described in the following application note Flash Cloning for the BL653. In this case the file system is also part of the .hex file.

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Signal Name SWDIO SWDCLK

Pin No 1 3

I/O Comments

I/O Internal pull-up resistor

I

Internal pull-down resistor

The Laird Connectivity development board incorporates an on-board SWD (JTAG) J-link programmer for this purpose. There is also the following SWD (JTAG) connector which allows on-board SWD (JTAG) J-link programmer signals to be routed off the development board. The only requirement is that you should use the following SWD (JTAG) connector on the host PCB.
The SWD (JTAG) connector MPN is as follows:

Reference JP1

Part FTSH-105

Description and MPN (Manufacturers Part Number) Header, 1.27mm, SMD, 10-way, FTSH-105-01-L-DV Samtech

Note: Reference on the BL653 development board schematic (Figure 7) shows the DVK development schematic wiring only for the SWD (JTAG) connector and the BL653 module JTAG pins.

VDD_VSRC_nRF

JP1 1 3 5 7 9

2 SWDIO_EXT 4 SWDCLK_EXT 6 SWO_EXT 8
10 nRESET_EXT

GND

PIN HEADER,1.27mm 2X5P

Figure 7: BL653 development board schematic

Note: The BL653 development board allows Laird Connectivity on-board SWD (JTAG) J-link programmer signals to be routed off the development board by from connector JP1

SWD (JTAG) is required because Nordic SDK applications can only be loaded using the SWED (JTAG) (smartBASIC firmware
can be loaded using SWD (JTAG) as well as over the UART). We recommend that you use SWD (JTAG) (2-wire SWD interface)
to handle future BL653 module firmware upgrades. You must wire out the JTAG (2-wire SWD interface) on your host design (see
Figure 7, where the following four lines should be wired out SWDIO, SWDCLK, GND, and VCC). smartBASIC firmware upgrades can still be performed over the BL653 UART interface, but this is slower than using the BL653 JTAG (2-wire SWD interface) (60 seconds using UART vs. 10 seconds when using JTAG).

Wake the BL653 from the host using wake-up pins (any SIO pin). You may configure the BL653’s wakeup pins via smartBASIC to do any of the following:
Wake up when signal is low Wake up when signal is high Wake up when signal changes
Refer to the smartBASIC user guide for details. You can access this guide from the Laird Connectivity BL653 product page.
For BL653 wake-up using the Nordic SDK, refer to Nordic infocenter.nordicsemi.com.

The BL653 has three power modes: Run, Standby Doze, and Deep Sleep.

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The module is placed automatically in Standby Doze if there are no pending events (when WAITEVENT statement is encountered within a customer’s smartBASIC script). The module wakes from Standby Doze via any interrupt (such as a received character on the UART Rx line). If the module receives a UART character from either the external UART or the radio, it wakes up. Deep sleep is the lowest power mode. Once awakened, the system goes through a system reset. For different Nordic power modes using the Nordic SDK, refer to Nordic infocenter.nordicsemi.com.
The on-silicon temperature sensor has a temperature range greater than or equal to the operating temperature of the device. Resolution is 0.25°C degrees. The on-silicon temperature sensor accuracy is ±5°C. To read temperature from on-silicon temperature sensor (in tenth of centigrade, so 23.4°C is output as 234) using smartBASIC: In command mode, use ATI2024
OR From running a smartBASIC application script, use SYSINFO(2024)
Exposed via an API in smartBASIC (see smartBASIC documentation available from the BL653 product page). The rand() function from a running smartBASIC application returns a value. For Nordic related functionality, visit Nordic infocenter.nordicsemi.com
Exposed via an API in smartBASIC (see smartBASIC documentation available from the BL653 product page). Function called aesencrypt and aesdecrypt. For Nordic related functionality, visit Nordic infocenter.nordicsemi.com
The BL653 supports readback protection capability that disallows the reading of the memory on the nRF52833 using a JTAG interface. Available via smartBASIC or the Nordic SDK.
The BL653 offers a range of functions for generating public/private keypair, calculating a shared secret, as well as generating an authenticated hash. Available via smartBASIC or the Nordic SDK.
This is not required for normal BL653 module operation. The BL653 uses the on- chip 32.76 kHz RC oscillator (LFCLK) by default (which has an accuracy of ±500 ppm) which requires regulator calibration (every eight seconds) to within ±500 ppm. You can connect an optional external high accuracy (±20 ppm) 32.768 kHz crystal (and associated load capacitors) to the BL653SIO_01/XL2 (pin 41) and SIO_00/XL1 (pin 42) to provide improved protocol timing and to help with radio power consumption in the system standby doze/deep sleep modes by reducing the time that the RX window needs to be open. Table 22 compares the current consumption difference between RC and crystal oscillator.

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Table 22: Comparing current consumption difference between BL653 on-chip RC 32.76 kHz oscillator and optional external crystal (32.768kHz) based oscillator

BL653 On-chip 32.768 kHz RC Oscillator (±500 ppm) LFRC

Optional External Higher Accuracy (±20 ppm) 32.768 kHz Crystal-based Oscillator
LFXO

Current Consumption of 32.768 kHz Block

0.7 uA

0.23 uA

Standby Doze Current (SYSTEM ON IDLE +full RAM retention +RTC run current (0uA) + LFRC or LFXO)

2.5 uA

2.03 uA

Calibration

Calibration required regularly (default eight seconds interval).
Calibration takes 32 ms; with DCDC used, the total charge of a calibration event is 15.1 uC (or 18.8uC with DCDC disabled).
The average current consumed by the calibration depends on the calibration interval and can be calculated using the following formula:
CAL_charge/CAL_interval The lowest calibration interval (0.25 seconds) provides an average current of (DCDC enabled):
15.1uC/0.25s = 60.4uA
To get the 250-ppm accuracy, the BLE stack specification states that a calibration interval of 8 seconds is enough. This gives an average current of:
15.1uC/8s = 1.89 uA
Added to the LFRC run current and Standby Doze (IDLE) base current shown above results in a total average current of:
LFRC + CAL = 2.5 + 1.89 = 4.39 uA

Not applicable

Total Summary

4.39 uA
Low current consumption Accuracy 250 ppm

2.03 uA
Lowest current consumption Needs external crystal High accuracy (depends on the crystal,
usually 20 ppm)

Table 23: Optional external 32.768 kHz crystal specification

Optional external 32.768kHz crystal

Min

Crystal Frequency

–

Frequency tolerance requirement of BLE stack

–

Load Capacitance

–

Shunt Capacitance

–

Equivalent series resistance

–

Drive level

–

Input capacitance on XL1 and XL2 pads

–

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Typ 32.768 kHz
4 pF

Max –
±500 ppm 12.5 pF 2 pF
100 kOhm 1 uW –

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Optional external 32.768kHz crystal Run current for 32.768 kHz crystal based oscillator Start-up time for 32.768 kHz crystal based oscillator Peak to peak amplitude for external low swing clock input signal must not be outside supply rails

Min –
200 mV

Typ 0.23 uA 0.25 seconds
–

Max –
1000 mV

Be sure to tune the load capacitors on the board design to optimize frequency accuracy (at room temperature) so it matches that of the same crystal standalone, Drive Level (so crystal operated within safe limits) and oscillation margin (Rneg is at least 3 to 5 times ESR) over the operating temperature range.

The 453-00039 on-board PCB trace monopole antenna radiated performance depends on the host PCB layout.

The BL653 development board was used for BL653 development and the 453-00039 PCB antenna performance evaluation. To obtain similar performance, follow guidelines in section PCB Layout on Host PCB for the 453-00039 to allow the on-board PCB antenna to radiate and reduce proximity effects due to nearby host PCB GND copper or metal covers.

Unit in dBi @2440 MHz 453-00039 PCB trace antenna

XY-plane

Peak

Avg

-0.94

-4.92

YZ-plane

Peak

Avg

-3.14

-8.64

ZX-plane

Peak

Avg

-3.41

-6.7

XY Plane

YZ Plaze

ZX Plane

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Figure 8: 453-00039 on-board PCB antenna performance (Antenna Gain and S11 whilst 453-00039 module sitting on Devboard 45300039-K1)

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The BL653 is easy to integrate, requiring no external components on your board apart from those which you require for development and in your end application.
The following are suggestions for your design for the best performance and functionality.
Checklist (for Schematic):
BL653 power supply options:
Option 1 Normal voltage power supply mode entered when the external supply voltage is connected to both the VDD and VDDH pins (so that VDD equals VDD_HV). Connect external supply within range 1.7V to 3.6V range to BL653 VDD and VDD_HV pins.
OR
Option 2 High voltage mode power supply mode (using BL653 VDD_HV pin) entered when the external supply voltage in ONLY connected to the VDDH pin and the VDD pin is not connected to any external voltage supply. Connect external supply within range 2.5V to 5.5V range to BL653 VDD_HV pin. BL653 VDD pin left unconnected. In High Voltage mode (VDD_HV), No external current draw (from VDD pin) is allowed (limitation of nRF52833 chipset).
For either option, if you use USB interface then the BL653 VBUS pin must be connected to external supply within the range 4.35V to 5.5V. When using the BL653 VBUS pin, you MUST externally fit a 4.7uF to ground.
Note: To avoid surpassing the maximum die temperature (110 ºC), it is important to minimize current consumption when operating in the extended operating temperature conditions (+85 ºC to +105ºC). It is therefore recommended to use the module device on Normal Voltage mode with DCDC (REG1) enabled.
External power source should be within the operating range, rise time and noise/ripple specification of the BL653. Add decoupling capacitors for filtering the external source. Power-on reset circuitry within BL653 series module incorporates brown-out detector, thus simplifying your power supply design. Upon application of power, the internal power-on reset ensures that the module starts correctly.
VDD and coin-cell operation
With a built-in DCDC (operating range 1.7V to 3.6V), that reduces the peak current required from a coin-cell, making it easier to use with a coin-cell.
AIN (ADC) and SIO pin IO voltage levels
BL653 SIO voltage levels are at VDD. Ensure input voltage levels into SIO pins are at VDD also (if VDD source is a battery whose voltage will drop). Ensure ADC pin maximum input voltage for damage is not violated.
AIN (ADC) impedance and external voltage divider setup
If you need to measure with ADC a voltage higher than 3.6V, you can connect a high impedance voltage divider to lower the voltage to the ADC input pin.
JTAG (SWD)
This is REQUIRED as Nordic SDK applications can only be loaded using the SWD (JTAG) (smartBASIC firmware can be loaded using the JTAG as well as the UART).
We recommend that you use JTAG (2-wire interface) to handle future BL653 module firmware upgrades. You MUST wire out the JTAG (2-wire interface) on your host design (see Figure 7, where four lines should be wired out, namely SWDIO, SWDCLK, GND and VCC). Firmware upgrades can still be performed over the BL653 UART interface, but this is slower (60 seconds using UART vs. 10 seconds when using JTAG) than using the BL653 JTAG (2-wire interface). JTAG may be used if you intend to use Flash Cloning during production to load smartBASIC scripts.
UART
Required for loading your smartBASIC application script during development (or for subsequent firmware upgrades (except JTAG for FW upgrades and/or Flash Cloning of the smartBASIC application script). Add connector to allow interfacing with UART via PC (UARTRS232 or UART-USB).

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UART_RX and UART_CTS
SIO_08 (alternative function UART_RX) is an input, set with internal weak pull-up (in firmware). The pull-up prevents the module from going into deep sleep when UART_RX line is idling. SIO_07 (alternative function UART_CTS) is an input, set with internal weak pull-down (in firmware). This pull-down ensures the default state of the UART_CTS will be asserted which means can send data out of the UART_TX line. Laird Connectivity recommends that UART_CTS be connected.
nAutoRUN pin and operating mode selection
nAutoRUN pin needs to be externally held high or low to select between the two BL653 operating modes at power-up:
Self-contained Run mode (nAutoRUN pin held at 0V). Interactive / development mode (nAutoRUN pin held at VDD).
Make provision to allow operation in the required mode. Add jumper to allow nAutoRUN pin to be held high or low (BL653 has internal 13K pull-down by default) OR driven by host GPIO. I2C
It is essential to remember that pull-up resistors on both I2C_SCL and I2C_SDA lines are not provided in the BL653 module and MUST be provided external to the module as per I2C standard.
SPI
Implement SPI chip select using any unused SIO pin within your smartBASIC application script or Nordic application then SPI_CS is controlled from the software application allowing multi-dropping.
SIO pin direction
BL653 modules shipped from production with smart BASIC FW, all SIO pins (with default function of DIO) are mostly digital inputs (see Pin Definitions Table2). Remember to change the direction SIO pin (in your smartBASIC application script) if that particular pin is wired to a device that expects to be driven by the BL653 SIO pin configured as an output. Also, these SIO pins have the internal pull-up or pull-down resistor-enabled by default in firmware (see Pin Definitions Table 2). This was done to avoid floating inputs, which can cause current consumption in low power modes (e.g. StandbyDoze) to drift with time. You can disable the PULL-UP or Pull-down through their smartBASIC application.
Note: Internal pull-up, pull down takes current from VDD.

SIO_02 pin and OTA smartBASIC application download feature
SIO_02 is an input, set with internal pull-down (in FW). Refer to latest firmware release documentation on how SIO_02 is used for Over the Air smartBASIC application download feature. The SIO_02 pin must be pulled high externally to enable the feature. Decide if this feature is required in production. When SIO_02 is high, ensure nAutoRun is NOT high at same time; otherwise you cannot load the smartBASIC application script.
NFC antenna connector
To make use of the Laird Connectivity flexi-PCB NFC antenna, fit connector:
Description FFC/FPC Connector, Right Angle, SMD/90d, Dual Contact,1.2 mm Mated Height Manufacturer Molex Manufacturers Part number 512810594
Add tuning capacitors of 300 pF on NFC1 pin to GND and 300 pF on NFC2 pins to GND if the PCB track length is similar as development board.
nRESET pin (active low)
Hardware reset. Wire out to push button or drive by host. By default module is out of reset when power applied to VCC pins.
Optional External 32.768kHz crystal
If the optional external 32.768kHz crystal is needed, then use a crystal that meets specification and add load capacitors whose values should be tuned to meet all specification for frequency and oscillation margin.
SIO_38 special function pin
This is for future use by Laird Connectivity. It is currently a Do Not Connect pin if using the smartBASIC FW.
BL653 module RF pad variant 453-00041

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If using the BL653 module RF pad variant (453-00041), MUST copy the 50-Ohms GCPW RF track design, MUST add series 2nH RF inductor (Murata LQG15HN2N0B02# or Murata LQG15HS2N0B02) and RF connector IPEX MHF4 Receptacle (MPN: 20449001E) Detailed in the following section: 50-Ohms RF Trace and RF Match Series 2nH RF Inductor on Host PCB for BL653 RF Pad Variant (453-00041).
Checklist (for PCB): MUST locate BL653 module close to the edge of PCB (mandatory for the 453-00039 for on-board PCB trace antenna to
radiate properly). Use solid GND plane on inner layer (for best EMC and RF performance). All module GND pins MUST be connected to host PCB GND. Place GND vias close to module GND pads as possible. Unused PCB area on surface layer can flooded with copper but place GND vias regularly to connect the copper flood to
the inner GND plane. If GND flood copper is on the bottom of the module, then connect it with GND vias to the inner GND plane. Route traces to avoid noise being picked up on VDD, VDDH, VBUS supply and AIN (analogue) and SIO (digital) traces. Ensure no exposed copper is on the underside of the module (refer to land pattern of BL653 development board).
The 453-00039 has an integrated PCB trace antenna and its performance is sensitive to host PCB. It is critical to locate the 45300039 on the edge of the host PCB (or corner) to allow the antenna to radiate properly. Refer to guidelines in section PCB land pattern and antenna keep-out area for the 453-00039. Some of those guidelines repeated below. Ensure there is no copper in the antenna keep-out area on any layers of the host PCB. Keep all mounting hardware and
metal clear of the area to allow proper antenna radiation. For best antenna performance, place the 453-00039 module on the edge of the host PCB, preferably in the edge center. The BL653 development board has the 453-00039 module on the edge of the board (not in the corner). The antenna keep-
out area is defined by the BL653 development board which was used for module development and antenna performance evaluation is shown in Figure 9, where the antenna keep-out area is ~5 mm wide, ~39.95 mm long; with PCB dielectric (no copper) height ~1 mm sitting under the 453-00039 PCB trace antenna. The 453-00039 module on-board PCB trace antenna is tuned when the 453-00039 is sitting on development board (host PCB) with size of 125 mm x 85 mm x 1mm. A different host PCB thickness dielectric will have small effect on antenna. The antenna-keep-out defined in the Host PCB Land Pattern and Antenna Keep-out for the 453-00039 section. Host PCB land pattern and antenna keep-out for the BL653 applies when the 453-00039 is placed in the edge of the host PCB preferably in the edge center. Figure 9 shows an example.

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Antenna Keep-out

Figure 9: PCB trace Antenna keep-out area (shown in red), corner of the BL653 development board for the 453-00039 module.
Antenna Keep-out Notes:
Note 1 The BL653 module is placed on the edge, preferably edge centre of the host PCB. Note 2 Copper cut-away on all layers in the Antenna Keep-out area under the 453-00039 on host PCB.
Checklist (for metal /plastic enclosure): Minimum safe distance for metals without seriously compromising the antenna (tuning) is 40 mm top/bottom and 30 mm
left or right. Metal close to the 453-00039 PCB trace monopole antenna (bottom, top, left, right, any direction) will have degradation on
the antenna performance. The amount of that degradation is entirely system dependent, meaning you will need to perform some testing with your host application. Any metal closer than 20 mm will begin to significantly degrade performance (S11, gain, radiation efficiency). It is best that you test the range with a mock-up (or actual prototype) of the product to assess effects of enclosure height (and materials, whether metal or plastic).

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To use an external antenna, you need a BL653 module variant with RF pad (453-00041) and 50-Ohm RF trace (GCPW or Grounded Coplanar Waveguide) from RF_pad (pin 72) of the module (BL653 453-00041) to RF antenna connector (IPEX MHF4) on host PCB. On this RF path, you must use a 2nH series RF inductor. The BL653 module GND pin 0 and GND pin 66 are used to support GCPW 50-Ohm RF trace. Checklist for SCH MUST fit 2 nH RF inductor (R144) in series. RF inductor part number is Murata LQG15HN2N0B02# or Murata
LQG15HS2N0B02# with 0402 body size. https://www.murata.com/en- eu/products/productdetail.aspx?partno=LQG15HN2N0B02%23 https://www.murata.com/en- eu/products/productdetail.aspx?partno=LQG15HS2N0B02%23 MUST fit RF connector IPEX MHF4 Receptacle (MPN: 20449-001E), https://www.i-pex.com/product/mhf-4-smt#!
Figure 10: BL6653 RF pad variant (453-00041) Host PCB 50-Ohm RF trace schematic with series 2nH inductor, RF connector

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Layer1 (RF Track and RF GND)

Layer2 (RF GND) and Layer2 copper cut-out under RF connector

Figure 11: 50-Ohm RF trace design (Layer1 and Layer2) on BL653 development board (or host PCB) for use with BL653 (453-00041) module
Checklist for PCB: MUST use a 50-Ohm RF trace (GCPW, that is Grounded Coplanar Waveguide) from RF_pad (pin72) of the module
(BL653 453-00041) to RF antenna connector (IPEX MHF4) on host PCB.
To ensure regulatory compliance, MUST follow exactly the following considerations for 50-Ohms RF trace design and test verification:

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Solder Mask Layer1 Copper 0.5 oz+plating (Note1) Prepreg (2113)
Layer2 Copper 1 oz Core 0.6 mm Layer3 Copper 1 oz Prepreg (2113) Layer1 Copper 0.5 oz+plating Solder Mask

Thickness mil 0.4 1.3 4 1.4 24 1.4 4 1.3 0.4

Dielectric Constant Er
3.5
4.1
4.4 4.1 3.5

Stack up for 50 Ohms GCPW RF track.

Note 1: The plating (ENIG) above base 0.5 oz copper is not listed, but plating expected to be ENIG.

Figure 12: BL653 development board PCB stack-up and L1 to L2 50-Ohms Grounded CPW RF trace design
The 50-Ohms RF trace design MUST be Grounded Coplanar Waveguide (GCPW) with Layer1 RF track width (W) of 6.5 mil and Layer1 gap (G) to GND of 10mil and where the Layer1 to Layer 2 dielectric thickness (H) MUST be 4 mil (dielectric constant Er 4.1). Further the Layer1 base copper must be 0.5-ounce base copper (that is 0.7 mil) plus the plating and Layer1 MUST be covered by solder mask of 0.4 mil thickness (dielectric constant Er 3.5).
The 50-Ohms RF trace design MUST follow the PCB stack-up shown in Figure 12. (Layer1 to Layer2 thickness MUST be identical to the BL653 development board).
The 50-Ohms RF track should be a controlled-impedance trace e.g. ±10%.
The 50-Ohms RF trace length MUST be identical (as seen in Figure 12) (262.09mil) to that on the BL653 development board from BL653 module RF pad (pin72) to the RF connector IPEX MHF4 Receptable (MPN: 20449-001E).
Place GND vias regularly spaced either side of 50-Ohms RF trace to form GCPW (Grounded coplanar waveguide) transmission line as shown in Figure12 and use BL653 module GND pin0 and GND pin66.
Cut away copper on Layer2 GND layer under the RF connector IPEX MHF4 Receptable, as seen in Figure 12. This is to reduce RF detuning the 50Ohms of the RF connector (J49) when it sits on the PCB.
Cut away copper on Layer2 GND layer under the BL653 module RF pad (pin72), identical to the BL653 development board as seen in Figure 12.
Use spectrum analyzer to confirm the radiated (and conducted) signal is within the certification limit.

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Please refer to the regulatory sections for FCC, ISED, EU, RCM, KC, and Japan for details of use of BL653-with external antennas in each regulatory region.
The BL653 family has been designed to operate with the below external antennas (with a maximum gain of 2.0 dBi). The required antenna impedance is 50 ohms. See Table 24. External antennas improve radiation efficiency.

Table 24: External antennas for the BL653

Manufacturer

Model

Laird Connectivity Part Number

Type

Peak Gain Connector
2400-2500 MHz 2400-2480 MHz

Laird Connectivity
Laird Connectivity

NanoBlue FlexPIFA

Mag.Layers EDA-8709-2G4C1-B27-CY

Laird Connectivity
Laird Connectivity

mFlexPIFA Laird Connectivity NFC

EBL2400A110MH4L 001-0022
0600-00057 EFA2400A3S-
10MH4L 0600-00061

PCB Dipole PIFA Dipole PIFA NFC

IPEX MHF4 IPEX MHF4 IPEX MHF4 IPEX MHF4
N/A

2 dBi –
2 dBi –

2 dBi
2 dBi
–

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Figure 13: BL653 mechanical drawing

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Figure 14: Mechanical Details – Integrated Antenna

Figure 15: Mechanical Details – Trace Pin Development kit schematics can be found in the software downloads tab of the BL653 product page.

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Figure 16: Land pattern and Keep-out for the 453-00039

All dimensions are in millimeters.

Host PCB Land Pattern and Antenna Keep-out for the 453-00039 Notes:

Ensure there is no copper in the antenna `keep out area’ on any layers of the host PCB. Also keep all mounting Note 1 hardware or any metal clear of the area (Refer to 6.3.2) to reduce effects of proximity detuning the antenna and to
help antenna radiate properly.

Note 2

For the best on-board antenna performance, the module 453-00039 MUST be placed on the edge of the host PCB and preferably in the edge centre and host PCB, the antenna “Keep Out Area” is extended (see Note 4).

Note 3

BL653 development board has the 453-00039 placed on the edge of the PCB board (and not in corner) for that the Antenna keep out area is extended down to the corner of the development board, see section PCB Layout on Host PCB for the 453-00039, Figure 16. This was used for module development and antenna performance evaluation.

Note 4 Ensure that there is no exposed copper under the module on the host PCB.

Note 5 You may modify the PCB land pattern dimensions based on their experience and/or process capability.

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Laird Connectivity’s surface mount modules are designed to conform to all major manufacturing guidelines. This application note is intended to provide additional guidance beyond the information that is presented in the User Manual. This Application Note is considered a living document and will be updated as new information is presented.
The modules are designed to meet the needs of several commercial and industrial applications. They are easy to manufacture and conform to current automated manufacturing processes.

Figure 17: Reel specifications

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Figure 18: Tape specifications There are 1,000 x BL653 modules taped in a reel (and packaged in a pizza box) and five boxes per carton (5000 modules per carton). Reel, boxes, and carton are labeled with the appropriate labels. See Carton Contents for more information.
The following are the contents of the carton shipped for the BL653 modules.

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Figure 19: Carton contents for the BL653

Figure 20: BL653 packaging process The following labels are located on the antistatic bag:
M/N:453-00039 QTY:1000PCS
Figure 21: Antistatic bag labels

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The following package label is located on both sides of the master carton:
Figure 22: Master carton package label The following is the packing slip label:

Figure 23: Packing slip label

Prior to any reflow, it is important to ensure the modules were packaged to prevent moisture absorption. New packages contain desiccate (to absorb moisture) and a humidity indicator card to display the level maintained during storage and shipment. If directed to bake units on the card, see Table 25 and follow instructions specified by IPC/JEDEC J-STD-033. A copy of this standard is available from the JEDEC website: http://www.jedec.org/sites/default/files/docs/jstd033b01.pdf
Any modules not manufactured before exceeding their floor life should be re- packaged with fresh desiccate and a new humidity indicator card. Floor life for MSL (Moisture Sensitivity Level) 4 devices is 72 hours in ambient environment 30°C/60%RH.

Table 25: Recommended baking times and temperatures 125°C

90°C/ 5%RH

Baking Temp.

MSL

Saturated @
30°C/85%

Floor Life Limit + 72 hours @ 30°C/60%

Saturated @
30°C/85%

Floor Life Limit + 72 hours @ 30°C/60%

4

11 hours

7 hours

37 hours

23 hours

40°C/ 5%RH Baking Temp.

Saturated @ 30°C/85%

Floor Life Limit + 72 hours @
30°C/60%

15 days

9 days

Laird Connectivity surface mount modules are designed to be easily manufactured, including reflow soldering to a PCB. Ultimately it is the responsibility of the customer to choose the appropriate solder paste and to ensure oven temperatures during reflow meet the requirements of the solder paste. Laird Connectivity surface mount modules conform to J-STD-020D1 standards for reflow temperatures.

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Important:

During reflow, modules should not be above 260° and not for more than 30 seconds. In addition, we recommend that the BL653 module does not go through the reflow process more than one time; otherwise the BL653 internal component soldering may be impacted.

Figure 24: Recommended reflow temperature

Temperatures should not exceed the minimums or maximums presented in Table 26.

Table 26: Recommended maximum and minimum temperatures Specification Temperature Inc./Dec. Rate (max) Temperature Decrease rate (goal) Soak Temp Increase rate (goal) Flux Soak Period (Min) Flux Soak Period (Max) Flux Soak Temp (Min) Flux Soak Temp (max) Time Above Liquidous (max) Time Above Liquidous (min) Time In Target Reflow Range (goal) Time At Absolute Peak (max) Liquidous Temperature (SAC305) Lower Target Reflow Temperature Upper Target Reflow Temperature Absolute Peak Temperature

Value 1~3 2-4 .5 – 1 70 120 150 190 70 50 30
5 218 240 250 260

Unit °C / Sec °C / Sec °C / Sec
Sec Sec °C °C Sec Sec Sec Sec °C °C °C °C

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Note: For complete regulatory information, refer to the BL653 Regulatory Information document which is also available from the BL653 product page.

The BL653 holds current certifications in the following countries:
Country/Region USA (FCC) EU Canada (ISED) Japan (MIC) Korea (KC) Australia New Zealand

Regulatory ID SQGBL653 N/A 3147A-BL653 201-200063
R-C-L7C-BL653 N/A N/A

Part Number 453-00039R 453-00041R 453-00039C 453-00041C 453-00039-K1 453-00041-K1

Product Description BLE module (Nordic nRF52833) Integrated antenna (Tape/Reel) BLE module (Nordic nRF52833) Trace pin (Tape/Reel) BLE module (Nordic nRF52833) Integrated antenna (Cut Tape) BLE module (Nordic nRF52833) Trace pin (Cut Tape) Development Kit for Bluetooth +802.15.4 + NFC module Integrated antenna Development Kit for Bluetooth +802.15.4 + NFC module Trace pin (External antenna)

The BL653 module is listed on the Bluetooth SIG website as a qualified End Product.

Design Name
BL653

Owner
Laird Connectivity

Declaration ID QD ID Link to listing on the SIG website

D049591

147394 https://launchstudio.bluetooth.com/ListingDetails/104900

It is a mandatory requirement of the Bluetooth Special Interest Group (SIG) that every product implementing Bluetooth technology has a Declaration ID. Every Bluetooth design is required to go through the qualification process, even when referencing a Bluetooth Design that already has its own Declaration ID. The Qualification Process requires each company to registered as a member of the Bluetooth SIG www.bluetooth.org
The following link provides a link to the Bluetooth Registration page: https://www.bluetooth.org/login/register/
For each Bluetooth Design, it is necessary to purchase a Declaration ID. This can be done before starting the new qualification, either through invoicing or credit card payment. The fees for the Declaration ID will depend on your membership status, please refer to the following webpage:
https://www.bluetooth.org/en-us/test-qualification/qualification- overview/fees
For a detailed procedure of how to obtain a new Declaration ID for your design, please refer to the following SIG document:

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https://www.bluetooth.org/DocMan/handlers/DownloadDoc.ashx?doc_id=283698&vId=317486
To start a listing, go to: https://www.bluetooth.org/tpg/QLI_SDoc.cfm In step 1, select the option, Reference a Qualified Design and enter D049591 in the End Product table entry. You can then select your pre-paid Declaration ID from the drop-down menu or go to the Purchase Declaration ID page, (please note that unless the Declaration ID is pre-paid or purchased with a credit card, it will not be possible to proceed until the SIG invoice is paid. Once all the relevant sections of step 1 are finished, complete steps 2, 3, and 4 as described in the help document. Your new Design will be listed on the SIG website and you can print your Certificate and Declaration of Conformity. For further information, please refer to the following training material: https://www.bluetooth.org/en-us/test-qualification/qualification-overview /listing-process-updates
Note: If using the BL653 with Laird Connectivity Firmware and smartBASIC script, you can skip “Controller Subsystem”, “Host Subsystem”, and “Profile Subsystem”.

If you wish to deviate from the standard End Product design listed under D0xxxxx, the qualification process follows the Traditional Project route, creating a new design. When creating a new design, it is necessary to complete the full qualification listing process and also maintain a compliance folder for the new design.

The BL653 design under D049591 incorporates the following components:

Listing reference D043345 D043346

Design Name S140 Link Layer v7.0.1 S140 Host Layer v7.0.1

Core Spec Version 5.1 5.1

In the future, Nordic may list updated versions of these components and it is possible to use them in your new design. Please check with Nordic to make sure these software components are compatible with the nRF52833 hardware.

If your design is based on un-modified BL653 hardware it is possible use the following process;

1. Reference the existing RF-PHY test report from the BL653 listing. 2. Combine the relevant Nordic Link Layer (LL) check QDID with Nordic. 3. Combine in a Host Component (covering L2CAP, GAP, ATT, GATT, SM) – check QDID with Nordic. 4. Test any standard SIG profiles that are supported in the design (customs profiles are exempt).

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End Product
Laird RFNordic LL
Host Layers
Profiles
Figure 25: Scope of the qualification for an End Product Design The first step is to generate a project on the TPG (Test Plan Generator) system. This determines which test cases apply to demonstrate compliance with the Bluetooth Test Specifications. If you are combining pre-tested and qualified components in your design and they are within their three-year listing period, you are not required to re-test those layers covered by these components. If the design incorporates any standard SIG LE profiles (such as Heart Rate Profile), it is necessary to test these profiles using PTS or other tools where permitted; the results are added to the compliance folder. You are required to upload your test declaration and test reports (where applicable) and then complete the final listing steps on the SIG website. Remember to purchase your Declaration ID before you start the qualification process, as it’s impossible to complete the listing without it.

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The BL653 module went through the below reliability tests and passed.

Test Sequence 1

Test Item
Vibration Test

2

Mechanical

Shock

3

Thermal

Shock

Test Limits and Pass JESD22-B103B Vibration, Variable frequency
JESD22-B104C
JESD22-A104E Temperature cycling

Test Conditions

Sample: Unpowered. Sample number: 3. Vibration waveform: Sine waveform. Vibration frequency /Displacement: 20 to 80Hz /1.52mm. Vibration frequency /Acceleration: 80 to 2000Hz /20g. Cycle time: 4 minutes. Number of cycles: 4 cycles for each axis. Vibration axis: X, Y and Z (Rotating each axis on vertical vibration table). Sample: Unpowered. Sample number: 3. Pulse shape: Half-sine waveform. Impact acceleration: 1500g. Pulse duration: 0.5ms. Number of shocks: 30 shocks (5 shocks for each face). Orientation: Bottom, top, left, right, front and rear faces. Sample: Unpowered. Sample number: 3. Temperature transition time: Less than 30 seconds. Temperature cycle: -40 (10 minutes), +105 (10 minutes). Number of cycles: 350.

Before and after the testing, visual inspection showed no physical defect on samples.

After Vibration test and Mechanical Shock testing, the samples were functionally tested, and all samples functioned as normal. Then after Thermal shock test, the samples were functionally tested, and all samples functioned as normal.

Please contact your local sales representative or our support team for further assistance:
Laird Connectivity Support Centre: https://www.lairdconnect.com/resources/support Email: [email protected] Phone: Americas: +1-800-492-2320 Europe: +44-1628-858-940 Hong Kong: +852 2923 0610 Web: https://www.lairdconnect.com/products
Note: Information contained in this document is subject to change.

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© Copyright 2020 Laird Connectivity. All Rights Reserved. Patent pending. Any information furnished by Laird and its agents is believed to be accurate and reliable. All specifications are subject to change without notice. Responsibility for the use and application of Laird materials or products rests with the end user since Laird and its agents cannot be aware of all potential uses. Laird makes no warranties as to non-infringement nor as to the fitness, merchantability, or sustainability of any Laird materials or products for any specific or general uses. Laird Connectivity or any of its affiliates or agents shall not be liable for incidental or consequential damages of any kind. All Laird products are sold pursuant to the Laird Terms and Conditions of Sale in effect from time to time, a copy of which will be furnished upon request. Nothing herein provides a license under any Laird or any third-party intellectual property right.

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