ON Semiconductor NCP51820 HB GaN Driver Evaluation Board Owner’s Manual

ON Semiconductor NCP51820 HB GaN Driver Evaluation Board

Product Information

Specifications:

• Model: NCP51820GAN1GEVB
• Description: NCP51820 HB GaN Driver Evaluation Board
• High-speed, half-bridge GaN driver
• Designed for existing or new PCB designs
• High-side can float up to 650V referenced to SW
• Low-side can float up to 3.5V referenced to PGND
• Drive stages with matched propagation delays within 5 ns
• Rise and fall times can be set independently with a single resistor

Product Usage Instructions

Connection and Setup:

1. Connect the NCP51820 HB GaN Driver Evaluation Board to the power supply.
2. Ensure proper connections of high-side and low-side floating drive stages.
3. Adjust rise and fall times using a single resistor as needed.

Probe Access:

When probing the circuit, note the following access points:

• HS and LS gate drives, as well as SWN are accessible.
• HS gate drive can be probed with a high-voltage differential probe on HSGD and HSGR pins.
• LS gate drive can be probed using the plated holes for a tip-and-barrel probe measurement (LSGD).

Dead-Time Control:

The EVB has preset dead-time control which can be configured as per requirements. Ensure proper configuration for optimized performance.

Driver Enable/Disable:

The driver enable/disable feature allows control over the driver operation. Enable or disable the driver as needed for testing or operation.

FAQ

• Q: Can the NCP51820 HB GaN Driver EVB be used in various topologies?
  • A: Yes, the EVB is generic and can be used in any topology requiring a high-side/low-side FET combination.
• Q: What is the maximum rating of the GaN power switches?
  • A: The GaN power switches are rated up to 650V, 30A, suitable for half-bridge topologies operating from a PFC output in the range of 400V.

INTRODUCTION

Purpose

The NCP51820 HB GaN Driver Evaluation Board (EVB) is intended to replace the driver and power MOSFETs used in existing half−bridge or full−bridge power supplies. This EVB highlights the performance, simplicity and minimal number of components required to efficiently and reliably drive two gallium nitride power switches used in a high−voltage, totem pole configuration. Intended applications include off−line power converter topologies such as: LLC, phase−shifted full−bridge, totem pole PFC, active clamp flyback and forward, dual active−bridge, Phi−2 and high voltage synchronous buck. This document describes the NCP51820 HB GaN Driver EVB mated to a 400 V to 12.5 V LLC converter, as one commonly used example from the topologies listed.

NCP51820 GaN Driver Description

The NCP51820 high−speed, gate driver is designed to meet the stringent requirements of driving enhancement mode (E−mode), high electron mobility transistor (HEMT) and gate injection transistor (GIT) HEMT, gallium nitride (GaN) power switches in off−line, half−bridge power topologies. The NCP51820 offers short and matched propagation delays with advanced level shift technology providing −3.5 V to +650 V (typical) common mode voltage range for the high−side drive and −3.5 V to +3.5 V common mode voltage range for the low−side drive. In addition, the device provides stable and  reliable operation when used in high dV/dt environments up to200 V/ns. In order to fully protect the gates of the GaN power switches against excessive voltage, both NCP51820 drive stages employ separate, dedicated voltage regulators to accurately maintain the gate−source drive signal amplitude. The circuit offers active clamping of the driver’s bias rails thus protecting against potential gate−sourceover−voltage under various operating conditions. The NCP51820 offers important protection functions such as independent under−voltage lockout (UVLO), monitoring VDD bias voltage, VDDH and VDDL driver bias and thermal shutdown based on die junction temperature of the device. As shown in Figure 2, the Schmitt trigger, EN, HIN and LIN inputs are internally pulled LOW to assure the driver is always in a default ‘OFF’ state during initial application of VDD bias. Programmable dead−time control is available by the DT pin and can be configured to prevent or allow cross−conduction

The NCP51820 can be considered as having two independent high−side and low−side “floating” drive stages. The high−side can float up to 650 V referenced to SW and the low−side can float up to 3.5 V referenced to PGND, making it well suited for applications where the driver has to float above a low−side current sense resistor as described in “Connection Method #2” section. Each drive stage includes dedicated input level shifting to ensure accurately matched propagation delays to within 5 ns. Each output includes separate source and sink allowing rise and fall times to be set independently with a single resistor, eliminating additional, discrete circuitry often required for high−speed turn−off.

NCP51820 HB GaN Driver EVB Description

The NCP51820 HB GaN Driver EVB is designed using an 1180 mil x 1310 mil, four−layer printed circuit board (PCB) and includes the NCP51820 GaN driver, two E−mode GaN power switches connected in a high−side, low−side configuration and all necessary drive circuitry. The EVB does not include a PWM controller, and is generic from the point of view that it is not dedicated to any one topology, and can be used in any topology that requires the use of a high−side/low−side FET combination. The EVB can be connected into an existing power supply, and will replace the HS/LS driver and MOSFETs. The EVB has preset, but configurable dead−time control and driver enable/disable. The GaN power switches are rated up to 650 V, 30 A, making them well suited for half−bridge topologies operating from a PFC output in the range of 400 V. However, due to RDS(ON) temperature dependence, the maximum, practical case temperature should not exceed ~90°C (90°C = 1.6 x RDS(ON), normalized at 25°C). The EVB has only 23 components and its small size allows it to be installed in tight areas. Even with the small size, several pins are available to probe the circuit. HS and LS gate drives, as well as SWN are accessible. Note: In half−bridge operation, the HS gate drive can only be probed with a high−voltage differential probe on the Hi−Side Gate Drive (HSGD) pin and the Hi−Side Gate Return (HSGR) pin. The LS gate drive has two plated holes for a tip−and−barrel probe measurement (LSGD). The plated hole closest to the NCP51820 is probe GND, as shown in Figure 3. A tip−and−barrel measurement is performed by removing the “hat” from a passive probe and using the probe “pin” for the measurement and a spring pin fit on the GND barrel of the probe for ground. Figure 4 shows the typical tip−and−barrel measurement method for LSGD using a LeCroy passive probe and GND spring. Downloaded from

NCP51820 EVB Schematic

NCP51820 EVB Bill of Materials (BOM)

Table 1. NCP51820 EVB BILL OF MATERIALS

Item| Qty| Reference| Value| Part Number| Description| Manufacturer| Pkg Type
---|---|---|---|---|---|---|---
1| 1| C1| 10 pF| CC0402JRNPO9BN100| CAP, SMD, CERAMIC, 50 V, NPO| ****

Yageo

| 402
2| 1| C2| 1 µF| CL10B105KA8NNNC| CAP, SMD, CERAMIC, 25 V, X7R| ****

Samsung

| 603
3| 1| C4| 100 nF| CGA3E2X7R1E104K080AA| CAP, SMD, CERAMIC, 25 V, X7R| ****

TDK

| 603
4| 1| C5| 470 nF| CL05A474KA5NNNC| CAP, SMD, CERAMIC, 25 V, X5R| ****

Samsung

| 402
5| 1| C8| 0.1 µF| CC0402KRX7R8BB104| CAP, SMD, CERAMIC, 25 V, X7R| Yageo| 402
6| 2| C3,C7| 0.1 µF| C4532X7R2J104K230KA| CAP, SMD, CERAMIC, 630 V, X7R| TDK| 1812
7| 2| C6,C9| 1 µF| CGB2A1X5R1E105K033BC| CAP, SMD, CERAMIC, 25 V, X5R| TDK| 402
8| 1| D1| | ES1J| DIODE FAST REC 1 A 600 V| ON Semiconductor| SMA
9| 1| J1| | 61300611121| Connector, Header, 100Mil spacing| Wurth| Thru−Hole
10| 5| J2−6| | 1352−1| Testpin, Gold, 40mil| Keystone| Thru−Hole
11| 2| Q1−2| | GS66508B| GaN, 650 V, E−mode, 30 A, 50 mQ| GaN Systems| 7.1 ´ 8.5 mm
12| 1| R3| 2 Q| RC1005F2R0CS| RES, SMD, 1/16 W| Samsung| 402
13| 1| R4 (Note 1)| 60.4 kQ| RC0603FR−0760K4L| RES, SMD, 1/10 W| Yageo| 603
14| 1| R10 (Note 2)| 0 Q| RC0603JR−070RL| RES, SMD, 1/10 W| Yageo| 603
15| 3| R1−2, R5| 10 kQ| RC0402FR−0710KL| RES, SMD, 1/16 W| Yageo| 402
16| 2| R6, R8| 10 Q| RC0603FR−0710RL| RES, SMD, 1/10 W| Yageo| 603
17| 2| R7, R9| 2 Q| RC0603FR−072RL| RES, SMD, 1/10 W| Yageo| 603
18| 1| U1| | NCP51820| High Speed Half Bridge GaN Driver| ON Semiconductor| MLP 4 ´ 4−15
19| 1| | | 658−60AB| Heatsink (optional)| Wakefield−Vette| 1.1 ´ 1.1 in.
20| 1| | | LI98−28−28−0.25| Adhesive thermal isolator (optional)| ****

T−Global Technology

| 28 ´ 28 mm

1. R4 used to set dead−time (DT).
2. R10 used to connect SGND to LS gate return

NCP51820 Layers

• Top Layer: All EVB components are on the top layer. The large copper high current carrying etches used to connect the HS/LS GaN power switches also act as heat spreaders.
• Layer 2 (Internal): This layer has a shielding plane for the driver and driver components as well as additional high current carrying etches for the HS/LS GaN power switches.
• Layer 3 (Internal): Layer 3 has additional high current carrying etches for the HS/LS GaN power switches.
• Bottom Layer: The high current carrying etches for the HS/LS GaN power switches on the bottom layer also act as heat spreaders. A heatsink (if utilized) will be attached to this layer

NCP51820 EVB I/C Connections

Table 2. I/O CONNECTOR DESCRIPTION

VDD + 0.3 V
VDD| J1−2| Bias voltage for high current driver| 8 V < VDD < 20 V
GND| J1−3,6| Signal ground on the driver| 0 V
HIN| J1−4| Logic input for high−side gate driver| 0 V< HIN < VDD + 0.3 V
LIN| J1−5| Logic input for low−side gate driver| 0 V< LIN < VDD + 0.3 V
VBULK| J2 and PAD| VIN connection| 650 V max
SWN| J3 and PAD| Switch Node connection| 650 V max
PGND| J4 and PAD| Power Ground connection| 0 V

EN pin tied to driver VDD through 10 k resistor (R1) on EVB.

NCP51820 EVB CONNECTION METHODS

There are two different methods for connecting the EVB to an existing power board. Power topologies not using a current sense resistor connected in series with the LS GaN power switch source (a current sense transformer or other method of sensing current used) will use Connection Method #1, shown in “Connection Method #1” section. Power topologies using a current sense resistor (RCS) connected in series with the LS GaN source, will use Connection Method #2, shown in “Connection Method #2” section.

Preparing Power Board for EVB Connection

1. Remove HS and LS MOSFETs and HS and LS gate drive resistors from the power board as illustrated in Figure 8.
2. Remove any gate turn off circuitry. This is any circuit used to help drive the gate to 0 V during turn off.
3. Before connecting the EVB, ensure that VDD, HIN, LIN, and VBULK are within the parameters listed in Table 2.

Connection Method #1 − No GaN LS Current Sense Resistor on Power Board

Connect the EVB as shown in Figure 9. AWG #22 wire is suggested for LIN, HIN and VDD. AWG #18 or larger wire is suggested for VBULK, SWN and PGND. Keeping both the Input connections and the VBLK, SWN and PGND connections as short as possible is preferred.

Connection Method #2 − LS GaN Current Sense Resistor (RCS) Present on Power Board

Low−power applications, such as an active−clamp flyback or forward converter often use a current sensing resistor, RCS, located in the low−side GaN power switch-source leg. In such applications, the EVB PGND and SGND pins must be isolated on the EVB (normally connected by R10) because RCS would essentially be shorted through this resistor if not removed. The NCP51820 low−side drive circuit is able to withstand −3.5 V to +3.5 V of common mode voltage. Since most current sense voltage signals are less than 1 V, the low−side drive stage can easily “float” above the voltage, VRCS, generated by the current sense resistor. Connection Method #2: Remove R10 on the EVB to isolate LS gate drive return from GND as shown in Figure 10 and Figure 13. Failure to remove R10 will short out RCS. Connect the EVB as shown in Figure 10. AWG #22 wire is suggested for LIN, HIN and VDD. AWG #18 or larger wire is suggested for VBULK, SWN and PGND. Keeping both the input and power connections as short as possible is preferred.

External VDD

An external VDD can be used, as long as the HIN and LIN signals still fall within the parameters listed in Table 2. If an external VDD is used, the external VDD GND connection must be connected to the power board VDD GND, as shown in Figure 11. An external VDD can be used for boards either with or without an LS Current Sense Resistor. When using an external VDD, put a 1N4148 blocking diode (or similar 60 V, 1A minimum diode) in series with VDD + to protect the VDD supply. It’s also suggested to put a small electrolytic decoupling capacitor (example: 22 F, 35 V) across the External VDD supply output, as shown in Figure 11. VDD voltage should be measured and set after the blocking diode to take into account the voltage drop across the diode

Thermal Considerations

Applications where higher currents could cause GaN power switch temperatures to exceed 90°C (such as a high voltage, synchronous buck), a voltage−isolated adhesive heatsink can be attached to the bottom of the EVB. The GaN power switches on this EVB are bottom−cooled. Copper heat spreaders are part of the bottom layer of this EVB. A voltage−isolated adhesive heatsink attached to the EVB bottom will aid in reducing the GaN power switch temperatures. Figure 12 shows the positioning of a heatsink. NOTE: The heatsink is positioned so the input pins are exposed on the PCB bottom. A sample heatsink and adhesive thermal pad are listed as optional components on the BOM (Table 1).

CONFIGURING ENABLE

AND DEAD−TIME (DT)

Function and External Control

The NCP51820 GaN Driver EN is internally pulled low to SGND, so the driver is always defaulted to a disabled output status. Similar to HIN and LIN, EN is a Schmitt trigger TTL-compatible input. Pulling the EN pin above 2.5 V typical, enables the outputs, placing the NCP51820 into an active ready state. Due to the nature of high−speed switching associated with GaN power stages, and for improved noise immunity, the EN pin is tied to VDD through a 10−kΩ (R1) pull−up resistor and is bypassed by a 10 pF capacitor (C1). If an external enable signal is preferred, the external enable signal must conform to the value limits listed in Table 2. More information on EN control can be found in the NCP51820 datasheet. When using an external active enable signal, remove R1 and connect a signal to the EN pin on the EVB. The external enable signal GND must connect to the EVB GND. The 10 pF EN bypass capacitor (C1) on the EVB must remain installed. Refer to Figure 13 for R1 and C1 locations. DT Function and Mode Configuration Accurately ensuring some minimal amount of dead−time between the high−side and low−side gate drive output signals is critical for safe, reliable optimized operation of any high−speed, half−bridge power stage. The NCP51820 uses a voltage−configured, dead−time control pin (DT). The NCP51820 offers four unique mode settings to utilize dead−time in such a way to be fully compatible with any control algorithm. The EVB dead−time is preset to Mode B by a single, 60.4 kΩ resistor (R4) connected between the DT and SGND pins. This sets the dead−time voltage to 1.3 V, proportional to approximately 65 ns of dead−time. When adjusting the dead time is required, the resistor value can be changed, which will change the voltage level on the DT pin. Follow the instructions outlined In DT Mode Descriptions to change DT modes. For noise immunity, the DT pin is bypassed with a 0.1ΩF capacitor (C8). This capacitor must not be removed. More information on dead−time control can be found in the NCP51820 datasheet. Refer to Figure 13 for R4 and C8 locations.

DT Mode Descriptions

1. MODE A: Connect DT to SGND; When the DT pin voltage, VDT, is less than 0.5 V typical (RDT = 0 Ω), the DT programmability is disabled and fixed dead−time, anti−cross−conduction protection is enabled. If HIN and LIN are overlapping by X ns, then X ns of dead−time is automatically inserted. Conversely, if HIN and LIN have greater than 0 ns of dead−time then the dead−time is not modified by the NCP51820 and is passed through to the output stage as defined by the controller. This type of dead−time control is preferred when the controller will be making the necessary dead−time adjustments but needs to rely on the NCP51820 dead−time control function for anti−cross−conduction protection.
2. MODE B: Connect a 25 kΩ < RDT < 200 kΩ Resistor from DT to SGND; Dead−time is programmable by a single resistor connected between the DT and SGND pins. The amount of desired dead time can be programmed via the dead time resistor, RDT, between the range of 25 kΩ < RDT < 200 kΩ to obtain an equivalent dead−time, proportional to RDT, in the range of 25 ns < tDT < 200 ns. If either edge between HIN and LIN result in a dead−time less than the amount set by RDT, the set DT value shall be dominant. If either edge between HIN and LIN result in a dead−time greater than the amount set by RDT, the controller dead−time shall be dominant.
3. MODE C: Connect a 249 kΩ Resistor from DT to SGND; Connect a 249 kΩ resistor between DT and SGND to program the maximum dead−time value of 200 ns. The control voltage range, VDT, for assuring tDT = 200 ns is 4 V < VDT < 5 V.
4. MODE D: Connect DT to VDD; When the DT pin voltage, VDT, is greater than 6 V (pulled up to VDD through 10 kΩ resistor), anti−cross−conduction protection is disabled, allowing the output signals to overlap. If choosing this operating mode while driving a half−bridge power stage, extreme caution should be taken, as cross conduction can potentially damage power components if not accounted for. This type of dead−time control is preferred when the controller will be making extremely accurate dead−time adjustments and can respond to the potential of over−current faults on a cycle−by−cycle basis.
5. 

NCP51820 HB GaN DRIVER EVB TEST EXAMPLE

NCP51820 HB GaN Driver EVB Mated to a FAN7688 LCC Resonant 250 W Converter The NCP51820 HB GaN Driver EVB was mated to an LLC Resonant 250 W, 400 V to 12.5 V converter featuring ON Semiconductor’s FAN7688, a secondary−side LLC resonant, pulse frequency modulated (PFM) controller with dedicated Synchronous Rectification (SR) drive, which offers best in class efficiency for isolated DC/DC converters

As shown in Figure 14 and Figure 15, the NCP51820 HB GaN Driver EVB is being used to replace the MOSFETs and driver circuitry in a FAN7688 250 W, 400 V to 12.5 V LLC converter. The FAN7688 board MOSFETs and gate drive resistors were removed. The EVB was wired into the board with the power connections coming from VIN, SWN and Power GND on the main board and VDD, GND, HIN and LIN coming from the FAN7688 PWM controller. Because VDD for the FAN7688 LLC converter is 12 V, the main board VDD was used for the EVB VDD. An external enable was not needed, so the existing pull up resistor, R1 (10 kΩ) on the EVB was left installed. The preset dead−time resistor, R4 (60.4 kΩ) ~ 65 ns was also left as−is on the EVB. Test Conditions The FAN7688/NCP51820 HB GaN Driver EVB was powered up using a 12 V bias for VDD, a high−voltage DC source for VIN and an electronic load for VOUT. The test board was operated at 380 VIN, 400 VIN and 12.5 VOUT, with output currents of 2 A, 5 A, 10 A, 15 A and 20 A. No EVB heatsink was needed for this test, as the input RMS currents were less than 2 A for all output conditions. The 380 VIN, 12.5 V, 20 A out waveform measurements are shown in Figure 16. The 400 V, 12.5 V, 20 A out waveform measurements are shown in Figure 17. A thermal image of the EVB running at 400 VIN, 12.5 V at 20 A out, is shown Figure 18.

Figure 18 shows a thermal image of EVB operating at 400 V in, 100 kHz, 12.5 V, 20 A out. This test was performed without an EVB heatsink, and in still air. In this test condition, the HS and LS GaN power switches, as well as the NCP51820 driver do not exceed 40°C.

CONCLUSION

When using this EVB with an existing silicon (Si) half−bridge power stage at normal Si frequencies (40−500 kHz), the true benefits of GaN technology (higher running frequencies, smaller magnetics, higher power density) will not be realized at the lower frequencies that Si typically operates. The goal of this EVB is to easily enable the evaluation of the NCP51820 GaN driver, mating it with existing half−bridge power topologies, and not to significantly change their operation or efficiency. This EVB can be run at high frequencies, but care must be applied to both the input signals and the power connections to be as short as possible to avoid noise injection and ringing. More information on GaN driver PCB design and layout techniques are available at ON Semiconductor/NCP51820. onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. The evaluation board/kit (research and development board/kit) (hereinafter the “board”) is not a finished product and is not available for sale to consumers. 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