TE connectivity 35GC007 STRADA Whisper 3.9mm 100-Ohm Pair-In-Row Vertical Header Connector Instruction Manual

TE connectivity 35GC007 STRADA Whisper 3.9mm 100-Ohm Pair-In-Row Vertical

Header Connector

INTRODUCTION

As engineers design systems that attempt to push serial speeds across backplane environments in the tens of gigabits per second range, the selection of the system’s electrical connector becomes more significant. Electrical, mechanical, and manufacturing aspects of the connector must be considered simultaneously. At the board level these aspects combine with common board design practices to influence the design of the connector-to-board interface and how the board itself will be routed. The manner in which the connector is designed into the system can significantly impact the system’s intended performance. TE has been actively researching these areas in an effort to help customers use the STRADA Whisper connector in multi-gigabit serial systems. The combination of interconnect research and intimate knowledge of the connector is presented to provide insight into the capability of a STRADA Whisper-based system design. Furthermore, this document provides specific design recommendations that will address layout, electrical performance, and manufacturability tradeoffs of the connector at the board level.

CONNECTOR OVERVIEW: STRADA WHISPER

BACKGROUND

Figure 1: STRADA Whisper Vertical Header Connector

The STRADA Whisper connector is the first of the next generation of high speed backplane interconnects offered by TE. A revolutionary performance upgrade is a result of the extremely low noise characteristics of the individually shielded pairs which provide improved signal integrity and EMI performance over competitive products. The in-row “horizontal” pair orientation enables the STRADA Whisper connector to have zero intra-pair skew.

FEATURES

• 56 Gb/s performance
• Individual shielded pairs facilitate excellent signal integrity and EMI performance
• Connector noise <0.5% @ 20 ps signal edge rate
• Connector insertion loss < 1.0dB (<1.5dB on 12 pair connector) at 12.5GHz
• Skewless in-pair
• Optimized PCB footprint design
• Continual signal pair balance throughout the connector
• Backplane uses eye of needle (EON) press-fit technology
• Compatible with existing card cage and connector mechanical envelopes
• Redundant points of contact in mating interface

APPLICATIONS

Designed for high speed or high signal quality applications that require serial data rates up to 56 Gb/s with superior signal integrity performance.

TYPICAL IMPLEMENTATIONS

RIGHT-ANGLE DIFFERENTIAL
STRADA Whisper is a high-speed connector that is typically implemented in differential applications. Although it can be implemented in single-ended applications as well, some additional grounding may be required depending upon the application. The variety of application spaces in which STRADA Whisper can be used are numerous, so the most common implementation space is described below. STRADA Whisper is available in various pair count configurations. In this document the 8-pair configuration will be used as an example. For the 8-pair configuration each differential column contains eight pairs in a 1.0” card-pitch module size. The connector has individually shielded pairs for excellent SI and EMI performance.

CONNECTOR DEFINITION

The following sections describe the STRADA Whisper backplane footprint. CAD models which include full mechanical dimensioning and tolerances are available for the STRADA Whisper connector and can be located at www.te.com. For overall dimensions, please refer to the latest customer drawings for the specific part that you are using. For other related usage information, please refer to the application specification for the STRADA Whisper product family.

BACKPLANE FOOTPRINT
Figure 2 depicts the dimensions of the via locations in the backplane footprint.

DRILLED HOLE DIMENSIONS
The dimensions critical to routing of the STRADA Whisper backplane connectors are related to the hole pattern, or “footprint”, of the connector. Table is provided to quickly identify critical hole dimensions for the circuit board. These sizes may vary slightly depending on the surface finish as noted in the application specification. Table provides typical hole size values. Although PCB drill bit manufacturers have 0.42mm, and 0.45mm drill bits available, not all PCB fabricators stock every drill size. It is suggested to check the intended PCB fabricator to ensure that the required drill sizes are procured prior to fabrication. Given today’s PCB fabrication capabilities for aspect ratio (the thickness of the PCB divided by the smallest drill diameter) boards with aspect ratios higher than ~12:1 can limit the number of fabricators that can successfully build the PCB in volume production. For the Whisper backplane footprint, with a drill hole size of 0.0165”, a 0.200” thick PCB would have a 12:1 aspect ratio.

Hole Dimension| Backplane Signal Hole

Diameter mm (in.) No-step drill

| Backplane GND Hole

Diameter mm (in.)

---|---|---
Drill Hole Size| 0.420 ± 0.025| 0.450 ± 0.025
(0.0165 ± 0.001)| (0.0177 ± 0.001)
Finished Hole Size| 0.340 ± 0.050

(0.0134 ± 0.002)

| 0.370 ± 0.050

(0.0146 ± 0.002)

Hole Copper Thickness| 0.025 Min (0.001 Min)| 0.025 Min (0.001 Min)

Table 1: Backplane Connector Hole Dimensions

FABRICATION TECHNOLOGY
Other important dimensions for board layout are also determined by the capabilities of the circuit board fabricator. Current high-tech PCB industry fabrication technology (i.e. capability) requires minimum pad sizes ranging from D+8 mils through D+16 mils, where “D” is the diameter of the drilled hole size (1 mil, or 0.001”, is 0.0254 mm). The resulting pad size for a given technology is typically defined as the minimum pad size required to maintain 0.05 mm (0.002″) of annular ring for a given PCB manufacturer’s capability. Annular ring is an industry standard measure of the clearance between the pad edge and worst-case drill edge after manufacturing. For the STRADA Whisper backplane footprint this requirement results in minimum pad sizes ranging from 0.622mm (0.0245″) to 0.826 mm (0.0325″). Because STRADA Whisper is typically used in high speed or dense applications where routing issues are most significant, it is recommended that all pad dimensions be no larger than D+10 mil. The pad diameter may be optimized for specific project needs, and should be evaluated on a project and vendor basis. Designing with a D+8 mil technology PCB or smaller will improve electrical performance, but could mean reduced yields or breakout, potentially adding cost to the PCB or violating industry specification compliance. Designing with a larger than D+10 mil pad size reduces electrical performance by increasing the capacitance of the plated through-hole to nearby pads, vias and traces. Where possible, the largest appropriate pad size should be used to provide the PCB manufacturer with the greatest flexibility, thereby reducing overall system costs as long as it meets the performance requirements of the system.

Note: The remainder of the document will assume a D+10 fabrication technology and a minimum pad to trace clearance of 0.127 mm (0.005″) for calculating routing dimensions.

PAD SIZE
Based upon the D+10 mil fabrication recommendation, a 0.674 mm (0.0265″) diameter pad should be used on all STRADA Whisper backplane connector internal signal layers. For higher-tech PCBs (D+8 mil) the internal pad would be 0.622 mm (0.0245”). A
(D+6) or 0.572mm (0.0225”) pad is recommended on external layers. Table 1 summarizes different pad sizes for different manufacturing capabilities.

 |

High-tech

| Internal Layer Pad Size|

Low tech

---|---|---|---
D+8| D+10| D+12| D+14| D+16
BP Connector Signal Pins

w/out step drill

| 0.622 mm

(0.0245”)

| 0.674 mm

(0.0265”)

| 0.724 mm

(0.0285”)

| 0.775 mm

(0.0305”)

| 0.826 mm

(0.0325”)

Table 1: Pad sizes for STRADA Whisper Vertical Header Connector

NON-FUNCTIONAL PADS
The removal of non-functional internal pads will improve signal integrity and manufacturability of the PCB. However, some assembly facilities prefer that unused pads are retained in order to maintain hole integrity through various soldering processes. For electrical reasons it is recommended that unused pads be removed on internal layers. Additionally, landless pads (D+6 or smaller) are recommended for external layers that do not have signal connections to the connector pad.

THERMAL RELIEFS
Thermal reliefs are not required on ground or power pins, because the STRADA Whisper connector uses a press-fit technology. A direct connection to reference and power planes will offer the lowest inductance connection to the circuit board.

ANTIPAD SIZE
Antipads, or plane clearances (Figure 3), are required to separate signal holes from reference voltages to avoid shorting. Choosing the proper size of these clearances is critical in determining several other design parameters: signal integrity, EMI, voltage breakdown, and manufacturability. Determining the proper antipad size for STRADA Whisper depends upon system design goals. Several scenarios are described below. Antipad sizes are minimized:

• To reduce noise by closely shielding adjacent pins with reference planes
• To reduce EMI by minimizing aperture sizes in reference planes
• To maintain a strong reference to ground for single-ended traces and ground referenced differential traces

Antipad sizes are maximized:

• To maximize voltage breakdown spacing between the pin and the reference plane
• To increase manufacturability by reducing the chance of shorting.
• To reduce reflections in a high-speed gigabit serial system by reducing the capacitive effect (if present) of the plated through-hole.

In cases where antipads are minimized, the recommended antipad size is the pad diameter plus 0.254 mm (0.010”). This size maximizes trace coverage, while not risking shorting the plane to the barrel in the case of drill breakout. Using a minimal antipad will increase the capacitance of the via and could degrade system performance at high speeds. When antipads are maximized, the antipad geometry is dependent on the type of signals passing through the vias. The suggested antipad structure for differential signals encompasses two adjacent signal vias. This structure minimizes the via capacitance for both vias, while maintaining coupling between the two signals within the differential pair. The recommended antipad is designed to balance routable trace widths and associated ground coverage with the minimization of via capacitance. The antipad geometry may be adjusted to further optimize both, once a design specific trace geometry and fabrication technology is determined. Figure and Error! Reference source not found. detail the recommended standard and antipad reduction dimensions for the STRADA Whisper backplane connector. An antipad reduction is a smaller sized antipad that is used on layers above and below trace routing to increase performance by avoiding an inductive breakout from the via. Figure and Table 3 detail the recommended antipad dimensions for the backplane connector. These resulting antipad dimensions of 2.195 mm (.0864”) x 1.796 mm (.0707”) represent a geometry which maximizes routable trace widths and associated ground coverage, yet maintains a level of performance intended for high-speed 100Ω designs. Routing geometries that are achievable are discussed further in section IV.

Table 3: Backplane Standard and Antipad Reduction Dimensions
The recommended antipad size on power planes should be the same or greater than the antipads on the ground planes. However, if the planes are hazardous high voltage power, noisy, or are tightly spaced with small dielectrics separating the planes it is recommended to completely remove the planes within the connector pinfield.

HIGH SPEED VIA DESIGN

At gigabit speeds, one of the limiting factors in system design is the effect caused by the via stub in the board. A via stub is the portion of the via that is not in series with the transmission path of the signal, as shown in Figure 5. At high frequencies, this parallel path creates a significant capacitive discontinuity, which degrades the throughput of the link. Although it has a small impact at lower frequencies, this stub typically becomes critical at speeds greater than 3.125 Gbps. STRADA Whisper was designed to allow for various techniques to be applied to treat the via and remove the stub, without impacting the press-fit contact in the hole. When the connector is fully seated, the bottom tip of the eye of needle (EON) pins extend slightly beyond 1.0 mm (0.039”) into the hole. Because the connector only requires 1.0mm (0.039”) of via length, beyond that depth, various techniques can be employed to modify the via to eliminate the stub. Consult your board fabrication facility regarding their capabilities for these techniques.

COUNTERBORING (I.E. BACKDRILLING)

Counterboring is a technique that has been used for years by the microwave industry to treat vias in microwave designs. With digital signaling approaching microwave frequencies, similar techniques can be employed to enhance the signal integrity of a link. Counterboring is performed as one of the final steps in the board manufacturing process. After the multilayer board is laminated, drilled, and plated, designated holes are control-depth drilled to remove any via stub that is present. This controlled-depth drill should allow a minimum length of barrel to remain in the hole to allow the eye-of- needle to engage the via. Figure 6 illustrates a counterbored via. The minimum remaining via depth (after counterboring) is 1.0 mm (0.039”) for the EON pins. For routing that occurs on layers above this minimum, a stub will exist and will degrade the throughput of the link.

BLIND VIAS
An alternative approach that is equally as effective as counterboring is the use of blind vias. Like counterboring, care must be taken to ensure that the depth of the blind via is sufficient to fully engage the eye-of-needle and accommodate the entirety of the pin tip. Due to the additional operations needed in manufacturing for blind vias manufacturing costs will be higher

than a typical multilayer board with the same number of layers. Care should be taken to ensure successful cleaning of the via such that long-term reliability is maintained. Figure 7 illustrates a blind via. Consult Product Engineering for via depth guidance.

STEP DRILL
An alternative approach that is less effective than counterboring is the use of step drill via technique. Like counterboring, care must be taken to ensure that the depth of the step drill is sufficient to fully engage the eye- of-needle and accommodate the entirety of the pin tip. Due to the additional operations needed in manufacturing for step drill vias manufacturing costs will be higher than a typical multilayer board with the same number of layers. Figure 8 illustrates a step drill via. Stub will still exist and will degrade the throughput of the link, however the drill is smaller at bottom layers and might help to reduce this effect as well as allowing additional space for the routing channel.

Table 4: Hole Dimensioning For Step Drill Via Implementation

Hole Dimension

| Signal EON via drill

section diameter mm (in.)

| Step Drill

section diameter mm (in.)

---|---|---
Drill Hole Size| 0.420 ± 0.025

(0.0165 ± 0.001)

| 0.305 ± 0.025

(0.0120 ± 0.001)

Finished Hole Size| 0.340 ± 0.050

(0.0134 ± 0.002)

| A/R
Hole Copper Thickness| 0.025 Min

(0.001 Min)

| A/R

ROUTING

The STRADA Whisper connector can be used for both single-ended and differential signals, however only the more common routing of differential signals will be examined.

BACKPLANE ROUTING

ROUTING CHANNELS
The connector’s routing channel is defined by the space between adjacent vias in the connector pinfield that is available for trace routing. Typical routing is implemented horizontally (between columns of vias), as shown in Figure. With a D+10 mil pad size, the remaining space allows different track width and intra-pair spacing. The wider track would be 7-mil differential lines with 7-mil intra-pair spacing, or alternatively 6-mil differential lines with 9-mil intra-pair spacing. In board materials with dielectric constant values in the 3 to 4 range, these geometries will provide well matched common and differential impedances in typical board stackups. These differential trace geometries also allow for a 5-mil antipad to trace clearance and an 8-mil ground drill to trace clearance. In this example, the bends are routed at 30º angles for the backplane routing. Although smaller differential geometries will fit within the routing channel, care should be taken if increasing the trace width and spacing from these recommendations due to manufacturing tolerances that could affect electrical performance. When using pair geometries smaller than the above examples, it is advised to bias the pair away from the antipad (not centered in the channel), while maintaining recommended spacings to the column of ground vias that is shared between adjacent routing channels. When implemented the minimum edge-of-trace to edge- of-trace spacing between pairs should be approximately .3512mm (.0138”) on the backplane.

Vertical routing is also possible through the STRADA Whisper pinfield, but this type of routing should be performed with care to avoid routing over openings in the ground plane. When vertical routing is required, antipads should be reduced to provide appropriate coverage for signals. Note that this practice will increase the capacitance of associated vias and will typically decrease the throughput of those vias.

ALTERNATIVE ROUTING
As noted in the previous section 30º is ideally used in the routing channel to match the antipad geometry. 45º routing can also be implemented with sufficiently small differential trace geometries, or with minor signal degradation as long as the antipads are adjusted to maintain the same trace to antipad and trace to ground clearances. In order to route straight through the pinfield a trace geometry must be used that does not exceed 17-mils. For example 5-mil differential lines with 7-mil intra-pair spacing can be routed straight.

ESCAPE ROUTING

The recommended escape routing from the connector pin has been designed in a way that results in zero skew in the differential trace. Figure 30 illustrates the escape routing for a differential pair consisting of signal vias marked as 1 and 2. Escape routing for via 1 runs from point A (on its corresponding pad) to point B. Similarly, escape routing for via 2 runs from point C on its pad to point D. Notice that point B and D coincide with a straight reference line passing through the center of the ground vias between differential via pairs. The physical route length of the trace between point A and B should be equal to the physical length of the trace between point C and D. The initial width, starting at the via, of the escape traces between A and B as well as between C and D, should be equal to the value which provides a single ended trace impedance of 50 Ohms for the given stack-up and the dielectric properties. As the escape traces come closer to each other, their widths should be changed to the width of the differential traces in the rest of the system beyond points B and D. It is recommended to transition the trace width at that point where the spacing between the single-ended traces becomes the same as the spacing between the legs of the differential pair. At no point should any portion of the trace pair have a spacing smaller than the differential spacing. Not only should the physical route length of the trace between point A and B be equal to the physical length of the trace between point C and D, but also the lengths of the single-ended portions of both legs should be equal. Since the physical length of the differential traces beyond points B and D are equal, having ensured equal length escape traces between point A and B and between point C and D, ensures that the overall routing from a via pair to the destination via pair is electrically skew-less. As with all routing, escape traces should maintain a minimum manufacturing distance between trace edges and ground vias of 0.2mm (.008”). As mentioned in Section III.A.2.d, it should be noted that antipad reduction is necessary for the backplane footprint only on the layers above and below the layer where traces escape from the footprint vias, to provide ground coverage for the trace between point A and B.

LAYER COUNT ANALYSIS
illustrates the typical routing technique for the 8-pair backplane and daughtercard connectors. Typically the 8-pair connector is routed in 4 layers, because there are two available routing channels for each pair. By allowing routing out the end of the connector footprint, the layer count can be further reduced. Antipad reductions, shown in the vertical routing technique, are only necessary on layers above and below trace routing to avoid inductive breakout. For a 4-pair connector configuration, 2 layers or fewer are needed to route out, and for a 12-pair configuration 6 layers or fewer are needed.

LAYER SPECIFIC ROUTING
Layer Specific Routing (LSR) is the use of a specific routing layer for each connector pair based upon performance criteria. It is recommended to implement LSR in order to reduce far end crosstalk in the via field. When counterboring or other stub removal techniques are used, this configuration reduces the amount of coupling of each signal via to its neighboring signals. Table – Table 6 show examples of LSR configurations for both the backplane connector when 4 or 6 routing layers are available. The value within the table represents the routing layer that each pair should reside on. Four or six columns of the connector are shown for reference, but the pattern continues for additional columns of the connector.

Table 5: 4-layer LSR recommendation for 8-pair backplane connector

Table 6: 6-layer LSR recommendation for 12-pair backplane connector

GENERAL

PINOUT RECOMMENDATION
In order to reduce noise within the connector pinfield, an interstitial transmit and receive pin assignment is recommended. An interstitial pin assignment, similar to a checkerboard pinout, is an alternating pattern of transmit and receive signals as shown in Figure 52.

EXAMPLE STACKUPS AND MATERIAL CHARACTERISTICS
The stack heights and material properties shown in Figure 63 and Figure 74 were used to achieve 100Ω impedances for the 6-9-6 and 7-7-7 channel and escape routing scenarios illustrated in Section IV, for both backplane case.

RECOMMENDED ROUTING TECHNIQUES

RIGHT-ANGLE BENDS
It is recommended to avoid using right-angle bends (90°). Use of two 45° bends or radiused corners is recommended. Less sharp turns will minimize the impedance discontinuity resulting in a reduction of reflection on the signal at the bend.

PART PLACEMENT

Part placement and spacing guidelines as well as associated up-to-date mechanical dimensions should be obtained in addition to this document. Placement related information is contained within the application specification, document #114-32029. The full mechanical dimensioning and tolerances are available for all versions of the STRADA Whisper connector within the customer drawing for the specific part number of interest. All of this information can be found at www.te.com, and also by contacting either your local TE sales support or the appropriate contact listed below in Section VIII.

ADDITIONAL INFORMATION

GIGABIT RESEARCH AND GENERAL APPLICATION NOTES
More information regarding TE research into the transmission of electrical signals at gigabit speeds or general application notes is available for download at http://www.te.com/usa-en/utilities/electrical-models.html

ELECTRICAL MODELS
Electrical S-parameter models for the STRADA Whisper may be requested at modeling@te.com.

WEBSITE
More information regarding the STRADA Whisper connector can be found on the web at www.te.com/products/stradawhisper

CONTACT INFORMATION

The following contact can be used to obtain additional information on the STRADA Whisper product family and other connector related issues.

• Technical Support Center 1-800-522-6752 www.te.com/help
• Information is TE Confidential & Proprietary. Do Not Reproduce or Distribute
• Downloaded from Arrow.com.

References

• STRADA Whisper High Speed Backplane Connectors | TE Connectivity
• Electrical Models and Simulation | TE Connectivity

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