NXP AN14179 Based Micro Controllers User Guide
- September 27, 2024
- NXP
Table of Contents
- AN14179 Based Micro Controllers
- Specifications
- Product Usage Instructions
- Step 1: Understanding the Migration Guide
- Step 2: Assessing Application Compatibility
- Step 3: Porting Applications
- Step 4: Testing and Validation
- Q: What are the key differences between MCXNx4x and
- Q: How can I migrate my applications from MCXNx4x to
AN14179 Based Micro Controllers
“`html
Specifications
-
Core Platform: Arm Cortex-M33 up to 150 MHz
with TrustZone, MPU, FPU, SIMD, DSP -
SmartDMA
-
System Control: Power control, Clock
generation unit, PMC, Secure DMA0, Secure DMA1, Secure AHB bus -
Analog: 4x 16 b ADC, Temp sensor, 2x ACMP,
Glitch detect, VREF -
Interfaces: 8x LP flexcomm supporting UART,
SPI, I2C, 4ch SAI, 2x CAN-FD, USB HS, 2x I3C -
Memory: Flash up to 512 kB, RAM up to 320 kB,
ECC RAM 32 kB -
HMI: FlexIO, DMIC
-
Security: PKC, ECC-256, SHA-512, RNG AES-256,
Multi-Rate Timer, Windowed WDT, Debug auth., PRINCE, RTC with
anti-tamper pins -
General Purpose Timers: 5x 32 b Timers
-
Other Features: Micro-Tick Timer, DICE + UUID,
PFR, SRAM PUF, 2x FlexPWM with 2 QDC module, OS Event Timer, 2x
Code WDG, OTP, Tamper detect
Product Usage Instructions
Step 1: Understanding the Migration Guide
Read through the migration guide provided from MCXNx4x to
MCXN23x to understand the differences and changes in the
platforms.
Step 2: Assessing Application Compatibility
Check if your current applications on MCXNx4x are compatible
with the MCXN23x platform. Identify any specific features or
peripherals that may need modification.
Step 3: Porting Applications
Follow the guidelines in the migration guide to port your
applications from MCXNx4x to MCXN23x. Make necessary code changes
based on the platform variations.
Step 4: Testing and Validation
After porting the applications, thoroughly test them on the
MCXN23x platform to ensure proper functionality and
performance.
Frequently Asked Questions (FAQ)
Q: What are the key differences between MCXNx4x and
MCXN23x?
A: MCXN23x is a cropped version of MCXNx4x with some
co-processors and peripherals removed. The MCX series MCU is
divided into subseries N, A, L, and W.
Q: How can I migrate my applications from MCXNx4x to
MCXN23x?
A: Refer to the migration guide provided by NXP that outlines
the steps to migrate applications between the two platforms. Ensure
compatibility and make necessary adjustments in the code.
“`
AN14179
Migration Guide from MCXNx4x to MCXN23x
Rev. 1 — 6 May 2024
Application note
Document information
Information
Content
Keywords
AN14179, MCXNx4x, MCXN23x, migration guide
Abstract
This application note describes the differences between MCXNx4x and MCXN23x and guides customers on how to quickly migrate applications from the MCXNx4x platform to the MCXN23x platform.
NXP Semiconductors
AN14179
Migration Guide from MCXNx4x to MCXN23x
1 Introduction
The MCXNx4x is a new-generation MCU launched by NXP after Kinetis and LPC. It
integrates excellent IP from both Kinetis and LPC platforms, such as CMC,
FlexCAN, FlexIO, and SPC from the Kinetis platform and PowerQuad, SmartDMA,
PINT, RTC, and MRT from the LPC platform. The MCX series MCU is divided into
four subseries: N, A, L, and W.
· MCX N (Neural): 150 MHz, 512KB-2MB On-chip accelerators, enhanced
peripherals, and advanced security
· MCX A (All-purpose): Up to 96 MHz, 32KB-1MB Intelligent peripherals and
various device options for a wide range of applications
· MCX W (Wireless): Up to 96 MHz Low-power Bluetooth LE, Thread, and
Zigbee radio optimized for IIoT and Matter applications and advanced security
· MCX L (Low-power): Below 50 MHz, up to 1 MB Optimized for always on
battery operated applications with the lowest active power and leakage
The MCXNx4x series microcontrollers combine the Arm Cortex-M33 TrustZone core
with a CoolFlux BSP32, a PowerQuad DSP Co-processor, and multiple high-speed
connectivity options running at 150 MHz. To support a wide variety of
applications, the MCX N series includes advanced serial peripherals, timers,
high-precision analog, and state-of-the-art security features like secure user
code, data, and communications. All MCXNx4x products include dual-bank flash,
which supports read-while-write operation from internal flash. The MCXNx4x
series also supports large external serial memory configurations.
The MCXNx4x MCU families are as follows:
· N54x: Mainstream MCU with a second M33 core, advanced timers, analog and
high-speed connectivity, including high-speed USB, 10/100 Ethernet, and
FlexIO, which can be programmed as an LCD controller.
· N94x: Integration of CPU and DSP serial connectivity, advanced timers, high
precision analog, and highspeed connectivity, including high-speed USB, CAN
2.0, 10/100 Ethernet, and FlexIO, which can be programmed as an LCD
controller.
MCXN23x is the second product in the MCX N series. It can be regarded as a
cropped version of MCXNx4x. Almost all IPs are reused from MCXNx4x, and some
co-processors and peripherals are removed. These removed modules are as
follows:
· Co-processor: Secondary Cortex-M33 Core, PowerQuad, NPU, CoolFlux BSP32, and
so on. · Peripherals: FlexSPI, uSDHC, EMVSIM, Ethernet, 12-bit DAC, 14-bit
DAC, and so on.
This document describes how to migrate applications from the MCXNx4x platform
to the MCXN23x platform.
The system block diagram of MCXN23x is shown in Figure 1.
AN14179
Application note
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Rev. 1 — 6 May 2024
© 2024 NXP B.V. All rights reserved.
2 / 24
NXP Semiconductors
AN14179
Migration Guide from MCXNx4x to MCXN23x
Core platform
Arm cortex-M33 up to 150 MHz Trustzone, MPU, FPU, SIMD, DSP
SmartDMA
System control
Power control Single Vdd power supply, POR, LVD/HVD, DCDC converter, Core LDO,
IVS, system LDO, VBAT RAM LDO,
VBAT switch
Clock generation unit FRO12M, FRO144M, 2x PLLs, XTAL32K, XTAL40M, clock out
PMC
Secure DMA0
Secure DMA1
Secure AHB bus
Analog
4x 16 b ADC 2 Msps 16 bit 3.15 Msps 12 bit
Temp sensor
2x ACMP
Glitch detect
VREF
Interfaces
8x LP flexcomm supports UART, SPI, I2C
4ch SAI 2x CAN-FD
USB HS 2x I3C
Flash up to 512 kB
Memory
Flash up to 512 kB
Flash cache
HMI
FlexIO
DMIC
RAM up to 320 kB
ECC RAM 32 kB
ROM boot + power API
General purpose timers 5x 32 b Timers
Security
PKC
ECC-256
SHA-512 RNG AES-256
Multi-Rate Timer
Windowed WDT
Debug auth.
PRINCE
RTC w anti tamper pins
Micro-Tick Timer
DICE + UUID
PFR
SRAM PUF
2x FlexPWM w 2 QDC module
OS Event Timer
2x Code WDG
OTP
Tamper detect
aaa-054528
Figure 1.MCXN23x system block diagram Table 1 lists the comparison of system
resources between the MCXNx4x and MCXN23x.
Table 1.Comparison of MCXNx4x and MCXN23x
MCU series
MCXNx4x
Part
MCXN947
MCXN946
Package
VFBGA184 HLQFP100
VFBGA184 HLQFP100
Temp range (junction)
-40 ºC to 125 -40 ºC to 125
ºC
ºC
MCXN547
VFBGA184 HLQFP100
-40 ºC to 125 ºC
MCXN546
VFBGA184 HLQFP100
-40 ºC to 125 ºC
MCXN23x
MCXN236
VFBGA184 HLQFP100
-40 ºC to 125 ºC
MCXN235
VFBGA184 HLQFP100
-40 ºC to 125 ºC
AN14179
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 6 May 2024
© 2024 NXP B.V. All rights reserved.
3 / 24
NXP Semiconductors
AN14179
Migration Guide from MCXNx4x to MCXN23x
Table 1.Comparison of MCXNx4x and MCXN23x…continued
MCU series
MCXNx4x
Part
MCXN947
MCXN946
MCXN547
Core #1 CortexM33
150 MHz TZM 150 MHz TZM 150 MHz TZM +FPU+ETM +FPU+ETM +FPU+ETM
Core #1 Cache 16 K
16 K
16 K
Core #2 CortexM33
150 MHz
150 MHz
150 MHz
PowerQuad (DSP Y
Y
Y
and Cordic)
NPU
Y
Y
Y
SmartDMA
Y
Y
Y
CoolFlux BSP32 Y
Y
–
Total flash
2 MB
1 MB
2 MB
Dual bank flash Y
Y
Y
Flash ECC and Y
Y
Y
CRC
Flash encrypt
Y
Y
Y
(Prince)
SRAM (ECC user 480 K configurable)
320 K
480 K
SRAM with ECC 32 K (in addition to main SRAM)
32 K
32 K
FlexSPI with 16 k cache
uSDHC
EMVSIM
1x, 2 ch
Y[1] Y[1]
1x, 2 ch
–
1x, 2 ch
Y Y
Secure key management
PUF/UDF
PUF/UDF
PUF/UDF
Secure subsystem Y
Y
Y
Anti-tamper pin[2] 8
8
8
Display controller 1
1
1
(FlexIO)
TSI
1[1]
N
1
DMIC
4 ch[1]
–
4 ch
SAI
4 ch
4 ch
4 ch
LP_FLEXCOMM 10
10
10
I3C
2
2
2
USB HS
1
–
1
USB FS
1
1
1
MCXN546 150 MHz TZM +FPU+ETM 16 K 150 MHz
Y
Y Y 1 MB Y Y
Y
320 K
32 K
1x, 2 ch
Y Y PUF/UDF
Y 8 1
1 4 ch 4 ch 10 2 1 1
MCXN23x MCXN236 150 MHz TZM +FPU+ETM 16 K –
–
Y 1 MB Y Y
Y
320 K
32 K
–
PUF/UDF
Y 6 1
4 ch 4 ch 8 2 1 –
MCXN235 150 MHz TZM +FPU+ETM 16 K –
–
Y 512 kB Y Y
Y
160 K
32 K
–
PUF/UDF
Y 6 1
4 ch 4 ch 8 2 1 –
AN14179
Application note
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Rev. 1 — 6 May 2024
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4 / 24
NXP Semiconductors
AN14179
Migration Guide from MCXNx4x to MCXN23x
Table 1.Comparison of MCXNx4x and MCXN23x…continued
MCU series
MCXNx4x
Part
MCXN947
MCXN946
MCXN547
10/100 Ethernet MAC
MII/RMII
MII/RMII
MII/RMII
FlexCAN (FD)
2
2
1
DAC 12b, 1 Msps 2
2
1
DAC 14b, 5 Msps 1
1
–
Comparator
3
3
2
Opamp
3
3
–
ADC
2
2
2
VREF
Y
Y
Y
FlexPWM
2
2
1
Quadrature
2
2
1
Decoder
SINC filter
Y
Y
–
RTC
1
1
1
32b timer
5
5
5
SCTimer
1
1
1
MRT 24b
1
1
1
uTick timer
1
1
1
WWDT
1
1
1
OS timer
1
1
1
MCXN546 MII/RMII
1 1 2 2 Y 1 1
1 5 1 1 1 1 1
MCXN23x MCXN236 –
2 2 2 Y 2 2
1 5 1 1 1 1
MCXN235 –
2 2 2 Y 2 2
1 5 1 1 1 1
[1] This feature is only supported on the MCXN947 VFBGA184 package. [2] The
100HLQFP supports two Anti-tamper pins.
The following section compares the MCXNx4x and MCXN23x in terms of memory,
clock, pinout, and peripherals.
2 Memory
This section provides details about flash memory and SRAM memory.
2.1 Flash memory
The MCXNx4x has a flash size of up to 2 MB, while the MCXN23x has a flash size of up to 1 MB, both support dual bank flash and dual image boot. The configuration of flash size for each part is listed in Table 2 and Table 3.
Table 2.MCXNx4x part list
Part Number
Embedded memory
Flash (MB) SRAM (kB)
(P)MCXN547VNLT
2
512
Features
Tamper pins GPIOs
(max)
(max)
2
74
Package
SRAM PUF Pin count
Type
Y
100
HLQFP
AN14179
Application note
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Rev. 1 — 6 May 2024
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AN14179
Migration Guide from MCXNx4x to MCXN23x
Table 2.MCXNx4x part list…continued
Part Number
Embedded memory
Flash (MB) SRAM (kB)
(P)MCXN546VNLT
1
352
(P)MCXN547VDFT
2
512
(P)MCXN546VDFT
1
352
(P)MCXN947VDFT
2
512
(P)MCXN947VNLT
2
512
(P)MCXN946VNLT
1
352
(P)MCXN946VDFT
1
352
Features
Tamper pins GPIOs
(max)
(max)
2
74
8
124
8
124
8
124
2
78
2
78
8
124
Package
SRAM PUF Pin count
Type
Y
100
HLQFP
Y
184
VFBGA
Y
184
VFBGA
Y
184
VFBGA
Y
100
HLQFP
Y
100
HLQFP
Y
184
VFBGA
Table 3.MCXN23x part list Part Number
(P)MCXN236VNLT (P)MCXN236VDFT (P)MCXN235VNLT (P)MCXN235VDFT
Embedded Memory Features
Flash (MB)
SRAM (kB) Tamper GPIOs pins (max) (max)
1
352
6
74
1
352
6
108
0.512
192
6
74
0.512
192
6
108
Package SRAM PUF Pin count Type
Y
100
HLQFP
Y
184
VFBGA
Y
100
HLQFP
Y
184
VFBGA
2.2 SRAM memory
The RAM size of the MCXNx4x is up to 512 kB, and the RAM size of the MCXN23x is up to 352 kB. The size of flash and RAM for each part of the MCXNx4x and MCXN23x is listed in Table 4.
Table 4.Flash and RAM size of different parts
Parts
MCXNx47
Flash
2M
SRAM (kB) Total size
512
SRAMX
96 (0x040000000x04017FFF)
SRAMA
32 (0x200000000x20007FFF)
SRAMB
32 (0x200080000x2000FFFF)
SRAMC
64 (0x200100000x2001FFFF)
SRAMD
64 (0x200200000x2002FFFFF)
SRAME
64 (0x200300000x2003FFFFF)
MCXNx46
1M
352
96 (0x040000000x04017FFF)
32 (0x200000000x20007FFF)
32 (0x200080000x2000FFFF)
64 (0x200100000x2001FFFF)
64 (0x200200000x2002FFFFF)
64 (0x200300000x2003FFFFF)
MCXN236
1M
352
96 (0x040000000x04017FFF)
32 (0x200000000x20007FFF)
32 (0x200080000x2000FFFF)
64 (0x200100000x2001FFFF)
64 (0x200200000x2002FFFFF)
64 (0x200300000x2003FFFFF)
MCXN235
512 kB
192
32 (0x040000000x04007FFF)
32 (0x200000000x20007FFF)
32 (0x200080000x2000FFFF)
64 (0x200100000x2001FFFF)
64 (0x200200000x2002FFFFF)
64 (0x200300000x2003FFFFF)
AN14179
Application note
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Rev. 1 — 6 May 2024
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6 / 24
NXP Semiconductors
AN14179
Migration Guide from MCXNx4x to MCXN23x
Table 4.Flash and RAM size of different parts…continued
Parts
MCXNx47
MCXNx46
SRAMF
64 (0x20040000-
–
0x2004FFFFF)
SRAMG
64 (0x20050000-
–
0x2005FFFFF)
SRAMH
32 (0x20060000-
–
0x20067FFF)
MCXN236 –
–
–
MCXN235 –
–
–
3 Clock system
The MCXN23x and MCXNx4x use almost the same clock system, with a few differences.
3.1 FRG
A Fractional Rate Generator (FRG) is added to the MCXN23x to generate a more
accurate clock for the CLKOUT divider. The FRG output is used as the input of
the CLKOUT divider, see Figure 2. It can be used to obtain more precise baud
rates when the function clock is not a multiple of standard baud rates. This
can be primarily used to create a base baud rate clock for USART functions,
and can be used for other purposes, such as metering applications.
main_clk
000
pll0_clk
001
clk_in
010
fro_hf
011
fro_12m
100
pll1_clk0
101
lp _osc
110
usb_pll_clk
111
FRG
100 MHz CLKOUT CLKOUT clock divider
CLKOUTDIV[7:0]
CLKOUT select CLKOUTSEL[2:0] Figure 2.MCXN23x CLKOUT diagram For the CLKOUT diagram of the MCXNx4x, see Figure 3.
aaa- 054535
main_clk pll0_clk clk_in
fro_hf fro_12m pll1_clk0
lp _osc usb_pll_clk
000
001
010
100 MHz
011
CLKOUT CLKOUT
100
clock divider
101
110
111 CLKOUTDIV[7:0]
CLKOUT select CLKOUTSEL[2:0]
aaa-054536
Figure 3.MCXNx4x CLKOUT diagram
The CLKOUT_FRGCTRL register has been added to the SYSCON module of MCXN23x and used to configure numerator and denominator values.
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NXP Semiconductors
AN14179
Migration Guide from MCXNx4x to MCXN23x
3.2 UTICK
The clock sources of UTICK (Micro-Tick) on the MCNX23x have been expanded from
1 to 3, and xtal32k[2] and clk_in have been added as clock sources of UTICK.
The clock source of UTICK on the MCXN23x is shown in Figure 4.
clk_in
00
xtal32k[2]
01
clk_1m
10
None
11
UTICK divider
1 MHz To UTICK
UTICKCLKSEL[2:0]
aaa – 05 4 5 37
Figure 4.MCXN23x UTICK clock source
In the metering application, UTICK is used to measure power line frequency. To support metering applications, clk_in and xtal32k[2] are added to the MCXN23x for high-accuracy clock source.
3.3 I3C
The clock diagram of I3C on the MCXN23x is shown in Figure 5.
1× instance per I3C
0 pll0_clk
0 fro_hf
clk_1m pll1_clk0
usb_pll_clk None
000
001
010
011
I3C FCLK
100
divider
101
110
111 I3CnFCLKDIV[7:0]
I3CnFCLKSEL[2:0]
CG I3Cn FCLK gate
CG I3Cn tc_slow_gate
CG I3Cn slow_gate
25 MHz To I3Cn FCLK
25 MHz To I3Cn CLK _SLOW_TC
25 MHz To I3Cn CLK _SLOW
aaa-054538
Figure 5.MCXN23x I3C clock diagram
Add clk_1m as the clock source to the I3C_FCLK divider, and keep CLK_SLOW and CLK_SLOW_TC synchronized with FCLK.
The I3C clock diagram of MCXNx4x is shown in Figure 6.
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Rev. 1 — 6 May 2024
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AN14179
Migration Guide from MCXNx4x to MCXN23x
1× instance per I3C
0
000
pll0_clk
001
clk_in
010
fro_hf
011
0
100
pll1_clk0
101
usb_pll_clk
110
None
111
I3C FCLK divider
I3CnFCLKDIV[7:0]
25 MHz
To I3C0/1 FCLK
I3CnFCLKSEL[2:0]
0
clk_1m
1
25 MHz
I3C FCLK_STC divider
To I3C0/1 CLK _SLOW_TC
I3CnFCLKSTCDIV[7:0] I3CnFCLKSTCSEL[2:0]
clk_1m
I3C slow clock divider
1 MHz
To I3C0/1 CLK_SLOW
Figure 6.MCXNx4x I3C clock diagram
I3CnFCLKSDIV[7:0]
aaa-054539
4 Pinout
This section compares the pinout differences between MCXNx4x and MCXN23x, including 184VFBGA and 100HLQFP packages.
4.1 184VFBGA
For the 184VFBGA package, the MCXN23x is pin-to-pin compatible with the
MCXNx4x. However, there are some differences between the two. In MCXN23x, 28
pins are removed, including 18 GPIO pins, eight analog pins, and two USB pins.
The pinout of the MCXN23x 184VFBGA package is illustrated in Figure 7.
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Rev. 1 — 6 May 2024
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NXP Semiconductors
AN14179
Migration Guide from MCXNx4x to MCXN23x
1
2
A P1_8 P1_7
3
4
P1_4
5
6
P0_25
7
8
P0_ 21
9
10
P0_17
11
12
NC
13
14
P0_5
15
16
17
P0_1 P0_0
B P1_9 P1_6 P1_5 P1_3
P0_24 P0_23 P0_22
P0_16 NC
NC
P0_4 P0_3 P0_2 P3_0
C
P1_10 P1_2 P1_1 P1_0
P0_20 P0_19 P0_18
NC P0_7 P0_6 P3_1
D P1_13 P1_12 P1_11 P1_14
VSS NC
VSS
NC VSS
P3_7 P3_2 NC P3_6
E
P1_15 VSS
NC P0_28
P0_27 P0_14
VSS P3_8
F
P1_30 P1_31
RESE T_B
P1_17
P1_16
P0_29
P0_26
NC
NC P3_9 P3_11 P3_10
G
VSS
P1_18 P1_19
VDD
VDD_ P3
P0_15 NC
P3_12
H P2_1 P2_0 P2_2
VSS VDD
VDD
VSS VDD_ P3
VDD_ VSS P3
P3_15 P3_13 P3_14
J
P2_3 VSS
VSS
VSS
VSS P3_16
K P2_5 P2_6 P2_4
L
P2_7
NC
VDDL NC DO
CORE
VDD_ P2
VSS
VDD_ CORE
P5_5 P5_6
NC
VDD_
P2
VDD_ CORE
P5_7
P3_17 P3_18 NC
NC
P3_ 21
M P2_9 P2_8 P2_10 NC
P4_4
P4_5
P5_2
P5_4
NC P3_23 P3_22 P3_20
N P P4_0 P4_1 R
P2_11
VDD_ P4
P4_6 P4_14
P4_18 P5_3
VSS
VDD_ SYS
NC
VDD_ P4
VSS VSS
P4
P4
VSS_ P4
USB1_ ID
VSS
VSS
VDD LDO SYS
VSS DCDC DCDC LX
NC
VDD_ VREF VREF
ANA
H
L
P4_16 P4_17 P4_19
VDD USB1 USB1 VDD USB DP DM DCDC
T P4_2 NC
NC P4_7
P4_12 P4_13 P4_15
P4_20 P4_21 P4_22
NC
NC
VSS
VDD_ BAT
U P4_3 NC
ANA_7
NC
NC
NC
P4_23
USB1_ VBUS
P5_0 P5_1
aaa – 05 4 5 4 0
Figure 7.MCXN23x 184VFBGA pinout
In Figure 7, the removed pins are labeled “NC” and are highlighted in yellow.
The removed pins on the MCXN23x 184VFBGA are as follows:
· GPIO pins: P0_8 P0_9 P0_10 P0_11 P0_12 P0_13 P0_30 P0_31 P1_20 P1_21 P1_22 P1_23
AN14179
Application note
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Rev. 1 — 6 May 2024
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AN14179
Migration Guide from MCXNx4x to MCXN23x
P3_3 P3_4 P3_5 P3_19 P5_8 P5_9 · Analog pins: ANA_0 ANA_1
ANA_4 ANA_5 ANA_6 ANA_14 ANA_18 ANA_22 · USB pins: USB0_DM
USB0_DP
The pinout of the MCXNx4x 184VFBGA package is shown in Figure 8.
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Migration Guide from MCXNx4x to MCXN23x
1
2
A P1_8 P1_7
3
4
P1_4
5
6
P0_25
7
8
P0_ 21
9
10
P0_17
11
12
P0_9
13
14
P0_5
15
16
17
P0_1 P0_0
B P1_9 P1_6 P1_5 P1_3
P0_24 P0_23 P0_22
P0_16 P0_11 P0_10
P0_4 P0_3 P0_2 P3_0
C
P1_10 P1_2 P1_1 P1_0
P0_20 P0_19 P0_18
P0_8 P0_7 P0_6 P3_1
D P1_13 P1_12 P1_11 P1_14
VSS P0_31
VSS
P0_12 VSS
P3_7 P3_2 P3_3 P3_6
E
P1_15 VSS
P0_30 P0_28
P0_27 P0_14
VSS P3_8
F
P1_30 P1_31
RESE T_B
P1_17
P1_16
P0_29
P0_26
P0_13
P3_4 P3_9 P3_11 P3_10
G
VSS
P1_18 P1_19
VDD
VDD_ P3
P0_15 P3_5
P3_12
H P2_1 P2_0 P2_2
VSS VDD
VDD
VSS VDD_ P3
VDD_ VSS P3
P3_15 P3_13 P3_14
J
P2_3 VSS
VSS
VSS
VSS P3_16
K P2_5 P2_6 P2_4
VDD_L P120 DO
CORE
VDD_ P2
VSS
VDD_ CORE
P5_5 P5_6
P3_17 P3_18 P3_19
L
P2_7
P1_22 P1_21
VDD_
P2
VDD_ CORE
P5_7 P5_8
P3_ 21
M P2_9 P2_8 P2_10 P1_23
P4_4
P4_5
P5_2
P5_4
P5_9 P3_23 P3_22 P3_20
N
P2_11
VDD_ P4
P4_6 P4_14
P4_18 P5_3
VSS
VDD_ SYS
P
P4_0
P4_1
ANA_0
VDD_ P4
VSS VSS
P4
P4
VSS_ P4
USB1_ ID
VSS
VSS
VDD LDO SYS
VSS DCDC DCDC LX
R
AN A _1
VDD_ ANA
VREF H
VREF L
P4_16 P4_17 P4_19
VDD USB1 USB1 VDD USB DP DM DCDC
T P4_2 ANA_4 ANA_5 P4_7
P4_12 P4_13 P4_15
P4_20 P4_21 P4_22
USB0 USB0 DM DP
VSS
VDD_ BAT
U P4_3 ANA_6
ANA_7
AN A _1 4
ANA _1 8
ANA_ 22
P4_23
USB1_ VBUS
P5_0 P5_1 aaa_054541
Figure 8.MCXNx4x 184VFBGA pinout
4.2 100HLQFP
For the 100HLQFP package, MCXN23x is almost pin-to-pin compatible with
MCXN54x. The only difference is the USB pin. The MCXN54x supports full-speed
USB (USB0) and high-speed USB (USB1), but the MCXN23x only supports USB1, so
the MCXN23x does not have USB0_DM and USB0_DP pins. The pinout of the MCXN23x
100HLQFP package is as shown in Figure 9.
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Migration Guide from MCXNx4x to MCXN23x
P1_ 8
1
P1_9
2
P1_10
3
P1_11
4
P1_12
5
P1_13
6
P1_14
7
P1_15
8
RESET_b 9
P1_30
10
P1_ 31
11
VDD_CORE 12
VDD
13
P2_0
14
P2_1
15
P2_2
16
P2_3
17
P2_4
18
P2_5
19
P2_6
20
P2_7
21
P4_0
22
P4_1
23
P4_ 2
24
P4_3
25
P1_7 100
P1_6 99
P1_5 98
P1_4 97
VDD 96
P1_3 95
P1_2 94
P1_1 93
P1_0 92
P0_23 P0_22 P0_21 P0_20 P0_19 P0_18
91
90
89
88
87
86
P0_17 P0_16
85
84
VDO 83
P0_6 82
P0_5 81
P0_4 80
P0_3 79
P0_2 78
P0_1 77
P0_0 76
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
P4_4
P4_5
P4_6
P4_7
V DD_ A NA
VREFH
VREFL VSS_P4 VDD_P4
P4_12
P4_13
P4_15
P4_16
P4_17
USB1 USB1
DP
DM
USB1_ VBUS
VSS_ USB
VDD_ USB
NC
46
47
48
49
50
NC
VDD_ BAT
P5_0
P5_1
P5_2
75
P3_0
74
P3 _1
73 VDD_P3
72
P3_6
71
P3_7
70
P3_8
69
P3_9
68
P3 _10
67
P3_11
66 VDD_P3
65
P3 _12
64
P3_13
63
P3 _14
62
P3 _15
61
P3 _16
60
P3_17
59 VDD_P3
58 VDD_CORE
57
P3_ 20
56
P3_ 21
55 VDD_SYS
54 VDD_DCD
53 DCDC_LX
52 VSS_DCDC
51
P5_3
aaa-05 4542
Figure 9.MCXN23x 100HLQFP pinout
The pinout of the MCXN54x and MCXN94x 100HLQFP package is shown in Figure 10.
N54x
N94x
P1_ 8
P1_8
1
P1_9
P1_9
2
P1_10
P1_10
3
P1_11
P1_11
4
P1_12
P1_12
5
P1_13
P1_13
6
P1_14
P1_14
7
P1_15
P1_15
8
RESET_b RESET_b 9
P1_30
P1_30
10
P1_ 31
P1_31
11
VDD_COREVDD_CORE 12
VDD
VDD
13
P2_0
P2_0
14
P2_1
P2_1
15
P2_2
P2_2
16
P2_3
P2_3
17
P2_4
P2_4
18
P2_5
P2_5
19
P2_6
P2_6
20
P2_7
P2_7
21
P4_0
P4_0
22
P4_1
P4_1
23
P4_ 2
P4_2
24
P4_3
P4_3
25
N54x
N94x
P1_7 P1_7 100
P1_6 P1_6
99
P1_5 P1_5
98
P1_4 P1_4
97
VDD VDD
96
P1_3 P1_3
95
P1 2 P1 2
94
P1_1 P1_1
93
P1_0 P1_0
92
P0_23 P0_22 P0_21 P0_20 P0_19 P0_18 P0_17
P0_23 P0_22 P0_21 P0_20 P0_19 P0_18 P0_17
91
90
89
88
87
86
85
P0_16 P0_16
84
VDD VDD
83
P0_6 P0_6
82
P0_5 P0_5
81
P0_4 P0_4
80
P0_3 P0_3
79
P0_2 P0_2
78
P0_1 P0_1
77
P0_0 P0_0
76
26 P4_4 P4_4
27 P4_5 P4_5
28 P4_6 P4_6
29 P4_7 P4_7
30
31
32
33
34
35
VDD_A NA
VREFH
VREFL VSS_P4 VDD_P4
P4_12
VDD_A NA
VREFH
VREFL VSS_P4 VDD_P4
P4_12
36 P4_13 P4_13
37 P4_15 P4_15
38 P4_16 P4_16
39
40
41
42
43
P4_17 P4_19 P4_20 P4_21 P4_23
P4_17
USB1_ DP
USB1_ DS
USB1_ VBUS
VSS_ USB
44
VDD USB VDD USB
45
46
USB0 DM
USB0 DM
USB0 DP
USB0 DP
47
VDD BAT VDD BAT
48 P5_0 P5_0
49 P5_1 P5_1
50 P5 _2 P5 _2
N94x
N54x
75
P3_0
P3_0
74
P3_1
P3_1
73 VDD_P3 VDD_P3
72
P3_6
P3_6
71
P3_7
P3_7
70
P3_8
P3_8
69
P3_9
P3_9
68
P3_10
P3_10
67
P3_11
P3_11
66 VDD_P3 VDD_P3
65
P3_12
P3 _12
64
P3_13
P3 _13
63
P3_14
P3 _14
62
P3_15
P3 _15
61
P3_16
P3_16
60
P3_17
P3 _17
59 VDD_P3 VDD_P3
58 VDD_CORE VDD_CORE
57
P3_20
P3_ 20
56
P3 _21
P3_ 21
55 VDD_SYS VDD_SYS
54 VDD_DCDC VDD_DCDC
53 DCDC_LX DCDC_LX
52 VSS_DCDC VSS_DCDC
51
P5 _3
P5_3
N94x
N54x aaa-05 4529
Figure 10.MCXN94x and MCXN54x 100HLQFP pinout
MCXN94x has six pins P4_19, P4_20, P4_21, P4_23, USB0_DM, and USB0_DP.
However, MCXN23x does not have these six pins but instead has four different
pins USB1_DP, USB1_DM, USB1_VBUS, and VSS_USB.
For more detailed information about the pinouts, refer to the pinout table in
the attachments of MCX Nx4x Reference Manual (document MCXNX4XRM) and MCXN23x
Reference Manual (document MCXN23XRM).
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Migration Guide from MCXNx4x to MCXN23x
5 Peripherals
In Table 1, we have compared the differences between MCNX23x and MCXNx4x. The MCXN23x does not have various modules such as FlexSPI, PowerQuad, NPU, CoolFlux BSP32, uSDHC, EMVSIM, TSI, USB FS, Ethernet, 12-bit DAC, 14-bit DAC, Opamp, SINC Filter, and SCTimer. The following section describes the differences between the common peripherals between the MCXN23x and MCXNx4x.
5.1 GPIO
As described in Section 4.1, the MCXNx4x supports up to 124 GPIOs, and the
MCXN23x supports up to 106 GPIOs. However, in the case of MCXN23x, 18 GPIO
pins are not supported. Apart from being used as GPIOs, these 16 pins also
support the functions listed in Table 5.
Table 5.Removed GPIOs on the MCXN23x 184VFBGA package
184BGA ALL
184BGA ALL Pin Name
Analog
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
K5
P1_20
ADC1_A20/ P1_20 TRIG_IN2
FC5_P4
FC4_P0
CT3MAT2 SCT0
CMP1_IN3
OUT8
L5
P1_21
ADC1_A21/ P1_21 TRIG_OUT2 FC5_P5
FC4_P1
CT3MAT3 SCT0
CMP2_IN3
OUT9
L4
P1_22
ADC1_A22 P1_22 TRIG_IN3
FC5_P6
FC4_P2
CTINP14 SCT0
OUT4
M4
P1_23
ADC1_A23 P1_23 –
–
FC4_P3
CTINP15 SCT0
OUT5
L14
P5_8
ADC1_B16 P5_8
TRIG_OUT7 –
TAMPER6 –
–
M14
P5_9
ADC1_B17 P5_9
–
TAMPER7 –
–
K17
P3_19
–
P3_19 –
FC7_P6
–
CT2_MAT1 PWM1_X1
G14
P3_5
–
P3_5
–
FC7_P3
–
CT_INP19 PWM0_X3
F14
P3_4
–
P3_4
–
FC7_P2
–
CT_INP18 PWM0_X2
D16
P3_3
–
P3_3
–
FC7_P1
–
CT4_MAT1 PWM0_X1
C12
P0_8
ADC0_B8 P0_8
–
FC0_P4
–
CT_INP0 –
A12
P0_9
ADC0_B9 P0_9
–
FC0_P5
–
CT_INP1 –
B12
P0_10
ADC0_B10 P0_10 –
FC0_P6
–
CT0_MAT0 –
B11
P0_11
ADC0_B11 P0_11 –
–
–
CT0_MAT1 –
D11
P0_12
ADC0_B12 P0_12 –
FC1_P4
FC0_P0
CT0_MAT2 –
F12
P0_13
ADC0_B13 P0_13 –
FC1_P5
FC0_P1
CT0_MAT3 –
E7
P0_30
ADC0_B22 P0_30 –
D7
P0_31
ADC0_B23 P0_31 –
FC1_P6 –
FC0_P6 –
CT_INP2 CT_INP3 –
ALT6
FLEXIO0 D28
FLEXIO0 D29
FLEXIO0 D30
FLEXIO0 D31
–
–
FLEXIO0 D27
FLEXIO0 D13
FLEXIO0 D12
FLEXIO0 D11
FLEXIO0 D0
FLEXIO0 D1
FLEXIO0 D2
FLEXIO0 D3
FLEXIO0 D4
FLEXIO0 D5
–
–
ALT7
ALT10
SmartDMA_ PIO16
SmartDMA SAI1
PIO17
MCLK
SmartDMA_ PIO18
SmartDMA_ PIO19
–
–
–
–
SmartDMA_ SAI1RX
PIO19
FS
SmartDMA_ PIO5
SmartDMA_ PIO4
SmartDMA_ PIO3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ALT11
CAN1_TXD CAN1_RXD –
Table 5 lists the specific pins, including LP_FLEXCOMM0/1/4/5/7, TRIG, CTimer, FlexPWM, FlexIO, SmartDMA, and SAI1 are involved. However, the other pins on the MCX23x can also implement the same functions as these pins. Before migrating from the MCXNx4x to MCXN23x, it is important to check if your design on the MCXNx4x uses these pins. If it does, you must reassign the pins to meet your requirements.
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5.2 USB
All the MCXN54x parts and the MCXN94x 184VFBGA packages support FS USB (USB0)
and HS USB (USB1). Whereas the MCXN94x 100HLQFP package only supports HS USB.
All the MCXN23x parts only support HS USB.
5.3 DMIC
All parts of the MCXN23x and MCXN54x have a DMIC module and support up to four
digital microphone channels. However, for the MCXN94x series, the MCXN946 does
not support the DMIC module, and the MCXN947 only supports the DMIC module on
the 184VFBGA package.
5.4 LP_FLEXCOMM
The MCXNx4x series supports 10 LP_FLEXCOMM modules. Each LP_FLEXCOMM can be
configured as UART, I2C, and SPI. Among them, the IO of LP_FLEXCOMM6/7/8/9 is
high-speed IO, and the highest clock that can be configured is 150 MHz. The
MCXN23x only supports eight LP_FLEXCOMM modules and does not support
LP_FLEXCOMM8 and LP_FLEXCOMM9, only LP_FLEXCOMM6 and LP_FLEXCOMM7 can use
high-speed IOs.
5.5 Comparator
The MCXN94x series supports three Comparator (CMP) modules, while the MCXN54x
and MCXN23x series only support two CMP modules.
5.6 ADC
The MCXNx4x and MCXN23x series have two 16-bit ADC modules but differ in the number of ADC channels they support. The MCXNx4x can support up to 75 ADC channels, while the MCXN23x can support up to 63 ADC channels. For the 184VFBGA package, the MCXN23x cannot support the 12 ADC channels listed in Table 6 because the 16 pins mentioned in Table 6 are removed.
Table 6.Removed ADC channels on MCXN23x
184BGA ALL Pin Name
Analog
P1_20
ADC1_A20/CMP1_IN3
P1_21
ADC1_A21/CMP2_IN3
P1_22
ADC1_A22
P1_23
ADC1_A23
P5_8
ADC1_B16
P5_9
ADC1_B17
P3_19
–
P3_5
–
P3_4
–
P3_3
–
P0_8
ADC0_B8
P0_9
ADC0_B9
P0_10
ADC0_B10
P0_11
ADC0_B11
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Table 6.Removed ADC channels on MCXN23x…continued
184BGA ALL Pin Name
Analog
P0_12
ADC0_B12
P0_13
ADC0_B13
P0_30
ADC0_B22
P0_31
ADC0_B23
Note: The term ADC channels refer to the external ADC input channels.
5.7 FlexPWM and Quadrature Decoder (QDC)
The MCXN94x and MCXN23x are compatible with dual-motor applications as they
support two FlexPWM modules and two QDC modules. But, the MCXN54x supports
only one FlexPWM module and one QDC module, making it suitable for single-
motor solutions only.
5.8 DMA
The MCXNx4X has two eDMA modules, eDMA0 and eDMA1. Each module supports 16 DMA
channels. The MCXN23x also has 2 eDMA modules, but eDMA1 only supports eight
channels.
5.9 Anti-tamper pin
The tamper pins for MCXNx4x are listed in Table 7 and Table 8. The MCXNx4x has
eight tamper pins, and the MCXN23x has six tamper pins. Pin P5_8 and P5_9 are
removed on MCXN23x.
Note: The 100HLQFP packaged parts of MCXN4x and MCXN23x only support two
tamper pins.
Table 7.Tamper pins on MCXNx4x
184BGA all 184VFBGA 100HLQFP pin name N94x
M10
P5_2
50
N11
P5_3
51
M12
P5_4
–
K12
P5_5
–
K13
P5_6
–
L13
P5_7
–
L14
P5_8
–
M14
P5_9
–
100HLQFP N94x pin name P5_2 P5_3 –
100HLQFP N54x
50 51 –
100HLQFP N54x pin name P5_2 P5_3 –
ALT0 ALT3
P5_2 P5_3 P5_4 P5_5 P5_6 P5_7 P5_8 P5_9
TAMPER0 TAMPER1 TAMPER2 TAMPER3 TAMPER4 TAMPER5 TAMPER6 TAMPER7
Table 8.Tamper pins on MCXN23x
184BGA ball
184VFBGA pin name
M10
P5_2
N11
P5_3
M12
P5_4
AN14179
Application note
100HLQFP
50 51 –
100HLQFP pin name P5_2
P5_3
–
ALT0
P5_2 P5_3 P5_4
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Rev. 1 — 6 May 2024
ALT3
TAMPER0 TAMPER1 TAMPER2
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Migration Guide from MCXNx4x to MCXN23x
Table 8.Tamper pins on MCXN23x…continued
184BGA ball
184VFBGA pin name
100HLQFP
K12
P5_5
–
K13
P5_6
–
L13
P5_7
–
100HLQFP pin name –
–
–
ALT0
P5_5 P5_6 P5_7
ALT3
TAMPER3 TAMPER4 TAMPER5
6 Miscellaneous
This section provides details about the boot source and debugging.
6.1 Boot source
The MCXN23x does not have the FlexSPI module and does not support external
flash boot, but the MCXNx4x supports external flash boot, which can be
configured with the BOOT_CFG field in the Customer Manufacturing/ Factory
Configuration Area (CMPA) to implement this function.
6.2 Debug
The MCXNx4x debug module supports ITM, DWT, ETM, ETB W/2KB RAM, and TPIU
function, but the ETM and ETB W/2KB functions are removed on the MCXN23x.
6.3 Power management
Power management The power management of MCXN23x and MCXNx4x is identical, so
they can use the same power supply circuit.
7 Software
This chapter describes some software considerations when porting the code from
the MCXNx4x platform to the MCXN23x platform. In this section, take the
hello_world project from the FRDM-MCXN236 SDK as an example, and the IDE is
IAR 9.40.1.
7.1 Chip-specified header files
Each SDK project has a device directory containing chip-specific header files.
These header files must be replaced when porting code between platforms, see
Figure 11.
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Figure 11.Chip-specified header files
7.2 SDK driver
Ensure that the SDK driver directory does not include unsupported modules such
as FlexSPI and uSDHC for MCXN23x.
7.3 Start_up file
Replace the start_up file of MCXNx4x with MCXN23x start_up file, as some
modules are removed, and the interrupt vector table is different.
7.4 Linker file
The MCXN23x and MCXNx4x can have different Flash and RAM sizes, so the
customer must replace the linker file to ensure the Flash and RAM range used
in the linker file is suitable.
7.5 IDE-related configuration update
When porting code from the MCXNx4x to MCXN23x, update IDE-related
configurations such as path and macro definition, see Figure 12.
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Figure 12.Path and macro definition Note: If the customer does not use the removed pins and peripherals on the MCXN23x, then the customer can directly solder the MCXN23x chip to the MCXNx4x board and can directly use the MCXNx4x software, but the linker file must be updated to match the flash and RAM size of MCXN23x. Currently, this method has only been verified on IAR IDE.
8 Conclusion
This document compares system resources and software differences between the MCXNx4x and MCXN23x, making project migration quick and easy.
9 Related documentation/resources
Table 9 lists additional documents and resources that can be referred to for more information. Some of the documents listed below may be available only under a non-disclosure agreement (NDA). To request access to these documents, contact local field applications engineer (FAE) or sales representative.
Table 9.Related documentation/resources Document MCX Nx4x Reference Manual
(document MCXNX4XRM)
MCXN23x Reference Manual (document MCXN23XRM) (document MCXN23XRM)
Link/how to access MCXNX4XRM MCXN23XRM
10 Acronyms and abbreviations
Table 10 defines the acronyms and abbreviations used in this document.
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Table 10.Acronyms and abbreviations
Acronym
Definition
ADC
Analog-to-Digital Converter
CAN
Controller Area Network
CMP
Comparator
CMPA
Customer Manufacturing/Factory Configuration Area
CPU
Central Processing Unit
CRC
Cyclic Redundancy Check
DAC
Digital-to-Analog Converter
DMA
Direct Memory Access
DSP
Digital Signal Processor
DWT
Drop-Weight Tear
ECC
Error Correcting Code
eDMA
Enhanced Direct Memory Access
ETM
Embedded Trace Macrocell
ETB
Embedded Trace Buffer
FlexCAN
Flexible Controller Area Network Interface
FlexIO
Flexible Input/Output
GPIO
General-Purpose Input/Output
HS USB
High-Speed USB
I2C
Inter-Integrated Circuit
ITM
Instrumentation Trace Macrocell
IP
Internet Protocol
LDO
Liquid Crystal Display
LPC
Low Pin Count
MAC
Media Access Control
MCU
Microcontroller Unit
MII
Media-Independent Interface
NDA
Non-Disclosure Agreement
OS
Operating System
QDC
Quadrature Decoder
RTC
Real-Time Clock
TPIU
Trace Port Interface Unit
TSI
Touch System Interface
SAI
Serial Audio Interface
SDK
Software Development Kit
SPI
Serial Peripheral Interface
SRAM
Static Random-Access Memory
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Migration Guide from MCXNx4x to MCXN23x
Table 10.Acronyms and abbreviations…continued
Acronym
Definition
RAM
Random-Access Memory
RMII
Reduced Media Independent Interface
TPIU
Trace Port Interface Unit
UART
Universal Asynchronous Receiver Transmitter
USB
Universal Serial Bus
VREF
Voltage Reference
11 Note about the source code in the document
Example code shown in this document has the following copyright and
BSD-3-Clause license:
Copyright 2024 NXP Redistribution and use in source and binary forms, with or
without modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials must be provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS”
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 Revision history
Table 11 summarizes the revisions to this document.
Table 11.Revision history
Document ID
Release date
AN14179 v.1.0
06 May 2024
Description Initial public version
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Legal information
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Notwithstanding any damages that customer might incur for any reason
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NXP B.V. — NXP B.V. is not an operating company and it does not distribute or
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Trademarks
Notice: All referenced brands, product names, service names, and trademarks
are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
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AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink,
CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed
Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK,
ULINK2, ULINK-ME, ULINKPLUS, ULINKpro, Vision, Versatile — are trademarks
and/or registered trademarks of Arm Limited (or its subsidiaries or
affiliates) in the US and/or elsewhere. The related technology may be
protected by any or all of patents, copyrights, designs and trade secrets. All
rights reserved.
Bluetooth — the Bluetooth wordmark and logos are registered trademarks owned
by Bluetooth SIG, Inc. and any use of such marks by NXP Semiconductors is
under license.
CoolFlux — is a trademark of NXP B.V. CoolFlux DSP — is a trademark of NXP
B.V. EdgeLock — is a trademark of NXP B.V. IAR — is a trademark of IAR Systems
AB. Kinetis — is a trademark of NXP B.V. Matter, Zigbee — are developed by the
Connectivity Standards Alliance. The Alliance’s Brands and all goodwill
associated therewith, are the exclusive property of the Alliance.
MCX — is a trademark of NXP B.V.
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Contents
1
Introduction ……………………………………………… 2
2
Memory ……………………………………………………. 5
2.1
Flash memory …………………………………………….5
2.2
SRAM memory ………………………………………….. 6
3
Clock system …………………………………………… 7
3.1
FRG …………………………………………………………. 7
3.2
UTICK ………………………………………………………. 8
3.3
I3C …………………………………………………………… 8
4
Pinout ……………………………………………………….9
4.1
184VFBGA …………………………………………………9
4.2
100HLQFP ………………………………………………. 12
5
Peripherals …………………………………………….. 14
5.1
GPIO ………………………………………………………. 14
5.2
USB …………………………………………………………15
5.3
DMIC ……………………………………………………….15
5.4
LP_FLEXCOMM ………………………………………. 15
5.5
Comparator ……………………………………………… 15
5.6
ADC ……………………………………………………….. 15
5.7
FlexPWM and Quadrature Decoder (QDC) ….. 16
5.8
DMA ……………………………………………………….. 16
5.9
Anti-tamper pin ………………………………………… 16
6
Miscellaneous ………………………………………… 17
6.1
Boot source …………………………………………….. 17
6.2
Debug …………………………………………………….. 17
6.3
Power management …………………………………..17
7
Software ………………………………………………….17
7.1
Chip-specified header files ………………………… 17
7.2
SDK driver ………………………………………………. 18
7.3
Start_up file …………………………………………….. 18
7.4
Linker file ………………………………………………… 18
7.5
IDE-related configuration update ………………… 18
8
Conclusion …………………………………………….. 19
9
Related documentation/resources …………… 19
10
Acronyms and abbreviations ………………….. 19
11
Note about the source code in the
document ………………………………………………..21
12
Revision history ………………………………………21
Legal information …………………………………….22
AN14179
Migration Guide from MCXNx4x to MCXN23x
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.
© 2024 NXP B.V.
For more information, please visit: https://www.nxp.com
All rights reserved.
Date of release: 6 May 2024 Document identifier: AN14179
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