NXP UM11900 Computer to ETPL Dongle User Manual

October 30, 2023
NXP

UM11900
Hardware user manual for KIT-PC2TPLEVB
Rev. 1 — 20 April 2023
User manual

Document information

Information Content
Keywords MC33665A, TPL, KIT-PC2TPLEVB, evaluation, tool
Abstract User manual for KIT-PC2TPLEVB.

Revision history

Rev Date Description
v.1 20230420 Initial version

Important notice

IMPORTANT NOTICE
For engineering development or evaluation purposes only
**** NXP provides the product under the following conditions:
This evaluation kit is for use of ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY. It is provided as a sample IC pre-soldered to a printed-circuit board to make it easier to access inputs, outputs and supply terminals. This evaluation board may be used with any development system or other source of I/O signals by connecting it to the host MCU computer board via off-theshelf cables. This evaluation board is not a Reference Design and is not intended to represent a final design recommendation for any particular application. Final device in an application heavily depends on proper printed-circuit board layout and heat sinking design as well as attention to supply filtering, transient suppression, and I/O signal quality.
The product provided may not be complete in terms of required design, marketing, and or manufacturing related protective considerations, including product safety measures typically found in the end device incorporating the product. Due to the open construction of the product, it is the responsibility of the user to take all appropriate precautions for electric discharge. In order to minimize risks associated with the customers’ applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. For any safety concerns, contact NXP sales and technical support services.

Introduction

The NXP analog product development boards provide an easy-to-use platform for evaluating NXP products.
The boards support a range of analog, mixed-signal, and power solutions. They incorporate monolithic integrated circuits and system-in-package devices that use proven high-volume technology. NXP products offer longer battery life, a smaller form factor, reduced component counts, lower cost, and improved performance in powering state-of-the-art systems.

Finding kit resources and information on the NXP web site

NXP Semiconductors provides online resources for this evaluation board and its supported device(s) on http://www.nxp.com.
The information page for the KIT-PC2TPLEVB evaluation board is at http://www.nxp.com/KITPC2TPLEVB.
The information page provides overview information, documentation, software and tools, parametric, ordering information and a Getting Started tab. The Getting Started tab provides quick-reference information applicable to using the KIT-PC2TPLEVB evaluation board, including the downloadable assets referenced in this document.

Getting ready

The purpose of the KIT-PC2TPLEVB is to interface NXP PC software (that is, Device Evaluation GUI) to TPL attached NXP devices (that is, MC33775A).
This document guides the user through the process of using the KIT-PC2TPLEVB.
4.1 Kit contents
The KIT-PC2TPLEVB kit includes:

  • KIT-PC2TPLEVB – personal computer (PC) to electrical transport protocol link (ETPL) gateway board
  • TTL-232R-5V – USB to RS232 cable (1.8 m)
  • ETPL cable – two-wire twisted pair TPL cable (50 cm)
  • Quick start guide

Getting to know the hardware

5.1 Kit overview
Figure 1 an overview of the KIT-PC2TPLEVB.

NXP UM11900 Computer to ETPL Dongle - hardware

5.2 Board features
The main features of the KIT-PC2TPLEVB are:

  • Direct control from a PC via USB connection (VCP)
  • VCP communication speed 2 MBd
  • Supply of the KIT-PC2TPLEVB from USB
  • Two galvanically isolated ETPL ports
  • Supports TPL3 and TPL2 protocol versions
  • Four status LEDs

The KIT-PC2TPLEVB serves as a hardware tool supporting evaluation of ETPL devices with software running on a PC. This board can be directly connected to a USB port of a PC and interfaced via a virtual COM port (VCP).

NXP UM11900 Computer to ETPL Dongle - hardware1

5.3 Block diagram

NXP UM11900 Computer to ETPL Dongle - diagram

5.4 Kit featured components
The KIT-PC2TPLEVB allows the user to interface ETPL chains/devices with software running on a PC.
The kit includes a UART-to-USB translator cable (TTL-232R-5V) and an ETPL cable. The UART-to-USB translator cable interfaces with the UART-based MC33665A gateway and provides the 5 V supply. The two ETPL ports allow connection to NXP evaluation boards or customer boards having the NXP ETPL interface.
The KIT-PC2TPLEVB has the following LEDs to indicate information to the user. The D13 indicates the operating mode (active) of the MC33665A. The D14, D15, and D16 LEDs are connected to GPIOs of the MC33665A and depend on the configuration of the MC33665A device. The default use is listed in Table 1.
Table 1. Status LEDs

LED Description MC33665A signal
D13 – green Active: Indicates the MC33665A operating state STB_OUT_N
D16 – orange ReqHigh (default use): Indicates Request Queue High status

GPIO0
D15 – orange| User (default use): optional for User purpose| GPIO1
D14 – red| Error (default use): optional indicating error status| GPIO3

5.4.1 Connectors
The KIT-PC2TPLEVB has one connector to interface to a PC and two TPL ports.

NXP UM11900 Computer to ETPL Dongle - Connectors

Connector J5 connects the KIT-PC2TPLEVB to the UART-to-USB translator cable. Pin 1 of the TTL-232R-5V (black wire) must be connected to the J5 Pin 1 as shown in Figure 4.
Table 2. Interface – J5

Pin number Connection Description
1 GND Ground
2 Req High Request Queue High output (connect to PC UART CTS input)
3 VDD5V 5 V supply input
4 Req Data Request Data input (connect to PC UART TXD output)
5 Rsp Data Response Data output (connect to PC UART RXD input)
6 Hold Hold input (optional connect to PC UART RTS output)

Connectors J1 and J2 connects to the KIT-PC2TPLEVB TPL ports 0 and 1.
Table 3. TPL port 0 – J1

Pin number Connection Description
1 TPL0_P TPL port 0 (positive)
2 TPL0_N TPL port 0 (negative)

Table 4. TPL port 1 – J2

Pin number Connection Description
1 TPL1_P TPL port 1 (positive)
2 TPL1_N TPL port 1 (negative)

5.5 Schematic, board layout, and bill of materials
The schematic, board layout and bill of materials for the KIT-PC2TPLEVB evaluation board are available at http://www.nxp.com/KITPC2TPLEVB.

Legal information

6.1 Definitions
Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information.
6.2 Disclaimers
Limited warranty and liability
— Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including – without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.
Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
Suitability for use in automotive applications — This NXP product has been qualified for use in automotive applications. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer.
Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application.
Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its  applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP.
NXP has a Product Security Incident Response Team (PSIRT) (reachable at [email protected]) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products.
6.3 Trademarks
Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© 2023 NXP B.V.
All rights reserved.
For more information, please visit: http://www.nxp.com
Date of release: 20 April 2023
Document identifier: UM11900

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