GOWIN GW1NS-4C Semiconductor Corporation User Guide

GOWIN GW1NS-4C Semiconductor Corporation

Specifications

• Product Name: Gowin_EMPU(GW1NS-4C) Hardware Design Reference Manual
• Trademark: Gowin_EMPU(GW1NS-4C)
• Trademark Holder: Guangdong Gowin Semiconductor Corporation
• Registration: China, U.S. Patent and Trademark Office, and other countries

Product Information

Gowin_EMPU(GW1NS-4C) Hardware Design Reference Manual provides detailed information about the hardware architecture, design flow, project templates, and reference designs for the Gowin_EMPU(GW1NS-4C) system.

Hardware Architecture
System Architecture

• Gowin_EMPU(GW1NS-4C) is an on-chip system consisting of MCU core system and FPGA core system.
• The MCU core system includes MCU Core, AHB and peripherals, AHB2APB Bridge, APB1 and peripherals.
• The FPGA core system includes clock and reset signal inputs, data…

Hardware Design Flow
The hardware design flow outlines the process of designing hardware for the Gowin_EMPU(GW1NS-4C) system.

Project Template
A project template is provided to assist users in creating new projects for the Gowin_EMPU(GW1NS-4C) system.

Reference Design
The reference design section contains detailed information about the pre- designed configurations and setups for the Gowin_EMPU(GW1NS-4C) system.

FAQ

• Q: Can I reproduce or transmit any part of the document?
  A: No, reproduction or transmission of any part of the document is not allowed without prior written consent of GOWINSEMI.

• Q: Is there a warranty provided for the product?
  A: GOWINSEMI assumes no liability and provides no warranty, except as outlined in the GOWINSEMI Terms and Conditions of Sale.

Copyright © 2024 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
is a trademark of Guangdong Gowin Semiconductor Corporation and is registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI.

Disclaimer

GOWINSEMI assumes no liability and provides no warranty (either expressed or implied) and is not responsible for any damage incurred to your hardware, software, data, or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions of Sale. GOWINSEMI may make changes to this document at any time without prior notice. Anyone relying on this documentation should contact GOWINSEMI for the current documentation and errata.

Revision History

02/08/2021

|

1.1E

| l  AHB PSRAM Memory Interface peripheral supported.

l  AHB HyperRAM Memory Interface peripheral supported.

l  APB SPI Nor Flash peripheral supported.

l  GPIO supports multiple port types.

l  I2C supports multiple port types.

l  ARM Keil MDK as well as GOWIN MCU Designer upgraded.

06/21/2021

|

1.2E

| l  Known issue of SPI full duplex read and write fixed.

l  Synplify Pro removed.

l  FPGA software upgraded.

l  Reference design updated.

12/16/2022

|

1.3E

| l  Known issue of port signal name fixed.

l  MCU IP updated and logic resources optimized.

l  Software development kit updated.

03/14/2024

|

2.0E

| l  System clock frequency and performance boosted.

l  Hardware reference design updated.

Hardware Architecture

System Architecture

Gowin_EMPU(GW1NS-4C) is an on-chip system consisting of MCU core system and FPGA core system, as shown in Figure 1-1.
Figure 1-1 System Architecture

MCU core system consists of MCU Core, AHB and peripherals, AHB2APB Bridge, APB1 and peripherals.
FPGA core system consists of the clock and reset signal input, data SRAM, instruction FLASH of MCU core system, APB2 Bridge, APB2 and peripherals.

System Feature
Gowin_EMPU(GW1NS 4C) includes two sub systems:

• MCU core system
• FPGA core system

MCU Core System
MCU core system includes:

• MCU Core:
  • ARM Cortex M3 Core, ARM architecture v7 M Thumb2 supporting 16 bit and 32 bit instruction set
  • DAP (Debug Access Port)
  • Bus Matrix
  • NVIC (Nested Vector Interrupt Controller)
  • TPIU (Trace Port Interface Unit)
• AHB and peripherals
  • GPIO
  • AHB2 Master user extension interface
  • AHB2 Slave user extension interface
• AHB2APB Bridge
• APB and peripherals
  • UART0
  • UART1
  • Timer0
  • Timer1
  • Watch Dog
  • RTC
  • APB2 Extension Interface

FPGA Core System

FPGA core system includes:

• External crystal oscillator clock input or internal crystal oscillator clock can be as the system clock source of MCU core system. The max. frequency of the system clock is up to 200MHz (Subject to the project design and the chip in use).
• The reset signal input can be as the system reset signal of MCU core system.
• Six user interrupt handling signals for user extension peripherals
• AHB Extension interface
  • SRAM and FLASH can be as the data and instruction memory respectively of MCU core system
  • One AHB2 Master user extension interface
  • One AHB2 Slave user extension interface
• APB2 Extension Interface
  • SPI Master
  • I2C Master
  • Twelve APB2 Master user extension interfaces
• Memory
  • The SRAM Size can be configured as 2KB, 4KB, 8KB and 16KB.
  • The FLASH Size as 32KB.

System Port
The definition of system ports is as shown in Table 1 1.
Table 1 1 Definition of System Ports

TPIU

trace_data| out| [3:0]| TPIU data output signal
user_int_0| in| 1| User Interrupt handling signal 0| ****

NVIC

user_int_1| in| 1| User Interrupt handling signal 1
Name| I/O| Data Width| Description| Module
---|---|---|---|---
user_int_2| in| 1| User Interrupt handling signal 2|
user_int_3| in| 1| User Interrupt handling signal 3
user_int_4| in| 1| User Interrupt handling signal 4
user_int_5| in| 1| User Interrupt handling signal 5
gpio| inout| [15:0]| GPIO signal| GPIO I/O
gpioin| in| [15:0]| GPIO input signal| ****

GPIO non-I/O

gpioout| out| [15:0]| GPIO output signal
gpioouten| out| [15:0]| GPIO output enable signal
uart0_rxd| in| 1| UART0 receive signal| ****

UART0

uart0_txd| out| 1| UART0 transmit signal
uart1_rxd| in| 1| UART1 receive signal| ****

UART1

uart1_txd| out| 1| UART1 transmit signal
scl| inout| 1| I2C serial clock signal| ****

I2C Master I/O

sda| inout| 1| I2C serial data signal
sclin| in| 1| I2C serial clock input signal| ****

I2C Master non-I/O

sclout| out| 1| I2C serial clock output signal
sclouten| out| 1| I2C serial clock output enable signal
sdain| in| 1| I2C serial data input signal
sdaout| out| 1| I2C serial data output signal
sdaouten| out| 1| I2C serial data output enable signal
mosi| out| 1| SPI master output / slave input| ****

SPI Master

miso| in| 1| SPI master input / slave output
sclk| out| 1| SPI clock signal
nss| out| 1| SPI slave selection signal
rtc_src_clk| in| 1| RTC signal| RTC
master_hclk| out| 1| Master clock signal| ****

AHB2 Master

master_hrst| out| 1| Master reset signal
master_hsel| out| 1| Master selection signal
master_haddr| out| [31:0]| Master address signal
master_htrans| out| [1:0]| Master transmit type signal
Name| I/O| Data Width| Description| Module
---|---|---|---|---
master_hwrite| out| 1| I/O of Master read and write signal|
master_hsize| out| [2:0]| Master transmit Size signal
master_hburst| out| [2:0]| Master burst type signal
master_hprot| out| [3:0]| Master protect and control signal
master_memattr| out| [1:0]| Master memattr signal
master_exreq| out| 1| Matter exreq signal
master_hmaster| out| [3:0]| Master label signal
master_hwdata| out| [31:0]| Master write data signal
master_hmastlock| out| 1| Master lock signal
master_hreadymux| out| 1| Master hreadymux signal
master_hauser| out| 1| Master hauser signal
master_hwuser| out| [3:0]| Master hwuser signal
master_hrdata| in| [31:0]| Master read data signal
master_hreadyout| in| 1| Master hreadyout signal
master_hresp| in| 1| Master transmit status signal
master_exresp| in| 1| Master exresp signal
master_hruser| in| [2:0]| Master hruser signal
slave_hsel| in| 1| Slave selection signal| ****

AHB2 Slave

slave_haddr| in| [31:0]| Slave address signal
slave_htrans| in| [1:0]| Slave transmit type signal
slave_hwrite| in| 1| I/O of Slave read and write signal
slave_hsize| in| [2:0]| Slave transmit Size signal
slave_hburst| in| [2:0]| Slave burst type signal
slave_hprot| in| [3:0]| Slave protect and control signal
slave_hmaster| in| [3:0]| Slave label signal
slave_hwdata| in| [31:0]| Slave write data signal
slave_hmastlock| in| 1| Slave lock signal
slave_hrdata| out| [31:0]| Slave read data signal
slave_hready| out| 1| Slave ready signal
slave_hresp| out| 1| Slave transmit status signal
slave_hexresp| out| 1| Slave hexresp signal
Name| I/O| Data Width| Description| Module
---|---|---|---|---
slave_hruser| out| [2:0]| Slave hruser signal|
slave_hmemattr| in| [1:0]| Slave hmemattr signal
slave_hexreq| in| 1| Slave hexreq signal
slave_hauser| in| 1| Slave hauser signal
slave_hwuser| in| [3:0]| Slave hwuser signal
master_pclk| out| 1| APB2 Master clock signal| ****

APB2 Master [1-12]

master_prst| out| 1| APB2 Master reset signal
master_penable| out| 1| APB2 Master enable signal
master_paddr| out| [7:0]| APB2 Master address signal
master_pwrite| out| 1| I/O of APB2 Master read and write signal
master_pwdata| out| [31:0]| APB2 Master write data signal
master_pstrb| out| [3:0]| APB2 Master write strobe signal
master_pprot| out| [2:0]| APB2 Master protect type signal
master_psel1| out| 1| APB2 Master [1 ] selection signal| ****

APB2 Master [1]

master_pready1| in| 1| APB2 Master [1 ] ready Signal
master_prdata1| in| [31:0]| APB2 Master [1 ] read data signal
master_pslverr1| in| 1| APB2 Master[ ] transmit failure signal
master_psel2| out| 1| APB2 Master [2 ] selection signal| ****

APB2 Master [2]

master_pready2| in| 1| APB2 Master [2 ] ready Signal
master_prdata2| in| [31:0]| APB2 Master [2 ] read data signal
master_pslverr2| in| 1| APB2 Master[ ] transmit failure signal
master_psel3| out| 1| APB2 Master [3 ] selection signal| ****

APB2 Master [3]

master_pready3| in| 1| APB2 Master [3 ] ready Signal
master_prdata3| in| [31:0]| APB2 Master [3 ] read data signal
master_pslverr3| in| 1| APB2 Master[ ] transmit failure signal
master_psel4| out| 1| APB2 Master [4 ] selection signal| ****

APB2 Master [4]

master_pready4| in| 1| APB2 Master [4 ] ready signal
Name| I/O| Data Width| Description| Module
---|---|---|---|---
master_prdata4| in| [31:0]| APB2 Master [4 ] read data signal|
master_pslverr4| in| 1| APB2 Master[ ] transmit failure signal
master_psel5| out| 1| APB2 Master [5 ] selection signal| ****

APB2 Master [5]

master_pready5| in| 1| APB2 Master [5 ] ready signal
master_prdata5| in| [31:0]| APB2 Master [5 ] read data signal
master_pslverr5| in| 1| APB2 Master[ ] transmit failure signal
master_psel6| out| 1| APB2 Master [6 ] selection signal| ****

APB2 Master [6]

master_pready6| in| 1| APB2 Master [6 ] ready signal
master_prdata6| in| [31:0]| APB2 Master [6 ] read data signal
master_pslverr6| in| 1| APB2 Master[ ] transmit failure signal
master_psel7| out| 1| APB2 Master [7 ] selection signal| ****

APB2 Master [7]

master_pready7| in| 1| APB2 Master [7 ] ready signal
master_prdata7| in| [31:0]| APB2 Master [7 ] read data signal
master_pslverr7| in| 1| APB2 Master[ ] transmit failure signal
master_psel8| out| 1| APB2 Master [8 ] selection signal| ****

APB2 Master [8]

master_pready8| in| 1| APB2 Master [8 ] ready signal
master_prdata8| in| [31:0]| APB2 Master [8 ] read data signal
master_pslverr8| in| 1| APB2 Master[ ] transmit failure signal
master_psel9| out| 1| APB2 Master [9 ] selection signal| ****

APB2 Master [9]

master_pready9| in| 1| APB2 Master [9 ] ready signal
master_prdata9| in| [31:0]| APB2 Master [9 ] read data signal
master_pslverr9| in| 1| APB2 Master[ ] transmit failure signal
master_psel10| out| 1| APB2 Master [10 ] selection| APB2 Master [10]
Name| I/O| Data Width| Description| Module
---|---|---|---|---
| | | signal|
master_pready10| in| 1| APB2 Master [10 ] ready signal
master_prdata10| in| [31:0]| APB2 Master [10 ] read data signal
master_pslverr10| in| 1| APB2 Master[ ] transmit failure signal
master_psel11| out| 1| APB2 Master [11 ] selection signal| ****

APB2 Master [11]

master_pready11| in| 1| APB2 Master [11 ] ready signal
master_prdata11| in| [31:0]| APB2 Master [11 ] read data signal
master_pslverr11| in| 1| APB2 Master[11] transmit failure signal
master_psel12| out| 1| APB2 Master [12 ] selection signal| ****

APB2 Master [12]

master_pready12| in| 1| APB2 Master [12 ] ready signal
master_prdata12| in| [31:0]| APB2 Master [12 ] read data signal
master_pslverr12| in| 1| APB2 Master[12] transmit failure signal

System Resource Utilization and Performance Statistics
The system resource utilization and performance statistics of Gowin_EMPU(GW1NS 4C) are as shown in Table 1 2 .

Resources

Configuration

| LUTs| Registers| BSRAMs| Frequency

(MHz)

---|---|---|---|---
MCU core system| 33| 19| 4| 200
MCU core system + I2C Master + SPI Master| 456| 282| 4| 100
MCU core system + APB SPI-Flash Memory| 1073| 618| 4| 50
MCU core system + AHB PSRAM Memory| 1709| 1464| 4| 100
MCU core ssystem + AHB HyperRAM Memory| 1163| 1008| 4| 100

Table 1 2 System Resource Utilization and Performance Statistics

Hardware Design Flow

Hardware Target

• DK START GW1NSR4C QN48G V1.1
  GW1NSR LV4CQN48GC7/I6

• DK START GW1NSR4C QN48P V1.1
  GW1NSR LV4CQN48PC7/I6

• DK START GW1NSR4C MG64P V1.1
  GW1NSR LV4CMG64PC7/I6

Software Version
Tested software version: Gowin_V1.9.9.01 (64 bit)

IP Core Generator
The IP Core Generator tool from Gowin Software is used to configure and generate Gowin_EMPU(GW1NS 4C) IP Core.

Programmer
Gowin Programmer tool is used to download the bitstream file of Gowin_EMPU(GW1NS 4C).
For the Gowin Programmer usage, please refer to SUG502, Gowin Programmer User Guide.

Design Flow
Gowin_EMPU(GW1NS 4C) hardware design flow is as follows:

• Configure and generate Gowin_EMPU(GW1NS 4C) IP Core using IP Core Generator and import the current project.
• Instantiate Gowin_EMPU(GW1NS 4C), import user design, and connect user design with Gowin_EMPU Top Module.
• Add physical and timing Constraints.
• Use GowinSynthesis to synthesize and generate post synthesis netlist file.
• Use Place & Route to generate bitstream file.
• Use Programmer to download bitstream file to chip to chip.

Project Template

Project Creation

Create a New Project
Double click to open the Gowin Software. Click “File > New… > FPGA Design Project” on the menu bar, as shown in Figure 3 1.
Figure 3 1 Create a FPGA Design Project

Set Project Name and Path
Enter the project name and select the project path, as shown in Figure 3 2.
Figure 3 2 Set Project Name and Path

Select Device
Configure “Series”, “Device”, “Device Version”, “Package”, “Speed”, and “Part Number”, as shown in Figure 3 3.
Take DK_START_GW1NSR4C_QN48G_V1.1 reference design as an instance.

• Series: GW1NSR
• Device: GW1NSR 4C
• Device Version: Any
• Package: QFN48G
• Speed: C7/I6
• Part Number: GW1NSR LV4CQN48GC7/I6

Project Creation Completed
Project creation is completed, as shown in Figure 3 4.
Figure 3 4 Project Creation Completed

Hardware Design

• Use IP Core Generator to generate Gowin_EMPU(GW1NS 4C) hardware design.
• Select “Tools > IP Core Generator” in the menu bar or “” to open the IP Core Generator.
• Select ” Soft IP Core > Microprocessor System > Hard Core MCU > Gowin_EMPU(GW1NS 4C) 2.0″, as shown in Figure 3 5.
  Figure 3 5 Select Gowin_EMPU(GW1NS 4C) IP Core

The system architecture of Gowin_EMPU(GW1NS 4C) is as shown in Figure 3 6.
The grayed modules are the default, and you can not configure them; if the modules are not grayed, you can open them to configure them.

The modules that you can choose to configure include:

• TPIU
• NVIC: six user interrupt handling signals USER_INT0~5
• AHB2 Slave: FPGA core system can extend AHB2 Slave peripherals.
• AHB2 Master: FPGA core system can extend AHB2 Master peripherals.
• GPIO
• UART0 and UART1
• RTC
• The SRAM can be configured as 2KB, 4KB, 8KB or 16KB, 16KB by default.
• I2C: FPGA core system integrates I2C Master.
• SPI: FPGA core system integrates SPI Master.
• APB2 Master[1 12]: FPGA core system can extend twelve APB2 Master user devices.
  Figure 3 6 System Architecture

The system configuration options of Gowin_EMPU(GW1NS 4C) are as shown in Table 3 1.

default.
Enable USER_INT_1| Enable user interrupt handling signal [1], disabled by default.
Enable USER_INT_2| Enable user interrupt handling signal [2], disabled by default.
Enable USER_INT_3| Enable user interrupt handling signal [3], disabled by default.
Enable USER_INT_4| Enable user interrupt handling signal [4], disabled by default.
Enable USER_INT_5| Enable user interrupt handling signal [5], disabled by default.
Enable GPIO| Enable GPIO, disabled by default.
Enable GPIO I/O| Enable GPIO inout port, enabled by default.
Enable UART0| Enable UART0, disabled by default.
Enable UART1| Enable UART1, disabled by default.
Enable RTC| Enable RTC, disabled by default.
Enable AHB2 Master| Enable AHB2 Master user extension interface, disabled by default.
Enable AHB2 Slave| Enable AHB2 Slave user extension interface, disabled by default.
Enable I2C| Enable I2C Master, disabled by default.
Enable I2C I/O| Enable I2C inout port, enabled by default.
Enable SPI| Enable SPI Master, disabled by default.
Enable APB2 Master 1| Enable APB2 Master [1] user extension interface, disabled by default.
Enable APB2 Master 2| Enable APB2 Master [2] user extension interface, disabled by default.
Enable APB2 Master 3| Enable APB2 Master [3] user extension interface, disabled by default.
Enable APB2 Master 4| Enable APB2 Master [4] user extension interface, disabled by default.
Enable APB2 Master 5| Enable APB2 Master [5] user extension interface, disabled by default.
Enable APB2 Master 6| Enable APB2 Master [6] user extension interface, disabled by default.
Enable APB2 Master 7| Enable APB2 Master [7] user extension interface, disabled by default.
Enable APB2 Master 8| Enable APB2 Master [8] user extension interface, disabled by default.
Enable APB2 Master 9| Enable APB2 Master [9] user extension interface, disabled by default.
Enable APB2 Master 10| Enable APB2 Master [10] user extension interface, disabled by default.
Enable APB2 Master 11| Enable APB2 Master [11] user extension interface, disabled by default.
Enable APB2 Master 12| Enable APB2 Master [12] user extension interface, disabled by default.

SRAM Size

| The SRAM Size can be configured as 2KB, 4KB, 8KB and 16KB, 16KB by default.

TPIU Configuration
Double click to configure TPIU, as shown in Figure 3 7.
If “Enable TPIU” is selected, Gowin_EMPU(GW1NS 4C) supports TPIU, disabled by default.
Figure 3 7 TPIU Configuration

NVIC Configuration
Double click to open NVIC to configure USER_INT_0~5 for user extension peripherals of FPGA core system, as shown in Figure 3 8.

• If Enable USER_INT_0 is selected, Gowin_EMPU(GW1NS 4C) supports user interrupt handling signal [0], disabled by default.
• If Enable USER_INT_1 is selected, Gowin_EMPU(GW1NS 4C) supports user interrupt handling signal [1], disabled by default.
• If Enable USER_INT_2 is selected, Gowin_EMPU(GW1NS 4C) supports user interrupt handling signal [2], disabled by default.
• If Enable USER_INT_3 is selected, Gowin_EMPU(GW1NS 4C) supports user interrupt handling signal [3], disabled by default.
• If Enable USER_INT_4 is selected, Gowin_EMPU(GW1NS 4C) supports user interrupt handling signal [4], disabled by default
• If Enable USER_INT_5 is selected, Gowin_EMPU(GW1NS 4C) supports user interrupt handling signal [5], disabled by default.
  Figure 3 8 NVIC Configuration

GPIO Configuration
Double click to configure GPIO, as shown in Figure 3 9.

• If “Enable GPIO” is selected, Gowin_EMPU(GW1NS 4C) supports GPIO, disabled by default.
• If “Enable GPIO” is selected, you can configure GPIO port type.
• If “Enable GPIO I/O” is selected, GPIO supports inout port, supported by default

UART Configuration
Double click to configure UART0 or UART1, as shown in Figure 3 10.

• If “Enable UART0” is selected, Gowin_EMPU(GW1NS 4C) supports UART0, disabled by default.
• If “Enable UART1” is selected, Gowin_EMPU(GW1NS 4C) supports UART1, disabled by default.

AHB2 Master / Slave Configuration
Double click to configure AHB2 Master or AHB2 Slave, as shown in Figure 3 11.

• If “Enable AHB2 Master” is selected, Gowin_EMPU(GW1NS 4C) supports AHB2 Master, disabled by default.
• If “Enable AHB2 Slave” is selected, Gowin_EMPU(GW1NS 4C) supports AHB2 Slave, disabled by default.
• The base address mapping of AHB2 Master user extension peripherals is 0xA0000000.

SRAM Configuration

• Double click to configure SRAM Size, as shown in Figure 3 12.
• The SRAM Size can be configured as 2KB, 4KB, 8KB or16KB, 16KB by default.

I 2 C Configuration
Double click to configure I2C Master, as shown in Figure 3 13.

• If “Enable I2C” is selected, Gowin_EMPU(GW1NS 4C) supports I2C Master, disabled by default.
• If “Enable I2C” is selected, you can configure I2C Master port type.
• If “Enable I2C I/O” is selected, I2C Master supports inout port, supported by default

SPI Configuration
Double click to configure SPI Master, as shown in Figure 3 14.
If “Enable SPI” is selected, Gowin_EMPU(GW1NS 4C) supports SPI Master, disabled by default.
Figure 3 14 SPI Configuration

RTC Configuration

Double click to configure RTC, as shown in Figure 3 15.
If “Enable RTC” is selected, Gowin_EMPU(GW1NS 4C) supports RTC, disabled by default.
The port rtc_src_clk is input a 3.072MHz clock, internally divided by the RTC to 1Hz.
Figure 3 15 RTC Configuration

APB2 Master Configuration
Double click to configure APB2 Master[1 12], as shown in Figure 3 16.

• If “Enable APB2 Master 1” is selected, Gowin_EMPU(GW1NS 4C) supports APB2 Master [1], disabled by default.
• If “Enable APB2 Master 2” is selected, Gowin_EMPU(GW1NS 4C) supports APB2 Master [2], disabled by default.
• If “Enable APB2 Master 3” is selected, Gowin_EMPU(GW1NS 4C) supports APB2 Master [3], disabled by default.
• If “Enable APB2 Master 4” is selected, Gowin_EMPU(GW1NS 4C) supports APB2 Master [4], disabled by default.
• If “Enable APB2 Master 5” is selected, Gowin_EMPU(GW1NS 4C) supports APB2 Master [5], disabled by default.
• If “Enable APB2 Master 6” is selected, Gowin_EMPU(GW1NS 4C) supports APB2 Master [6], disabled by default.
• If “Enable APB2 Master 7” is selected, Gowin_EMPU(GW1NS 4C) supports APB2 Master [7], disabled by default.
• If “Enable APB2 Master 8” is selected, Gowin_EMPU(GW1NS 4C) supports APB2 Master [8], disabled by default.
• If “Enable APB2 Master 9” is selected, Gowin_EMPU(GW1NS 4C) supports APB2 Master [9], disabled by default.
• If “Enable APB2 Master 10” is selected, Gowin_EMPU(GW1NS 4C) supports APB2 Master [10], disabled by default.
• If “Enable APB2 Master 11” is selected, Gowin_EMPU(GW1NS 4C) supports APB2 Master [11], disabled by default.
• If “Enable APB2 Master 12” is selected, Gowin_EMPU(GW1NS 4C) supports APB2 Master [12], disabled by default.
  Figure 3 16 APB2 M aster[1 12] Configuration

The base address mapping of APB2 Master [1 12] user extension peripherals is as shown in Table 3 2.

PSRAM Memor y Interface
If FPGA product GW1NSR 4C MG64P is selected, Gowin_EMPU (GW1NS 4C) supports the FPGA core system extended external device PSRAM Memory Interface.
The software development kit provides the external device PSRAM Memory Interface as a reference design.

Hardware Design Flow

• IP Core Generator is used to configure and generate Gowin_EMPU (GW1NS 4C) IP Core, and the AHB2 Master user extension interface is enabled.

• IP Core Generator is used to configure and generate PSRAM Memory Interface IP Core.

  • Memory Clock 100MHz
  • For other options, you can select default configuration.

• Design the AHB PSRAM Memory Interface IP implementing the AHB bus interface, refer to gw_ahb_psram.v.

• Instantiate Gowin_EMPU(GW1NS 4C) Top Module and AHB PSRAM Memory Interface Top Module.

• Connect Gowin_EMPU(GW1NS 4C) to AHB interface of AHB PSRAM Memory Interface.
  Reference Design
  You can click here to get the following reference design:

• Hardware Reference Design \ref_design\FPGA_RefDesign\DK_START_GW1NSR4C_MG64P_V1.1\gowin_empu\cm3_psram_demo

• Software Programming Reference Design

  • – …\ref_design\MCU_RefDesign\MDK_RefDesign\cm3_demo\project\psram
  • – …\ref_design\MCU_RefDesign\GMD_RefDesign\cm3_demo\project\psram

HyperRAM Memory Interface

If FPGA product GW1NSR 4C or GW1NSER 4C QN48P is selected, Gowin_EMPU (GW1NS 4C) supports the FPGA core system extended external device HyperRAM Memory Interface.
The software development kit provides the external device HyperRAM Memory Interface as a reference design.

Hardware Design Flow

• IP Core Generator is used to configure and generate Gowin_EMPU (GW1NS 4C), and AHB2 Master user extension interface is enabled.
• IP Core Generator is used to configure and generate HyperRAM Memory Interface embedded IP Core.
  • Memory Clock 100MHz
  • For other options, you can select default configuration.
• Design AHB HyperRAM Memory Interface IP implementing the AHB bus interface, refer to gw_ahb_hyperram.v.
• Instantiate Gowin_EMPU(GW1NS 4C) Top Module and AHB HyperRAM Memory Interface Top Module.
• Connect Gowin_EMPU(GW1NS 4C) to AHB interface of AHB HyperRAM Memory Interface.

Reference Design
You can click here to get the following reference design:
Hardware Reference Design \ref_design\FPGA_RefDesign\DK_START_GW1NSR4C_QN48P_V1.1\gowin_empu\cm3_hyperram_demo

• Software Programming Reference Design
  • – …\ref_design\MCU_RefDesign\MDK_RefDesign\cm3_demo\project\hyper_ram
  • – …\ref_design\MCU_RefDesign\GMD_RefDesign\cm3_demo\project\hyper_ram

SPI Flash Memory

If FPGA product GW1NSR 4C or GW1NSER 4C QN48G is selected, Gowin_EMPU (GW1NS 4C) supports the FPGA core system extended external device SPI Flash Memory.
The software development kit provides the external device SPI Flash Memory as a reference design.

Hardware Design Flow

• You can configure and generate Gowin_EMPU (GW1NS 4C) IP Core using IP Core Generator, and APB2 Master [1] user extension interface is enabled.
• Design SPI Flash Memory IP, refer to gw_spiflash.v.
• Design APB SPI Flash Memory IP implementing the APB bus interface, refer to gw_spiflash.v.
• Instantiate Gowin_EMPU(GW1NS 4C) Top Module and APB SPI Flash Memory Top Module.
• Connect Gowin_EMPU(GW1NS 4C) to APB interface of APB SPI Flash Memory.

Reference Design
You can click here to get the following reference design:

• Hardware Reference Design \ref_design\FPGA_RefDesign\DK_START_GW1NSR4C_QN48G_V1.1\gowin_empu\cm3_spiflash_demo
• Software Programming Reference Design
  • – …\ref_design\MCU_RefDesign\MDK_RefDesign\cm3_demo\project\spi_flash
  • – …\ref_design\MCU_RefDesign\GMD_RefDesign\cm3_demo\project\spi_flash

User Design

• After configuration, you can generate Gowin_EMPU(GW1NS 4C) IP Core.
• Instantiate Gowin_EMPU(GW1NS 4C) Top Module.
• Import user design and connect it with Gowin_EMPU(GW1NS 4C) Top Module to form a complete RTL design.

Constraint
After RTL design is completed, physical constraints can be generated according to the used development board and the IO. Timing constraints file can be generated according to timing requirements. For the details on physical constraints generation, please refer to SUG940, Gowin Design Timing Constraints Guide, SUG935, Gowin Design Physical Constraints Guide

Configuration
Synthesize Configuration
The “Synthesize” configuration is as shown in Figure 3 17.

• Configure “Top Module/Entity” according to the top module name in the design.
• Configure “Include Path” according to the file path in the design.
• Configure Verilog Language, such as System Verilog 2017.

Place Configuration
Configure the “Place” option as shown in Figure 3 18. For example, select “2” for “Place Option” to enhance the software timing.

Route Configuration
Configure the “Route” option as shown in Figure 3 19. For example, select “2” for “Route Option” to enhance the software timing.

Bitstream Configuration
Configure the “Bitstream” option as shown in Figure 3 20.
Figure 3 20 Bitstream Configuration

Synthesize
Run GowinSynthesis to complete the synthesis of RTL design to generate post synthesis netlist file, as shown in Figure 3 21.
Figure 3 21 Synthesize

For the tool usage, please refer to SUG100, Gowin Software User Guide.

Place & Route
Run the Place & Route tool in Gowin software and generate the bitstream file, as shown in Figure 3 22.

For the tool usage, please refer to SUG100, Gowin Software User Guide.

Download

• Download the bitstream file using Gowin Programmer.
• Open Programmer in Gowin software or under the installation path.
• Click “Edit > Configure Device” on the menu bar or “Configure Device” () on the tool bar to open the “Device configuration”.
• If FPGA product GW1NS 4C or GW1NSR 4C is selected, configuration options are as shown in Figure 3 23.

1. Select “MCU Mode” in “Access Mode” drop down list.
2. Select “Firmware Erase, Program” or “Firmware Erase, Program, Verify” in “Operation” drop down list.

If FPGA product GW1NSER 4C is selected, configuration options are as shown in Figure 3 24.

• Select “SecureFPGA Mode” in “Access Mode” drop-down list.

• Select “Firmware Erase, Program Securely” in “Operation” drop down list.
  Figure 3 24 Download Configuration for GW1NSER 4C
  Import hardware design bitstream file in “Programming Options > File name” .

• Click “Save” to complete the configuration.

Note!

• Import software programming Binary file in ” FW/MCU Input Options > Firmware/Binary File”, please refer to IPUG928, Gowin_EMPU(GW1NS 4C) IDE Software Reference Manual.
• After device configuration, click Program/Configure “” on the Programmer tool bar to complete downloading of hardware design bitstream file and software programming Binary file.
• For the usage of Programmer, please refer to SUG502, Gowin Programmer User Guide.

Reference Design

Gowin_EMPU(GW1NS 4C) provides hardware reference design in Gowin Software (tested software version V1.9.9.01 (64 bit)). You can click here to get the following reference design.

• …\ref_design\FPGA_RefDesign\DK_START_GW1NSR4C_MG64P_V1.1\gowin_empu\cm3_psram_demo
• …\ref_design\FPGA_RefDesign\DK_START_GW1NSR4C_QN48G_V1.1\gowin_empu\cm3_i2c_demo
• …\ref_design\FPGA_RefDesign\DK_START_GW1NSR4C_QN48G_V1.1\gowin_empu\cm3_spiflash_demo
• …\ref_design\FPGA_RefDesign\DK_START_GW1NSR4C_QN48P_V1.1\gowin_empu\cm3_ahb2_demo
• …\ref_design\FPGA_RefDesign\DK_START_GW1NSR4C_QN48P_V1.1\gowin_empu\cm3_apb2_demo
• …\ref_design\FPGA_RefDesign\DK_START_GW1NSR4C_QN48P_V1.1\gowin_empu\cm3_demo
• …\ref_design\FPGA_RefDesign\DK_START_GW1NSR4C_QN48P_V1.1\gowin_empu\cm3_hyperram_demo
• …\solution\RTOS\ref_design\FPGA_RefDesign\gowin_empu
• …\solution\RunInSRAM_FromEmbFlash\ref_design\FPGA_RefDesign\gowin_empu
• …\solution\RunInSRAM_FromSIPFlash\ref_design\FPGA_RefDesign\gowin_empu

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