MICROCHIP LAN8650/1 Ethernet Switches Instructions

LAN8650/1
Hardware Design Checklist

INTRODUCTION

This document provides a hardware design checklist for the Microchip LAN8650/1. These checklist items should be followed when utilizing the LAN8650/1 in a new design.
A summary of these items is provided in Section 12.0, HARDWARE CHECKLIST SUMMARY.
Detailed information on the following topics can be found in the corresponding section:

CONFORMITY

Table 2-1 shows the conformity relationship between product revision, silicon, and Hardware Design Checklist. This check list applies to silicon revisions as shown below. For the most current specifications, please visit the product pages on the website for LAN8650 and LAN8651 10BASE-T1S Single Pair Ethernet MAC-PHY [3].
TABLE 2-1: CONFORMITY TABLE

Note 1: The product revision is noted in the package top marking.
2: The silicon revision is obtained by reading the Manufacturer’s Model Revision from the PHY Identifier 2 register.

 GENERAL CONSIDERATIONS

3.1 Pin Check
Check the pinout of the part against the LAN8650/1 10BASE-T1S MAC-PHY Ethernet Controller With SPI Data
Sheet [1]. Ensure each pin matches the data sheet and is configured as input, output, or bidirectional.

POWER AND GROUND

4.1 Power
TABLE 4-1: POWER PINOUT

| LAN8650|

LAN8651

---|---|---
VDDP| Pin 7, Pin 17| Pin 7, Pin 17
VDDAU| Pin 25| Pin 25
VDDA| Pin 29| Pin 29
VDDC| Pin 6, Pin 15, Pin 21|
CCOMP| | Pin 21

The LAN8651 contains an integrated 1.8V regulator and only requires a single 3.3V supply while the LAN8650 requires both 3.3V and 1.8V external supplies.

• The digital pin supply, VDDP, is connected to a 3.3V supply.
  – If a ferrite bead is used to create an optional power island for the VDDP pins, a large bulk capacitor (typically 10 μF) should be placed in between the ferrite bead and the pin decoupling capacitors. The ferrite bead and bulk capacitor should be placed where the power supply sources the 3.3V local power island and as close as possible to the LAN8650/1. See Figure 4-2 and Figure 4-3.
  – If a ferrite bead is not used, a single bulk capacitor (typically 10 μF) should be placed on the 3.3V supply in the direction from which the power supply sources the LAN8650/1. The same bulk capacitor may be used for VDDP power as is used for VDDA power. See Figure 4-1.

• The analog pin supply, VDDA, is connected to a 3.3V supply.
  – If a ferrite bead is used to create an optional power island for the VDDA pins, a large bulk capacitor (typically 10 μF) should be placed in between the ferrite bead and the pin decoupling capacitors. The ferrite bead and bulk capacitor should be placed where the power supply sources the 3.3V local power island and as close as possible to the LAN8650/1. See Figure 4-2 and Figure 4-3.
  – If a ferrite bead is not used, a single bulk capacitor (typically 10 μF) should be placed on the 3.3V supply in the direction from which the power supply sources the LAN8650/1. The same bulk capacitor may be used for VDDA power as is used for VDDP power. See Figure 4-1.

• The LAN8650 core pin supply, VDDC, is connected to a 1.8V supply.
  – A single bulk capacitor (typically 10 μF) should be placed on the 1.8V supply in the direction from which the power supply sources the LAN8650.

• The LAN8651 CCOMP pin requires a 4.7 μF low ESR metal film capacitor connected to the PCB ground plane.

• If low-power wake-up support is desired, the continuous analog supply, VDDAU, is connected to a 3.3V uninter- ruptable continuous supply.
  – If a ferrite bead is used to create an optional power island for the VDDAU pin, a large bulk capacitor (typically 10 μF) should be placed in between the ferrite bead and the pin decoupling capacitors. The ferrite bead and bulk capacitor should be placed where the continuous power supply sources the 3.3V local power island and as close as possible to the LAN8650/1. See Figure 4-3.

• – If a ferrite bead is not used, a single bulk capacitor (typically 10 μF) should be placed on the 3.3V continuous supply in the direction from which the continuous power supply sources the LAN8650/1. See Figure 4-1.

• If low-power wake-up is not used, connect VDDAU to the same 3.3V switched supply as the VDDA pin. See Figure 4-2.

• A single 10 μF bulk capacitor may be placed on the 3.3V power supply for pins that do not use ferrite beads to create local power islands. The 10 μF bulk capacitor should be placed on the 3.3V supply in the direction from which the power supply sources the LAN8650/1.

• Each individual VDDP, VDDC, VDDA and VDDAU power pin requires a 0.01 μF and 0.1 μF decoupling capacitor.

• During layout, the smallest value capacitor, 0.01 μF, should have priority and be placed closest to the respective power pin. The tightest decoupling capacitor placement is underneath the device on the opposite side of the board. Each capacitor should have dedicated power and ground vias. Vias should not be shared.

• After placing the 0.01 μF capacitor, the next priority is the placing of the 0.1 μF capacitor. It follows the same general design rules as the 0.01 μF capacitor.

• The VDDA pin must never exceed the VDDAU pin by more than 0.5V, including during power-up and powerdown. Use optional Schottky diode for power sequencing.

• The LAN8650 VDDC pins must never exceed the VDDP pins by more than 0.5V, including during power-up and powerdown. Use optional Schottky diode for power sequencing.

General Power supply connections for the LAN8650 and LAN8651 are shown in Figure 4-1. Power supply connections utilizing ferrite beads to create localized power islands are shown in Figure 4-2 and Figure 4-3. Figure 4-3 illustrates power supply connections utilizing an uninterruptable, continuous power supply for low-power wake-up. For more information, please refer to the LAN8650/1 10BASE-T1S MAC-PHY Ethernet Controller With SPI Data Sheet [1], section “Power Connectivity”.
FIGURE 4-1: LAN8650/1 MINIMAL POWER CONNECTIVITY

† 3.3V continuous power only required for low-power wake-up applications.
Connect VDDAU to 3.3V switched power if low-power wake-up is not used.
FIGURE 4-2: LAN8650/1 LOCALIZED POWER ISLAND CONNECTIVITY WITHOUT SLEEP FIGURE 4-3: LAN8650/1 LOCALIZED POWER ISLAND CONNECTIVITY WITH SLEEP 4.2 Ground
TABLE 4-2: GROUND PINOUT

| LAN8650/1
---|---
VSS| Pin 2, Pin 3, Pin 5
ePAD| exposed thermal pad

• The LAN8650/1 contains a common ground thermal exposed pad. The exposed pad must be connected directly to a solid, contiguous digital ground plane through a thermal via array described in the LAN8650/1 10BASE-T1S MAC-PHY Ethernet Controller With SPI Data Sheet [1].
• All VSS pins must be connected to ground.

CLOCK CIRCUIT

TABLE 5-1: CLOCK CIRCUIT PINOUT

| LAN8650/1
---|---
XTI| Pin 27
XTO| Pin 28

The LAN8650/1 XTI and XTO pin must be connected to a 25 MHz ± 100 ppm clock source.

• 25 MHz ± 100 ppm crystal oscillator in fundamental, parallel resonant mode connected across the XTI/XTO pair with appropriately size C1 and C2 load capacitors (recommended value 10 pF – 22 pF).

The clock circuit is shown in Figure 5-1. A parallel resistance across the crystal between XTI and XTO is not required.
The LAN8650/1 contains an internal 1 M resistance between XTI and XTO.
FIGURE 5-1: CLOCK CIRCUIT

ETHERNET PHY EXTERNAL BIN

Please refer Microchip’s LAN86xx Bus Interface Network (BIN) Reference Design Application Note [2] for the latest recommended BIN. Be aware of the voltage ratings of the components and adhere to suggested ratings as described in the BIN.
TABLE 6-1: ETHERNET PHY EXTERNAL BIN PINOUT

| LAN8650/1
---|---
TRXP| Pin 30
TRXN| Pin 31

SPI (SERIAL PERIPHERAL INTERFACE)

TABLE 7-1: SPI PINOUT

| LAN8650/1
---|---
SCLK| Pin 12
SDI| Pin 13
SDO| Pin 10
CS_N| Pin 11
IRQ_N| Pin 9

• The SPI interface must be connected between the SPI host and the LAN8650/1.
• The CS_N pin is an active low input; a pull-up resistor should be added to keep this pin in a known state. This pin must never be left floating.
• The IRQ_N pin is an active low, open drain output. When used, this pin requires an external pull-up resistor to VDDP. When unused, this pin can be left unconnected.
• Series resistors matching the PCB trace impedance may be added on the driver side of the clock and data lines (SCK/SDI series resistor at SPI host).
• During the development phase, the option to populate test pins are recommended on the CS_N, SCLK, MISO, MOSI, and IRQ_N traces. Additionally, a nearby ground test pin is recommended. The existence of these test pins may significantly aid in debugging and firmware development.

RESET

TABLE 8-1: RESET PINOUT

| LAN8650/1
---|---
RESET_N| Pin 8

• When the external RESET_N pin is used, a pull-up resistor to VDDP may be added if the device driving this line is an open-drain output. If the device is a push-pull output, then the external pull-up resistor is not required.
• If the external RESET_N pin is unused, it must be connected to VDDP. The external RESET_N pin must never be left floating.
• The LAN8650/1 RESET_N input pin is not internally debounced and should therefore not be directly connected to a push button. The RESET_N pin should be stable for a minimum time of 5 us. See the “RESET_N Timing” section in the LAN8650/1 10BASE-T1S MAC-PHY Ethernet Controller With SPI Data Sheet [1] for more information.

POWER MANAGEMENT PINS

In order to utilize the ultra low-power sleep mode, the INH pin must be connected to the external regulator’s ENABLE pin. A pull-down resistor (typically 10-20k) is required on the INH pin. When the LAN8650/1 device is awake it will drive the INH pin high to VDDAU, enabling the external regulator. When the LAN8650/1 device goes to sleep, it makes the INH pin high impedance, pulling the output low through the pull-down resistor.
The ultra-low power mode on the LAN8650/1 is not a standby mode where the system remains fully powered-Sleep mode requires that the external regulator must disable power supply to all power supply except VDDAU.
If Low Power mode is not used, VDDAU should be connected to VDDA.
TABLE 9-1: POWER MANAGEMENT PINOUT

| LAN8650/1
---|---
INH| Pin 1
WAKE_IN| Pin 32
WAKE_OUT| Pin 24

• When INH is used, this pin requires a pull-down resistor (typically 10 kΩ – 20 kΩ).
• When INH is not used, this pin must be left unconnected.
• When WAKE_IN is not used, this pin must be connected to VSS.
• WAKE_ I N requires a pull-up to VDDAU or a pull-down to ground, depending on the configured wake input pulse polarity.
• When WAKE_OUT is used, this pin requires a pull-down resistor to ground.
• When WAKE_OUT is not used, this pin must be left unconnected.

CONFIGURABALE PINS

TABLE 10-1: CONFIGURABLE PINS PINOUT

| LAN8650/1
---|---
DIOA0| Pin 18
DIOA1| Pin 19
DIOA2| Pin 20
DIOA3| Pin 22
DIOA4| Pin 23
DIOB0| Pin 16
DIOB1| Pin 14

Note: When not used, these pins must be connected directly to ground. In this case, reserved registers must not  be written except by instruction from Microchip.

MISCELLANEOUS

11.1 RBIAS
TABLE 11-1: RBIAS PINOUT

| LAN8650/1
---|---
RBIAS| Pin 26

• The LAN8650/1 RBIAS pin requires the connection of an external 12.4 kΩ external biasing resistor to ground. This resistor must be within ± 1% tolerance over the entire expected operating temperature range.

11.2 TEST
TABLE 11-2: TEST PINOUT

| LAN8650/51
---|---
TEST| Pin 4

• This pin must be connected to VDDP.

11.3 DO NOT CONNECT
TABLE 11-3: DO NOT CONNECT PINOUT

| LAN8650| LAN8651
---|---|---
DNC| | Pin 6, Pin 15

• All DNC pins must not be connected and must remain floating, except when advised by Microchip.

HARDW ARE CHECKLIST SUMMAR Y

TABLE 12-1:HAR DW AR E DESIGN CH ECKLIST

APPENDIX A: REFERENCES

Documents listed below and referenced within this publication are current as of the release of this publication and may have been reissued with more current information.
To obtain information on Microchip documentation please submit a case through www.microchip.com/support.
All non-Microchip documentation should be retrieved from the applicable website locations listed below. Microchip is not responsible for the update, maintenance or distribution of non-Microchip documentation.
Because the Internet is a constantly changing environment, all Internet links mentioned below and throughout this document are subject to change without notice.

1. LAN8650/1 10BASE-T1S MAC-PHY Ethernet Controller With SPI Data Sheet
   DS60001734. Microchip. www.microchip.com/LAN8650.

2. LAN86xx Bus Interface Network (BIN) Reference Design Application Note
   DS60001718. Microchip. www.microchip.com/LAN8650.

3. LAN8650 and LAN8651 10BASE-T1S Single Pair Ethernet MAC-PHY
   LAN8650: Microchip. www.microchip.com/LAN8650.
   LAN8651: Microchip. www.microchip.com/LAN8651.

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DS60001746D
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091421b

Documents / Resources

| MICROCHIP LAN8650/1 Ethernet Switches [pdf] Instructions
LAN8650, LAN8651, LAN86501 Ethernet Switches, LAN86501, Ethernet Switches, Ethernet, Switches
---|---

References

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