MICROCHIP Pattern Generator IP User Guide

: October 30, 2023
: MICROCHIP

Table of Contents

Introduction
Revision History
Customer Support
Microchip Devices Code Protection Feature
Legal Notice
Trademarks
Quality Management System
References
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Download This Manual (PDF format)

MICROCHIP Pattern Generator IP User Guide

Introduction

The pattern generator IP generates the test patterns in RGB (red, green, and blue) video format, Bayer format, and can be used for troubleshooting and analyzing the video processing pipeline and display. The Bayer format generates video output in RAW format that is identical to a camera sensor output and hence can be used as a replacement for camera sensor to test video processing pipeline.

The test pattern IP generates following eight different types of video test patterns.

Color boxes pattern with 8 x 8 grid
Only red
Only green
Only blue
Horizontal eight color bars
Vertical eight color bars
Vertical graded bars from black to white
Horizontal graded bars from black to white

Figure 1. Top-Level Block Diagram of Pattern Generator

The pattern generator IP is configurable and can generate test patterns for any video resolution as per the configuration. The video resolution can be configured using the configuration parameters H Resolution and V Resolution. The input signal PATTERN_SEL_I defines the type of the video pattern to be generated. Below is the selection of pattern based on the pattern_sel_i input:

3’b000 – color boxes pattern
3’b001 – only red
3’b010 – only green
3’b011 – only blue
3’b100 – vertical eight color bars
3’b101 – horizontal eight color bars
3’b110 – horizontal graded bars from black to white
3’b111 – vertical graded bars from black to white

The pattern generator IP generates the patterns based on the input DATA_EN_I signal; if the DATA_EN_I signal is high, then the desired pattern is generated, else the output pattern is not generated. This pattern generator IP operates at the system clock SYS_CLK_I. The output of the pattern generator IP is 24-bit data which comprises of R, G, and B data of 8-bit each. The input signal FRAME_END_O is 2-stage flopped inside the pattern generator block to compensate for the latency of R, G, and B data and transmitted out as FRAME_END_O.

Hardware Implementation
The following figure shows the color bar pattern generated from the pattern generator. To generate the color bar pattern, a pattern generator counter is implemented. A horizontal counter is incremented when DATA_EN_I is high and reset to zero at the falling edge. A vertical counter is incremented at each falling edge of DATA_EN_I and is reset to zero at FRAME_END_I. The following figures show the eight patterns.

Figure 1-1. Color Boxes Pattern with 8 x 8 Grid
Figure 1-2. Only Red Pattern
Figure 1-3. Only Blue Pattern
Figure 1-4. Only Green Pattern
Figure 1-5. Horizontal Eight Color Bars
Figure 1-6. Vertical Eight Color Bars
Figure 1-7. Vertical Graded Bars from Black to White
Figure 1-8. Horizontal Graded Bars from Black to White

Inputs and Outputs
The following table shows the input and output ports of pattern generator.

Table 1-1. Inputs and Outputs of Pattern Conversion

Signal Name	Direction	Width	Description
RESET_N_I	Input	–	Active low asynchronous reset signal to design
SYS_CLK_I	Input	–	System clock
DATA_EN_I	Input	–	Data_enable signal that should have the valid period as

Configuration Parameters
The following table shows the configuration parameters used in the hardware implementation of pattern generator. These are generic parameters and can be varied based on the application requirements.

Table 1-2. Configuration Parameters

Signal Name	Description
H_RESOLUTION	Horizontal resolution
V_RESOLUTION	Vertical resolution
g_BAYER_FORMAT	Bayer format selection for RGGB, BGGR, GRBG, and GBRG

Testbench
A test bench has been provided to check the functionality of the pattern generator core.

Table 1-3. Testbench Configuration Parameters

Name	Description
CLKPERIOD	Clock Period

Resource Utilization
The following table lists the resource utilization of the pattern generator block implemented in the SmartFusion2 and PolarFire system-on-chip (SoC) FPGA device M2S150T-FBGA1152 package and PolarFire FPGA device MPF300TS_ES – 1FCG1152E package.

Table 1-4. Resource Utilization Report

Resource	Usage
DFFs	78
4-Input LUTs	240
MACC	0
RAM1Kx18	0
RAM64x18	0

Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Revision	Date	Description
A	03/2022	The following is the list of changes in revision A of the

document:• The document was migrated to the Microchip template.• The document number was updated to DS00004465A from 50200682.
1| 02/2016| Revision 1.0 was the first publication of this document.

Microchip FPGA Support

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From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 650.318.8044

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Customer Support

Users of Microchip products can receive assistance through several channels:

Distributor or Representative
Local Sales Office
Embedded Solutions Engineer (ESE)
Technical Support

Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in this document. Technical support is available through the website at: www.microchip.com/support

Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip products:

Microchip products meet the specifications contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions.
Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products.

Legal Notice

This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at www.microchip.com/enus/support/design-help/client-support- services.

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© 2022, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved.ISBN: 978-1-5224-9898-8

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