TQMa8MPxL Embedded Single Board Computer User Manual

: June 1, 2024
: TQ

Table of Contents

TQMa8MPxL Embedded Single Board Computer
Product Information
Product Usage Instructions
FAQs
REVISION HISTORY
ABOUT THIS MANUAL
BRIEF DESCRIPTION
ELECTRONICS
SOFTWARE
MECHANICS
SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS
ENVIRONMENT PROTECTION
APPENDIX
References
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TQMa8MPxL Embedded Single Board Computer

Product Information

Specifications

Model: TQMa8MPxL
Date: 06.05.2024
Manufacturer: TQ-Systems GmbH

Product Usage Instructions

About This Manual

This User’s Manual provides important information about the product and its proper usage. It includes details on copyright, license expenses, registered trademarks, and disclaimers.

Copyright and License Expenses

This User’s Manual is protected by copyright and may not be copied, reproduced, translated, changed, or distributed without written consent from TQ-Systems GmbH. The drivers, utilities, BIOS, and components used are subject to their respective manufacturers’ copyrights.

Registered Trademarks

TQ-Systems GmbH respects copyrights and aims to use original or license-free graphics and texts. All brand names and trademarks mentioned in this manual are protected by current copyright and proprietary laws.

Disclaimer

TQ-Systems GmbH reserves the right to change or add content to this User’s Manual without prior notification.

FAQs

Q: Can I make copies of this User’s Manual?
- A: No, this User’s Manual cannot be copied without written consent from TQ-Systems GmbH.
Q: Are license expenses for the operating system included in the price?
- A: No, license expenses for the operating system and applications are not included in the price and must be calculated separately.

TQMa8MPxL User’s Manual
TQMa8MPxL UM 0105 06.05.2024

REVISION HISTORY

Page v

Rev. 0100 0101 0102 0103 0104 0105

Date

Name

Pos.

23.03.2022 Kreuzer

22.11.2022 Kreuzer Table 3

30.05.2023 Kreuzer Chapter 3.1.1.1

20.03.2024 Kreuzer Chapter 3.2.5.20

11.04.2024 Kreuzer Table 3

06.05.2024 Kreuzer Table 27

Modification First issue V_SD2 corrected to Pout Number of pads corrected to 366 Chapter references corrected CPU ball assignments corrected Table expanded

Page 1

ABOUT THIS MANUAL

1.1

Copyright and license expenses

Copyright protected © 2024 by TQ-Systems GmbH.
This User’s Manual may not be copied, reproduced, translated, changed or distributed, completely or partially in electronic, machine readable, or in any other form without the written consent of TQ-Systems GmbH.
The drivers and utilities for the components used as well as the BIOS are subject to the copyrights of the respective manufacturers. The licence conditions of the respective manufacturer are to be adhered to.
Bootloader-licence expenses are paid by TQ-Systems GmbH and are included in the price.
Licence expenses for the operating system and applications are not taken into consideration and must be calculated / declared separately.

1.2

Registered trademarks

TQ-Systems GmbH aims to adhere to copyrights of all graphics and texts used in all publications, and strives to use original or license-free graphics and texts.
All brand names and trademarks mentioned in this User’s Manual, including those protected by a third party, unless specified otherwise in writing, are subjected to the specifications of the current copyright laws and the proprietary laws of the present registered proprietor without any limitation. One should conclude that brand and trademarks are rightly protected by a third party.

1.3

Disclaimer

TQ-Systems GmbH does not guarantee that the information in this User’s Manual is up-to-date, correct, complete or of good quality. Nor does TQ-Systems GmbH assume guarantee for further usage of the information. Liability claims against TQ-Systems GmbH, referring to material or non-material related damages caused, due to usage or non-usage of the information given in this User’s Manual, or due to usage of erroneous or incomplete information, are exempted, as long as there is no proven intentional or negligent fault of TQ-Systems GmbH.
TQ-Systems GmbH explicitly reserves the rights to change or add to the contents of this User’s Manual or parts of it without special notification.

Important Notice:
Before using the Starterkit MBa8MPxL or parts of the schematics of the MBa8MPxL, you must evaluate it and determine if it is suitable for your intended application. You assume all risks and liability associated with such use. TQ-Systems GmbH makes no other warranties including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. Except where prohibited by law, TQ-Systems GmbH will not be liable for any indirect, special, incidental or consequential loss or damage arising from the usage of the Starterkit MBa8MPxL or schematics used, regardless of the legal theory asserted.

1.4

Imprint

TQ-Systems GmbH Gut Delling, Mühlstraße 2 D-82229 Seefeld

Tel: Fax: E-Mail: Web:

+49 8153 93080 +49 8153 93084223 Info@TQ-Group TQ-Group

1.5

Tips on safety

Improper or incorrect handling of the product can substantially reduce its life span.

Page 2

1.6

Symbols and typographic conventions

Table 1: Terms and conventions

Symbol

Meaning

This symbol represents the handling of electrostatic-sensitive modules and / or components. These components are often damaged / destroyed by the transmission of a voltage higher than about 50 V. A human body usually only experiences electrostatic discharges above approximately 3,000 V.

This symbol indicates the possible use of voltages higher than 24 V.
Please note the relevant statutory regulations in this regard.
Non-compliance with these regulations can lead to serious damage to your health and may damage or destroy the component.

This symbol indicates a possible source of danger. Ignoring the instructions described can cause health damage, or damage the hardware.

This symbol represents important details or aspects for working with TQ- products.

Command

A font with fixed-width is used to denote commands, contents, file names, or menu items.

1.7

Handling and ESD tips

General handling of your TQ-products

The TQ-product may only be used and serviced by certified personnel who have taken note of the information, the safety regulations in this document and all related rules and regulations.
A general rule is not to touch the TQ-product during operation. This is especially important when switching on, changing jumper settings or connecting other devices without ensuring beforehand that the power supply of the system has been switched off.
Violation of this guideline may result in damage / destruction of the TQMa8MPxL and be dangerous to your health.
Improper handling of your TQ-product would render the guarantee invalid.

Proper ESD handling

The electronic components of your TQ-product are sensitive to electrostatic discharge (ESD).
Always wear antistatic clothing, use ESD-safe tools, packing materials etc., and operate your TQproduct in an ESD-safe environment. Especially when you switch modules on, change jumper settings, or connect other devices.

Page 3

1.8

Naming of signals

A hash mark (#) at the end of the signal name indicates a low-active signal. Example: RESET#

If a signal can switch between two functions and if this is noted in the name of the signal, the low-active function is marked with a hash mark and shown at the end.
Example: C / D#

If a signal has multiple functions, the individual functions are separated by slashes when they are important for the wiring. The identification of the individual functions follows the above conventions. Example: WE2# / OE#

1.9

Further applicable documents / presumed knowledge

· Specifications and manual of the modules used: These documents describe the service, functionality and special characteristics of the module used (incl. BIOS).
· Specifications of the components used: The manufacturer’s specifications of the components used, for example CompactFlash cards, are to be taken note of. They contain, if applicable, additional information that must be taken note of for safe and reliable operation. These documents are stored at TQ-Systems GmbH.
· Chip errata: It is the user’s responsibility to make sure all errata published by the manufacturer of each component are taken note of. The manufacturer’s advice should be followed.
· Software behaviour: No warranty can be given, nor responsibility taken for any unexpected software behaviour due to deficient components.
· General expertise: Expertise in electrical engineering / computer engineering is required for the installation and the use of the device.

The following documents are required to fully comprehend the following contents:

· MBa8MPxL circuit diagram · MBa8MPxL User’s Manual · i.MX 8M Plus Data Sheet · i.MX 8M Plus Reference Manual · U-Boot documentation: · PTXdist documentation: · Yocto documentation: · TQ-Support Wiki:

www.denx.de/wiki/U-Boot/Documentation www.ptxdist.de www.yoctoproject.org/docs/ Support-Wiki TQMa8MPxL

Page 4

BRIEF DESCRIPTION

This User’s Manual describes the hardware of the TQMa8MPxL as of revision 0100, in combination with the MBa8MPxL as of revision 0100 and refers to some software settings. A certain TQMa8MPxL derivative does not necessarily provide all features described in this User’s Manual.
This User’s Manual does neither replace the i.MX 8M Plus Reference Manual (1), nor the i.MX 8M Plus Data Sheet (2), nor any other documents from NXP.
The TQMa8MPxL is a universal Minimodule based on the NXP ARM® Cortex®-A53 based i.MX 8M CPU family, see also Table 4.

2.1

Key functions and characteristics

The TQMa8MPxL extends the TQ-Systems GmbH product range and offers an outstanding computing performance. All essential i.MX 8M Plus signals are routed to the TQMa8MPxL LGA pads. There are therefore no restrictions for customers using the TQMa8MPxL with respect to an integrated customised design. All essential components like CPU, LPDDR4, eMMC, and PMIC are already integrated on the TQMa8MPxL. The main features of the TQMa8MPxL are:
· 64 bit NXP i.MX 8M Plus CPU, up to 4 × ARM Cortex®-A53 and 1 × Cortex®-M7 o Plus Dual, Plus Quad 4 Lite, Plus Quad 6 Video, Plus Quad 8 ML/AI
· Up to 4 Gbyte 32-bit LPDDR4-4000 · Up to 256 Gbyte eMMC NAND Flash, eMMC standard 5.1 · Up to 256 Mbyte QSPI NOR Flash · 64 Kbit EEPROM (optional) · Temperature sensor + EEPROM · RTC (optinal) · Trust Secure Element (optional) · NXP Power Management Integrated Circuit PCA9450 · All essential i.MX 8M Plus signals are routed to the TQMa8MPxL LGA pads · Single supply voltage 5 V

2.2

CPU block diagram

Figure 1:

Block diagram i.MX 8M Plus (Source: NXP)

ELECTRONICS

The information provided in this User’s Manual is only valid in connection with the tailored boot loader, which is preinstalled on the TQMa8MPxL, and the BSP provided by TQ-Systems GmbH, see also chapter 4.

Page 5

PMIC NXP PCA9450C
Supervisor

i.MX 8M Plus

LPDDR4-RAM
e-MMC 5.1 (optional)
1x QSPI-NORFlash (optional)
RTC (optional) TSE (optional) EEPROM (option.)
Temperature Sensor / EEPROM

PCIe RGMII USB3.0 UART
I2C GPIO SPI HDMI CSI DSI

5 V
5 V

366 LGA pads Figure 2: Block diagram TQMa8MPxL (simplified)

3.1

Interfaces to other systems and devices

3.1.1

Pin multiplexing

The multiple pin configurations by different i.MX 8M Plus-internal function units must be taken note of. The pin assignment in Table 3 refers to a TQMa8MPxL with i.MX 8M Plus Quad 8 ML/AI CPU in combination with the carrier board MBa8MPxL. NXP provides a tool showing the multiplexing and simplifies the selection and configuration (i.MX Pins Tool NXP Tool). The electrical and pin characteristics are to be taken from the i.MX 8M Plus and PMIC documentation, see Table 40.

Attention: Destruction or malfunction, pin multiplexing
Depending on the configuration, many i.MX 8M Plus pins can provide several different functions. Please take note of the information concerning the configuration of these pins in the i.MX 8M Plus Reference Manual (1), before integration or start-up of your carrier board / Starterkit. Improper programming by operating software can cause malfunctions, deterioration or destruction of the TQMa8MPxL.
The descriptions given in the following tables should be taken note of: – DNC: These pins must never be connected and have to be left open.
Please contact TQ-Support for details.

Page 6

3.1.1.1 Pinout TQMa8MPxL The TQMa8MPxL has a total of 366 LGA pads. The TQMa8MPxL is soldered and thus permanently connected to the carrier board. It is not trivial and it is not recommended to remove the TQMa8MPxL. The following table shows the TQMa8MPxL pad-out, top view through the TQMa8MPxL.
Table 2: Pinout TQMa8MPxL, top view through TQMa8MPxL

A 22

B C D E F G H J K L M N P R T U V W Y AA AB

USB1 USB1 D_P D_N

GND

DSI DSI D1_N D1_P

GND

DSI DSI D3_N D3_P

GND

CSI1 CSI1 CLK_N CLK_P

GND

CSI2 CSI2 D0_N D0_P

GND

CSI2 CSI2 D2_N D2_P

GND

PCIE_RE PCIE_RE F_CLKN F_CLKP

22

21

USB1_ TX_N

GND

ISO_14 ISO_14 443_LB 443_LA

GND

DSI DSI CLK_N CLK_P

GND

CSI1_ D0_N

CSI1_ D0_P

GND

CSI1_ D2_N

CSI1_ D2_P

GND

CSI2_ D1_N

CSI2_ D1_P

GND

CSI2_ D3_N

CSI2_ D3_P

GND

PCIE_ TXN

PCIE_ TXP

21

20

USB1_ TX_P

USB1_ RX_N

GND

DSI_ D0_N

DSI_ D0_P

GND

DSI DSI D2_N D2_P

GND

CSI1 CSI1 D1_N D1_P

GND

CSI1 CSI1 D3_N D3_P

GND

CSI2 CSI2 CLK_N CLK_P

GND

PCIE_ RXN

PCIE_ RXP

LVDS1_ D3_P

GND

20

19 GND

USB1_ USB2 RX_P _D_N

USB2 GPIO1 USB1 _DNU _IO11 _DNU

GND

18

USB2_ TX_N

GND

USB2_ GPIO1 D_P _IO15

GND

USB1_ VBUS

USB1 _OTG _ID

USB1_ OTG _OC

ISO_78 16_CLK

GND

JTAG JTAG TDO TCK

GND

BOOT BOOT BOOT TEMP MODE3 MODE2 MODE1 EVENT#

M7_ NMI

USB1 OTG PWR

ISO_78 16_IO2

ISO_78 16_IO1

ISO_78 16_RST

GND

JTAG JTAG TMS TDI

GND

BOOT RTC MODE0 EVENT#

GND

V_SD1

LVDS1_ D3_N

LVDS1_ CLK_P

19

CLK1_ IN

GND

LVDS1_ D2_P

LVDS1_ CLK_N

18

17

USB2_ TX_P

USB2_ RX_N

GND

GPIO1 USB2_ _IO14 VBUS

CLK2_ OUT

CLK1_ LVDS1 LVDS1 OUT _D1_P _D2_N

GND

17

16 GND

USB2_ GPIO3 RX_P _IO14

GND

GPIO1 _IO00

15

VSAI2 SAI3_ SPDIF

VSAI1 SAI5

GND

V_ GPIO1 LICELL _IO01

14 GND

I2C4 I2C1 SCL SCL

GND

GPIO1 _IO03

GND

CLK2_ LVDS1 IN _D1_N

GND

LVDS1_ D0_P

16

QSPI_A QSPI_A _SS0# _SCLK

GND

LVDS0_ D3_P

LVDS1_ D0_N

15

QSPI_A _DATA0

GND

LVDS0 LVDS0 CLK_P D3_N

GND

14

13

SAI3_ TXD0

I2C4_ SDA

I2C2_ SCL

I2C1_ SDA

GND

QSPI_A QSPIA LVDS0 _DATA1 _DATA2 CLK_N

GND

LVDS0_ D2_P

13

12

SAI3_ RXD0

SAI3_ TXC

I2C2_ SDA

GND

GPIO1 _IO06

UART1 QSPI_A _RXD _DATA3

GND

LVDS0_ D1_P

LVDS0_ D2_N

12

11 GND

SAI3_ TXFS

GND

GPIO1 GPIO1 _IO09 _IO07

UART1 _TXD

GND

LVDS0 LVDS0 _D0_P _D1_N

GND 11

10

GPIO4 _IO29

GND

SAI3_ MCLK

PWM3

GND

I2C6_ SCL

I2C6_ SDA

LVDS0 _D0_N

ENET _QOS _TD3

V_ENET 10

9

GPIO4 _IO28

ENET_Q OS_EVE NT2_IN

GPIO4 _IO25

GND

GPIO5 GPIO5 _IO27 _IO26

RFU

GND

V_SD2

GPIO2 _IO07

UART2 UART2 _TXD _RXD

ENET _QOS _TD2

GND

ENET
_QOS 9 _TXC

8

ENET_QO GND S_EVENT GND
2_OUT

GPT2_ CLK

PMIC GND WDOG GND
OUT#

RFU

GND

GPIO2 UART3 _IO06 _RXD

ENET ENET GND QOS _QOS
TX_CTL _TD0

ENET _QOS 8 _TD1

7

GPIO4 _IO22

GND

GPIO4 _IO24

GND

RESET _IN#

RESET _OUT#

ONOFF

GND

SD2_ WP

SD2_ RST#

UART3 GPIO2 _TXD _IO11

ENET _QOS _RD3

GND

ENET
_QOS 7 _RXC

6

GPIO4 _IO27

GPIO4 _IO21

GND

PMIC _RST#

PMIC WDOG
IN#

UART4_ TXD

UART4_ RXD

ECSPI3_ MOSI

GND

GPIO5 GPIO5 _IO05 _IO03

GND

ECSPI2 SD2_ _SS0 CD#

GND

SD2_ CMD

GPIO2 _IO10

GND

ENET ENET QOS _QOS MDIO _RD2

GND 6

5 GND

GND

V_3V3 ECSPI3 ECSPI3 ECSPI3 GPIO5 ECSPI2 ECSPI2 ECSPI2 _SD _SS0 _MISO _SCLK _IO04 _SCLK _MISO _MOSI

GND

SD2_ DATA3

SD2_ DATA2

SD2_ DATA1

SD2_ DATA0

ENET QOS MDC

GND

ENET
_QOS 5 _RD1

4

V_5V _IN

V_5V V_5V _IN _IN

GND

ENET0 ENET1 _INT# _INT#

GND

ENET0 ENET1 _RST# _RST#

GND

GPIO4 ENET ENET SD2_ _IO18 RX_CTL TX_CTL CLK

GND

EARC HDMI AUX CEC

GND

ENET ENET QOS _QOS RX_CTL _RD0

4

3

V_5V _IN

V_5V V_5V _IN _IN

GND

ENET ENET _MDC _MDIO

GND

ENET ENET _RD2 _RD3

GND

ENET ENET _TD2 _TD3

GND

HDMI HDMI TXC_N TXC_P

GND

HDMI_ HPD

GND

HDMI
DDC 3 SCL

2

GPIO3 _IO20

GND

GPIO3 GPIO3 _IO21 _IO19

GND

GPIO5 GPIO5 _IO09 _IO08

GND

ENET _RD0

ENET _RD1

GND

ENET _TD0

ENET _TD1

GND

ENET _TXC

GPIO4 _IO19

GND

HDMI_ TX0_N

HDMI_ TX0_P

HDMI_ TX2_N

HDMI_ TX2_P

HDMI DDC SDA

2

1

CAN_F CAN_F CAN_F CAN_F D1_TX D1_RX D2_TX D2_RX

GND

GPIO5 GPIO5 _IO07 _IO06

GND

ENET _RXC

GPIO4 _IO20

GND

V_1V8 V_3V3

GND

EARC_N EARC_P _HPD _UTIL

GND

HDMI HDMI TX1_N TX1_P

GND

1

A B C D E F G H J K L M N P R T U V W Y AA AB

Page 7

3.1.1.2 TQMa8MPxL signals
Details about the electrical characteristics of single pins and interfaces are to be taken from the i.MX 8M Plus documentation (1), (2), (3), as well as the PMIC Data Sheet (4).

Table 3:
CPU-Ball
G10 F8 G8 G12 AF16 AD16 AF14 AE14 K28 K29 L28 L29 E22 D22 E18 D18 E20 D20 E24 D24 E26 D26 B23 A23 B25 A25 B24 A24 B22 A22 B21 A21 B18 A18 B16 A16 B17 A17 B19 A19 B20 A20

TQMa8MPxL, signals
Signal
BOOT_MODE0 BOOT_MODE1 BOOT_MODE2 BOOT_MODE3 CAN_FD1_RX CAN_FD1_TX CAN_FD2_RX CAN_FD2_TX CLK1_IN CLK1_OUT CLK2_IN CLK2_OUT CSI1_CLK_N CSI1_CLK_P CSI1_D0_N CSI1_D0_P CSI1_D1_N CSI1_D1_P CSI1_D2_N CSI1_D2_P CSI1_D3_N CSI1_D3_P CSI2_CLK_N CSI2_CLK_P CSI2_D0_N CSI2_D0_P CSI2_D1_N CSI2_D1_P CSI2_D2_N CSI2_D2_P CSI2_D3_N CSI2_D3_P DSI_CLK_N DSI_CLK_P DSI_D0_N DSI_D0_P DSI_D1_N DSI_D1_P DSI_D2_N DSI_D2_P DSI_D3_N DSI_D3_P

Group
BOOT BOOT BOOT BOOT CAN CAN CAN CAN CLK CLK CLK CLK
CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI DSI DSI DSI DSI DSI DSI DSI DSI DSI DSI

Dir.

Level

TQMa8MPxL-Pad

I

3.3 V

T18

I

3.3 V

T19

I

3.3 V

R19

I

3.3 V

P19

I

V_SAI1_SAI5

C1

O

V_SAI1_SAI5

B1

I

V_SAI1_SAI5

E1

O

V_SAI1_SAI5

D1

I

1.8 V

W18

O

1.8 V

W17

I

1.8 V

W16

O

1.8 V

V17

I

1.8 V

L22

I

1.8 V

M22

I

1.8 V

J21

I

1.8 V

K21

I

1.8 V

K20

I

1.8 V

L20

I

1.8 V

M21

I

1.8 V

N21

I

1.8 V

N20

I

1.8 V

P20

I

1.8 V

T20

I

1.8 V

U20

I

1.8 V

P22

I

1.8 V

R22

I

1.8 V

R21

I

1.8 V

T21

I

1.8 V

U22

I

1.8 V

V22

I

1.8 V

V21

I

1.8 V

W21

O

1.8 V

F21

O

1.8 V

G21

O

1.8 V

D20

O

1.8 V

E20

O

1.8 V

E22

O

1.8 V

F22

O

1.8 V

G20

O

1.8 V

H20

O

1.8 V

H22

O

1.8 V

J22

3.1.1.2 TQMa8MPxL signals (continued)

Table 3:
CPU AH20 AJ21 AH21 AJ22 AF6 AJ3 AD6 AH4 AJ9 AH8 AC10 AF10 AH9 AJ8 AH28 AH29 AG29 AG28 AF29 AF28 AE28 AE29 AC25 AE26 AF26 AD24 AF24 AE24 AJ14
AH16 AD10 AE10 AH10 AH12 AF12 AJ12 AJ11 AJ10 AH11 AD12 AE12 AH13 AH14
B4 –

TQMa8MPxL, signals (continued)
Signal ECSPI2_MISO ECSPI2_MOSI ECSPI2_SCLK ECSPI2_SS0 ECSPI3_MISO ECSPI3_MOSI ECSPI3_SCLK ECSPI3_SS0 ENET0_RST# ENET0_INT# ENET1_RST# ENET1_INT# ENET_MDC ENET_MDIO ENET_QOS_MDC ENET_QOS_MDIO ENET_QOS_RD0 ENET_QOS_RD1 ENET_QOS_RD2 ENET_QOS_RD3 ENET_QOS_RX_CTL ENET_QOS_RXC ENET_QOS_TD0 ENET_QOS_TD1 ENET_QOS_TD2 ENET_QOS_TD3 ENET_QOS_TX_CTL ENET_QOS_TXC ENET_QOS_EVENT2_OUT
ENET_QOS_EVENT2_IN ENET_RD0 ENET_RD1 ENET_RD2 ENET_RD3 ENET_RX_CTL ENET_RXC ENET_TD0 ENET_TD1 ENET_TD2 ENET_TD3 ENET_TX_CLK ENET_TX_CTL ENET_TXC M7_NMI RTC_EVENT# TEMP_EVENT#

Group
ECSPI ECSPI ECSPI ECSPI ECSPI ECSPI ECSPI ECSPI ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET
ENET
ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET ENET Event Event Event

Dir.

Level

I

1.8 V

O

1.8 V

O

1.8 V

O

1.8 V

I

3.3 V

O

3.3 V

O

3.3 V

O

3.3 V

O

V_SAI1_SAI5

I

V_SAI1_SAI5

O

V_SAI1_SAI5

I

V_SAI1_SAI5

O

V_SAI1_SAI5

I/O

V_SAI1_SAI5

O

V_ENET

I/O

V_ENET

I

V_ENET

I

V_ENET

I

V_ENET

I

V_ENET

I

V_ENET

I

V_ENET

O

V_ENET

O

V_ENET

O

V_ENET

O

V_ENET

O

V_ENET

O

V_ENET

O

V_SAI2_SAI3_SPDIF

I

V_SAI2_SAI3_SPDIF

I

V_SAI1_SAI5

I

V_SAI1_SAI5

I

V_SAI1_SAI5

I

V_SAI1_SAI5

I

V_SAI1_SAI5

I

V_SAI1_SAI5

O

V_SAI1_SAI5

O

V_SAI1_SAI5

O

V_SAI1_SAI5

O

V_SAI1_SAI5

O

V_SAI1_SAI5

O

V_SAI1_SAI5

O

V_SAI1_SAI5

I

3.3 V

O

OD

O

OD

Page 8
TQMa8MPxL N5 P5 M5 P6 J5 J6 K5 H5 K4 G4 L4 H4 H3 J3 Y5 Y6 AB4 AB5 AA6 Y7 AA4 AB7 AA8 AB8 Y9
AA10 Y8 AB9 B8 B9 J2 K2 L3 M3 P4 K1 M2 N2 P3 R3 L1 R4 R2 V19 U18 U19

3.1.1.2 TQMa8MPxL signals (continued)

Table 3:
CPU A7 E8 D6 A3 F6 B8 D8 A4 B5 U26
AA29
W25
W26 R26 AC14 AD14 AE16 AC12 AJ13 AH17
AJ16
AJ17
AH15
AJ15
AJ19
AJ18
AE18
AD18
AC18 AF20 AC20 AD20 AE20 AJ4 AE6 AJ7 AH23 AH22 AJ23 AD22 AC22 AF22 AE22 AJ25 AH25 AJ26

TQMa8MPxL, signals (continued)
Signal GPIO1_IO00 GPIO1_IO01 GPIO1_IO03 GPIO1_IO06 GPIO1_IO07 GPIO1_IO09 GPIO1_IO11 GPIO1_IO14 GPIO1_IO15 GPIO2_IO06
GPIO2_IO07
GPIO2_IO10
GPIO2_IO11 GPIO3_IO14 GPIO3_IO19 GPIO3_IO20 GPIO3_IO21 GPIO4_IO18 GPIO4_IO19 GPIO4_IO21
GPIO4_IO22
GPIO4_IO24
GPIO4_IO25
GPIO4_IO27
GPIO4_IO28
GPIO4_IO29
GPIO5_IO03
GPIO5_IO04
GPIO5_IO05 GPIO5_IO06 GPIO5_IO07 GPIO5_IO08 GPIO5_IO09 GPIO5_IO27 GPIO5_IO26 GPT2_CLK EARC_AUX EARC_N_HPD EARC_P_UTIL HDMI_CEC HDMI_DDC_SCL HDMI_DDC_SDA HDMI_HPD HDMI_TX0_N HDMI_TX0_P HDMI_TX1_N

Group GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
GPIO
GPIO
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPT HDMI HDMI HDMI HDMI HDMI HDMI HDMI HDMI HDMI HDMI

Dir.

Level

I/O

3.3 V

I/O

3.3 V

I/O

3.3 V

I/O

3.3 V

I/O

3.3 V

I/O

3.3 V

I/O

3.3 V

I/O

3.3 V

I/O

3.3 V

I/O

V_SD1

I/O

V_SD1

I/O

V_SD1

I/O

V_SD1

I/O

1.8 V

I/O

V_SAI1_SAI5

I/O

V_SAI1_SAI5

I/O

V_SAI1_SAI5

I/O

V_SAI1_SAI5

I/O

V_SAI1_SAI5

I/O V_SAI2_SAI3_SPDIF

I/O

1.8 V

I/O

1.8 V

I

1.8 V

O

1.8 V

I/O

3.3 V

I/O

3.3 V

I/O

3.3 V

O

1.8 V

I

1.8 V

O

1.8 V

O

1.8 V

O

1.8 V

I/O

1.8 V

I

1.8 V

O

1.8 V

O

1.8 V

O

1.8 V

Page 9
TQMa8MPxL E16 E15 E14 E12 E11 D11 E19 D17 D18 U8 U9 V6 W7 C16 D2 A2 C2 N4 T2 B6 A7 C7 C9 A6 A9 A10 M6 L5 L6 H1 G1 G2 F2 E9 F9 D8 V4 T1 U1 W4 AB3 AB2 Y3 V2 W2 W1

3.1.1.2 TQMa8MPxL signals (continued)

Table 3: TQMa8MPxL, signals (continued)

CPU
AH26 AJ27 AH27 AJ24 AH24 AC8 AH7 AH6 AE8 AF8 AD8 Y29 Y28
G18 G16 F14 G14 G28 F29 E28 D29 F28 E29 H28 G29 J28 H29 B28 A28 B26 A26 B27 A27 C28 B29 D28 C29

Signal
HDMI_TX1_P HDMI_TX2_N HDMI_TX2_P HDMI_TXC_N HDMI_TXC_P I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA I2C4_SCL I2C4_SDA I2C6_SCL I2C6_SDA ISO_7816_CLK ISO_7816_IO1 ISO_7816_IO2 ISO_7816_RST ISO_14443_LA ISO_14443_LB JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS LVDS0_CLK_N LVDS0_CLK_P LVDS0_D0_N LVDS0_D0_P LVDS0_D1_N LVDS0_D1_P LVDS0_D2_N LVDS0_D2_P LVDS0_D3_N LVDS0_D3_P LVDS1_CLK_N LVDS1_CLK_P LVDS1_D0_N LVDS1_D0_P LVDS1_D1_N LVDS1_D1_P LVDS1_D2_N LVDS1_D2_P LVDS1_D3_N LVDS1_D3_P

Group

Dir.

HDMI

O

HDMI

O

HDMI

O

HDMI

O

HDMI

O

I2C

O

I2C

I/O

I2C

O

I2C

I/O

I2C

O

I2C

I/O

I2C

O

I2C

I/O

ISO_7816

I

ISO_7816

I/O

ISO_7816

I/O

ISO_7816

I

ISO_14443

I/O

ISO_14443

I/O

JTAG

I

JTAG

I

JTAG

O

JTAG

I

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

LVDS

O

Level
1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V V_SD1 V_SD1 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V

Page 10
TQMa8MPxL Y1 Y2 AA2 U3 V3 C14 D13 C13 C12 B14 B13 V10 W10 J19 K18 J18 L18 D21 C21 M19 P18 L19 N18 Y13 Y14 Y10 Y11
AA11 AA12 AB12 AB13 AA14 AA15 AB18 AB19 AB15 AB16 Y16 Y17 AA17 AA18 AA19 AA20

3.1.1.2 TQMa8MPxL signals (continued)

Table 3:
CPU E16 D16 B14 A14 B15 A15 AJ6 R25 L25 L24 N24 N25 L26
B6 AJ20 AF18 AC16 AH19 AH18 AD29 AB29 AB28 AC28 AC29 AA26 AA25 AD28 AC26

TQMa8MPxL, signals (continued)
Signal PCIE_REF_CLKN PCIE_REF_CLKP PCIE_RXN PCIE_RXP PCIE_TXN PCIE_TXP PWM3 QSPI_A_DATA0 QSPI_A_DATA1 QSPI_A_DATA2 QSPI_A_DATA3 QSPI_A_SCLK QSPI_A_SS0# PMIC_RST# PMIC_WDOG_IN# PMIC_WDOG_OUT# RESET_IN# RESET_OUT# SAI3_MCLK SAI3_RXD0 SAI3_TXFS SAI3_TXC SAI3_TXD0 SD2_CD# SD2_CLK SD2_CMD SD2_DATA0 SD2_DATA1 SD2_DATA2 SD2_DATA3 SD2_RST# SD2_WP

Group PCIe PCIe PCIe PCIe PCIe PCIe PWM QSPI QSPI QSPI QSPI QSPI QSPI Reset Reset Reset Reset Reset SAI SAI SAI SAI SAI SD SD SD SD SD SD SD SD SD

Dir.

Level

I/O

1.8 V

I/O

1.8 V

I

1.8 V

I

1.8 V

O

1.8 V

O

1.8 V

O

3.3 V

I/O

1.8 V

I/O

1.8 V

I/O

1.8 V

I/O

1.8 V

O

1.8 V

O

1.8 V

I

1.8 V

I

3.3 V

O

3.3 V

I

OD

O

OD

O

V_SAI2_SAI3_SPDIF

I

V_SAI2_SAI3_SPDIF

O

V_SAI2_SAI3_SPDIF

O

V_SAI2_SAI3_SPDIF

O

V_SAI2_SAI3_SPDIF

I

1.8/ 3.3 V

O

1.8/ 3.3 V

I/O

1.8/ 3.3 V

I/O

1.8/ 3.3 V

I/O

1.8/ 3.3 V

I/O

1.8/ 3.3 V

I/O

1.8/ 3.3 V

O

1.8/ 3.3 V

I

1.8/ 3.3 V

Page 11
TQMa8MPxL Y22 AA22 W20 Y20 AA21 AB21 D10 V14 V13 W13 W12 W15 V15 E6 F6 F8 E7 F7 C10 A12 B11 B12 A13 R6 T4 U6 W5 V5 U5 T5 U7 T7

Page 12

3.1.1.2 TQMa8MPxL signals (continued)

Table 3:
CPU G22 W29 W28 V28 V29 U25 AA28 AJ5 AH5 E10 D10 B11 B7 A6 A5 B9 A9 B10 A10 A11 E14 D14 E12 B12 A12 B13 A13 D12

AA24 Y11 AA11 U24 –

TQMa8MPxL, signals (continued)

ONOFF

Signal

Group

Dir.

SNVS

I

Level 1.8 V

TQMa8MPxL G7

UART1_RXD

UART

I

V_SD1

V12

UART1_TXD UART2_RXD UART2_TXD UART3_RXD UART3_TXD

UART

O

V_SD1

V11

UART

I

V_SD1

W9

UART

O

V_SD1

V9

UART

I

V_SD1

V8

UART

O

V_SD1

V7

UART4_RXD

UART

I

3.3 V

H6

UART4_TXD USB1_D_N USB1_D_P USB1_DNU USB1_OTG_ID USB1_OTG_OC USB1_OTG_PWR USB1_RX_N USB1_RX_P USB1_TX_N USB1_TX_P USB1_VBUS USB2_D_N USB2_D_P USB2_DNU USB2_RX_N USB2_RX_P USB2_TX_N USB2_TX_P USB2_VBUS
GND
V_1V8 V_3V3 V_3V3_SD V_5V_IN V_ENET V_LICELL V_SAI1_SAI5 V_SAI2_SAI3_SPDIF V_SD1 V_SD2 RFU

UART

O

3.3 V

G6

USB

I/O

3.3 V

C22

USB

I/O

3.3 V

B22

USB

3.3 V

F19

USB

I

3.3 V

G18

USB

I

3.3 V

H19

USB

O

3.3 V

H18

USB

I

3.3 V

B20

USB

I

3.3 V

B19

USB

O

3.3 V

A21

USB

O

3.3 V

A20

USB

P

5 V

F18

USB

I/O

3.3 V

C19

USB

I/O

3.3 V

C18

USB

3.3 V

D19

USB

I

3.3 V

B17

USB

I

3.3 V

B16

USB

O

3.3 V

A18

USB

O

3.3 V

A17

USB

P

5 V

E17

A11, A14, A16, A19, A5, A8, AA1, AA13, AA16, AA3, AA5, AA7, AA9, AB11, AB14, AB17, AB20, AB6, B10, B18, B2, B21, B5, B7, C11, C15, C17, C20, C5, C6, C8, D12, D14, D16, D22, D3, D4, D5, D6, D7, D9, E10, E13, E18, E2, E21, E3, E4, E5, E8, F1, F20, F3, F4, F5, G19, G22, G3, G8, H2, H21, H7, H9, J1, J20, J4, K19, K22, K3, K6, L2, L21, M1, M18, M20, M4, N19, N22, N3, N6, P2, P21, R1, R18, R20, R5, R7, R9, T22, T3, T6, T8, U2, U21, U4, V1, V16, V18, V20, W11, W14, W19, W22, W3, W6, W8, Y12, Y15, Y18, Y21, Y4

Power

Pout

1.8 V 1

Power

Pout

3.3 V 1

Power

Pout

3.3 V 2

Power

5 V

Power

1.8 / 3.3 V

Power

3 V

Power

1.8 / 3.3 V

Power

1.8 / 3.3 V

Power

1.8 / 3.3 V

Power

Pout

1.8 / 3.3 V

Reserved for future use. Do not connect.

N1 P1 G5 A3, A4, B3, B4, C3, C4 AB10 D15 B15 A15 Y19 T9 G9, H8, R8

1: Maximum load of 500 mA. 2: Maximum load of 400 mA.

Page 13

3.2

System components

3.2.1

i.MX 8M Plus

3.2.1.1 i.MX 8M Plus derivatives

Depending on the TQMa8MPxL version, one of the following i.MX 8M Plus derivatives is assembled.

Table 4: i.MX 8M Plus derivatives

TQMa8MPxL version TQMa8MPDL-XX TQMa8MPQLL-AA TQMa8MPQL-AA TQMa8MPQL-AB

i.MX 8M Plus derivative i.MX 8M Plus Dual i.MX 8M Plus Quad 4 Lite i.MX 8M Plus Quad 6 Video i.MX 8M Plus Quad 8 ML/AI

i.MX 8M Plus clocks A53: 1.6 GHz, M7: 800 MHz A53: 1.6 GHz, M7: 800 MHz A53: 1.6 GHz, M7: 800 MHz A53: 1.6 GHz, M7: 800 MHz

Temperature range 40 °C … +105 °C 40 °C … +105 °C 40 °C … +105 °C 40 °C … +105 °C

3.2.1.2 i.MX 8M Plus errata Attention: Destruction or malfunction, i.MX 8M Plus errata

Please take note of the current i.MX 8M Plus errata (5).

3.2.1.3 Boot modes
The i.MX 8M Plus has a ROM with integrated boot loader. After the release of PMIC_POR# the System Controller (SCU) boots from the internal ROM and then loads the program image from the selected boot device. For example, the integrated eMMC or the optional QSPI NOR Flash can be selected as the default boot device. The following boot sources are supported by TQMa8MPxL:
· eMMC · QSPI NOR Flash · USB OTG · SD card
Alternatively, an image can be loaded into the internal RAM using the serial downloader. More information about the boot flow can be found in the Reference Manual (1), and the Data Sheet (2) of i.MX 8M Plus.

3.2.1.4 Boot configuration
The i.MX 8M Plus uses four BOOT_MODE signals available on the TQMa8MPxL’s LGA pads. These require pull-up/pull-down wiring to 3.3 V and Ground. The exact boot behaviour depends on the BT_FUSE_SEL register value. Booting from USDHC1 is only possible on the i.MX 8M Plus after burning the eFuses. The following table shows the behaviour in dependence of BT_FUSE_SEL and selected boot mode:

Table 5: Boot configuration i.MX 8M Plus

Boot source
Boot from eFuse USB Serial Downloader Boot from USDHC3 (eMMC) Boot from USDHC2 (SD card) Boot from NAND (not supported) Boot from QSPI (3 Byte Read) Boot from QSPI (Hyperflash) (not supported) Boot from eCSPI (not supported) (Reserved)

BOOT_MODE3 0 0 0 0 0 0
0
1 1

BOOT_MODE2 0 0 0 0 1 1
1
0 0

BOOT_MODE1 0 0 1 1 0 1
1
0 0

BOOT_MODE0 0 1 0 1 x 0
1
0 1

Page 14

3.2.2

Memory

3.2.2.1 LPDDR4 SDRAM

The memory interface of the i.MX 8M Plus supports DDR4 and LPDDR4 memory (32 bit bus) with a maximum clock rate of 2.0 GHz, which meets JEDEC LPDDR4-4000 standard. The TQMa8MPxL exclusively uses LPDDR4. A maximum of 8 Gbyte of LPDDR4 SDRAM is supported.

3.2.2.2 eMMC
An eMMC is provided on the TQMa8MPxL for boot loader, operating system and application software. It is connected to the i.MX 8M Plus via USDHC3.

1,8 V 3,3 V
i.MX8M Plus NAND_WE# NAND_WP#
NAND_DATA[7;4] NAND_RE#
NAND_CE2# NAND_CE3#
NAND_CLE NAND_READY#
NAND_CE1#

e-MMC 5.1
VCC VCCQ
CLK CMD DATA[3:0] DATA4 DATA5 DATA6 DATA7 RST# STROBE

Figure 3: Block diagram eMMC
The i.MX 8M Plus supports transfer modes up to the current eMMC standard v5.1 according to JESD84-B51. In DDR mode (HS400) data rates of up to 400 Mbyte/s can be achieved. The boot configuration is described in chapter 3.2.1.3

3.2.2.3 QSPI NOR Flash
QSPI NOR flash can optionally be assembled on the TQMa8MPxL. If no QSPI NOR Flash is populated on the TQMa8MPxL, the LGA pads of the interface can be used. Since it is not possible to separate the signal paths, these LGA pads must not be wired when the NOR Flash is equipped.

3.2.2.4 EEPROM 24LC64T
A serial EEPROM, controlled by the I2C1 bus, is assembled. Write-Protection (WP) is not supported. A 64 Kbit EEPROM 24LC64T is assembled by default on the TQMa8MPxL.

i.MX 8M Plus
I2C1_SCL I2C1_SDA

EEPROM
SCL SDA

Figure 4: Block diagram EEPROM The EEPROM has I2C address 0x57 / 101 0111b

Page 15

3.2.2.5 EEPROM with temperature sensor SE97BTP
A serial EEPROM including temperature sensor type SE97BTP, controlled by the I2C1 bus, is assembled on the TQMa8MPxL. The lower 128 bytes (address 00h to 7Fh) can be set to Permanent Write-Protected mode (PWP) or to Reversible Write-Protected mode (RWP) by software. The upper 128 bytes (address 80h to FFh) cannot be write-protected and are available for general data storage. The overtemperature output of the SE97BTP is connected as open drain to TQMa8MPxL LGA pad U19 (TEMP_EVENT#). This requires a pull-up to 3.3 V (maximum 5.5 V) on the carrier board. The device is assembled on the top side of the TQMa8MPxL, see component D12, Figure 22.

The device provides the following I2C addresses:

o EEPROM (Normal Mode): o EEPROM (Protection Mode): o Temperature sensor:

0x53 / 101 0011b 0x33 / 011 0011b 0x1B / 001 1011b

3.2.3

Trust Secure Element SE050

An NXP Trust Secure Element SE050 is available on the TQMa8MPxL as an assembly option. When equipped, the chip provides two interfaces according to ISO 7816 and ISO 14443. Among other things, antennas can be connected to these.

i.MX 8M Plus
I2C1_SCL I2C1_SDA

SE050
I2C_SCL I2C_SDA
ISO_7816_IO1 ISO_7816_IO2 ISO_7816_CLK ISO_7816_RST
ISO_14443_LA ISO_14443_LB

LGA pads
V_3V3_IN
ISO_7816_IO1 ISO_7816_IO2 ISO_7816_CLK ISO_7816_RST
ISO_14443_LA ISO_14443_LB

The SE050 is controlled by the I2C1 bus. More details can be found in (8). The Trust Secure Element has I2C address 0x48 / 100 1000b

3.2.4

RTC

The TQMa8MPxL provides an i.MX 8M Plus-internal RTC or a discrete RTC PCF85063A.

3.2.4.1 i.MX 8M Plus internal RTC
The i.MX 8M Plus provides an RTC, which has its own power domain (V_1V8_SNVS). The RTC power domain SNVS of the i.MX 8M Plus is supplied by the PMIC. The PMIC is supplied by the TQMa8MPxL input voltage of V_5V_IN. The quartz used to clock the RTC has a standard frequency tolerance of ±20 ppm @ +25 °C.

5 V

LGA pads

V_5V_IN

PMIC PCA9450

INL1

LDO1

i.MX 8M Plus
VDD_SNVS_1P8

Figure 5: Block diagram RTC supply (TQMa8MPxL without discrete RTC)

Page 16

Note: RTC power supply
The CPU internal RTC can be used in regular operation. If the TQMa8MPxL supply (5 V) fails, it is no longer available, since the i.MX 8M Plus’s SNVS rail is no longer supplied.

3.2.4.2 Discrete RTC PCF85063A
In addition to the i.MX 8M Plus internal RTC the TQMa8MPxL provides a discrete RTC PCF85063A as an assembly option, which is controlled by the I2C1 bus. The quartz used to clock the RTC has a standard frequency tolerance of ±20 ppm @ +25 °C. The discrete RTC has an interrupt output which provides the open-drain signal RTC_EVENT# at LGA pad U18. This pin requires a pull-up to 3.3 V (maximum 3.6 V) on the carrier board. The RTC PCF85063A is only directly supplied by V_LICELL when the PMIC or the TQMa8MPxL supply is switched off. During normal operation of the TQMa8MPxL, the PMIC supplies 3.3 V.

Power supply

Protection

LGA pads
V_5V_IN

PMIC
INL1 BUCK4

Coin Cell (typ. 3 V)

Protection

V_LICELL

PCF85063A
VDD

Figure 6: Block diagram RTC supply (TQMa8MPxL with discrete RTC) The discrete RTC has I2C address 0x51 / 101 0001b

Note: RTC power supply
The SNVS functions of the i.MX 8M Plus can only be used if the TQMa8MPxL is supplied with 5 V. Since the SNVS rail is not supplied when the TQMa8MPxL is not powered-up, we recommend using the optional RTC PCF85063A.

3.2.5

Interfaces

3.2.5.1 Overview

The following interfaces or signals are not available on the TQMa8MPxL LGA pads and are used on the TQMa8MPxL. Table 6: TQMa8MPxL-internal interfaces

Interface USDHC3 SDRAM GPIO1_IO04 / SD2_VSELECT GPIO1_IO08 / IRQ# POR# PMIC_ON_REQ PMIC_STBY_REQ RTC_XTALO

Chapter 3.2.2.2 3.2.2.1 3.2.5.20

Remark eMMC, 8 bit LPDDR4, 32 bit 100 k PU on TQMa8MPxL 100 k PU on TQMa8MPxL, signal from CPU to PMIC Signal from CPU to PMIC Signal from CPU to PMIC 100 k PU on TQMa8MPxL

Page 17

3.2.5.2 CAN FD
The i.MX 8M Plus provides two CAN FD interfaces, CAN FD1 and CAN FD2. Both are multiplexed to SAI5 pins in the standard configuration and specified according to the CAN 2.0B protocol. The supply voltage is set via TQMa8MPxL LGA pad V_SAI1_SAI5.

Table 7: CAN FD signals
Signal CAN_FD1_TX CAN_FD1_RX CAN_FD2_TX CAN_FD2_RX

i.MX 8M Plus AD16 AF16 AE14 AF14

TQMa8MPxL B1 C1 D1 E1

Power group V_SAI1_SAI5

3.2.5.3 PWM The i.MX 8M Plus provides up to four PWM signals which can be multipexed via various pins. In the default configuration one PWM signal (PWM3) is provided at the TQMa8MPxL LGA pad D10.
3.2.5.4 GPT The i.MX 8M Plus provides up to three General Purpose Timers (GPT). These always use a part of the UART res. I2C pins of the CPU. Therefore only the GPT2 interface (GPT2_CLK) is provided by the TQMa8MPxL pad D8.

Page 18

3.2.5.5 Ethernet
The i.MX 8M Plus provides two Gigabit Ethernet interfaces, which support transfer rates of 10/100 and 1000 Mbps as well as fulland half-duplex. By default the ENET interface is configured as RGMII. The second Ethernet interface is provided at the SAI1 pins. The supply voltage must be set externally to 1.8 V or 3.3 V, with LGA pads V_ENET and V_SAI1_SAI5, see also chapter 3.2.8.6. The differential signals are length matched on the TQMa8MPxL and routed with a differential impedance of 100 . On the carrier board they have to be connected according to RGMII specifications.

The following table shows the signals used in RGMII mode.

Table 8: ENET signals in RGMII mode

Signal
ENET_QOS_RX_CTL ENET_QOS_RXC ENET_QOS_RD0 ENET_QOS_RD1 ENET_QOS_RD2 ENET_QOS_RD3 ENET_QOS_TX_CTL ENET_QOS_TXC ENET_QOS_TD0 ENET_QOS_TD1 ENET_QOS_TD2 ENET_QOS_TD3 ENET_QOS_MDC ENET_QOS_MDIO ENET_QOS_EVENT2_OUT ENET_QOS_EVENT2_IN ENET1_RST# ENET1_INT# ENET0_RST# ENET0_INT# ENET_MDC ENET_MDIO ENET_RD0 ENET_RD1 ENET_RD2 ENET_RD3 ENET_RXC ENET_TD0 ENET_TD1 ENET_TD2 ENET_TD3 ENET_TX_CTL ENET_TXC ENET_RX_CTL

Ethernet
ENET1 ENET1 ENET1 ENET1 ENET1 ENET1 ENET1 ENET1 ENET1 ENET1 ENET1 ENET1 ENET1 ENET1 ENET1 ENET1 ENET1 ENET1 ENET0 ENET0 ENET0 ENET0 ENET0 ENET0 ENET0 ENET0 ENET0 ENET0 ENET0 ENET0 ENET0 ENET0 ENET0 ENET0

Direction
I I I I I I O O O O O O O I/O O I O O O I O I/O I I I I I O O O O O O I

i.MX 8M Plus
AE28 AE29 AG29 AG28 AF29 AF28 AF24 AE24 AC25 AE26 AF26 AD24 AH28 AH29 AJ14 AH16 AC10 AF10 AJ9 AH8 AH9 AJ8 AD10 AE10 AH10 AH12 AJ12 AJ11 AJ10 AH11 AD12 AH13 AH14 AF12

TQMa8MPxL
AA4 AB7 AB4 AB5 AA6 Y7 Y8 AB9 AA8 AB8 Y9 AA10 Y5 Y6 B8 B9 L4 H4 K4 G4 H3 J3 J2 K2 L3 M3 K1 M2 N2 P3 R3 R4 R2 P4

Power group V_ENET
V_SAI2_SAI3_SPDIF V_SAI1_SAI5

User’s Manual l TQMa8MPxL UM 0105 l © 2024, TQ-Systems GmbH
3.2.5.6 I2C Four I2C interfaces provided by the i.MX 8M Plus are routed to TQMa8MPxL LGA pads. All I2C devices on the TQMa8MPxL are controlled by the I2C1 bus.
The following table shows the signals used by the I2C interfaces.

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I2C1

i.MX 8M Plus

PCA9450

PCF85063

3.3 V

SE050

SE97BTP

I2C1

24LC64T

LGA pads

I2C2

I2C4

SD1_DATA[1:0]

I2C6

Figure 7: Block diagram I2C

Table 9:
Signal I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA I2C4_SCL I2C4_SDA I2C6_SCL I2C6_SDA

I2C signals
Direction O I/O O I/O O I/O O I/O

i.MX 8M Plus AC8 AH7 AH6 AE8 AF8 AD8 Y29 Y28

TQMa8MPxL C14 D13 C13 C12 B14 B13 V10 W10

Power group 3.3 V V_SD1

Remark 4.7 k PU to 3.3 V on TQMa8MPxL 4.7 k PU to 3.3 V on TQMa8MPxL No PU on TQMa8MPxL No PU on TQMa8MPxL No PU on TQMa8MPxL No PU on TQMa8MPxL No PU on TQMa8MPxL No PU on TQMa8MPxL

The following table shows the I2C devices controlled by the I2C1 bus on the TQMa8MPxL.

Table 10: Address assignment I2C1 bus

Component

Function

PCA9450 24LC64T PCF85063A
SE97BTP
SE050

PMIC EEPROM (optional) RTC (optional) EEPROM (Normal Mode) EEPROM (Protection Mode) Temperature sensor in EEPROM Trust Secure Element (optional)

7-bit address 0x25 / 010 0101b 0x57 / 101 0111b 0x51 / 101 0001b 0x53 / 101 0011b 0x33 / 011 0011b 0x1B / 001 1011b 0x48 / 100 1000b

If more devices are connected to the I2C1 bus on the carrier board, the maximum capacitive bus load according to the I2C standard has to be taken note of. Additional pull-ups should be provided at the I2C bus on the carrier board, if required.

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3.2.5.7 JTAG
The processor provides a JTAG interface that can be used to debug the programs executed on the processor. A corresponding hardware tool is required for this. The interface can also be configured for Boundary Scan.

i.MX 8M Plus
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_MOD

GND

LGA pads
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS

Figure 8: Block diagram JTAG interface

The following table shows the signals used by the JTAG interface. An external circuit on the mainboard has not to be provided.

Table 11:
Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_MOD

JTAG signals
Direction I I O I I

i.MX 8M Plus G18 G16 F14 G14 G20

TQMa8MPxL M19 P18 L19 N18

Remark 10 k PD on TQMa8MPxL

Power group 3.3 V

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3.2.5.8 GPIO
Except for the dedicated differential signals, e.g., MIPI DSI/CSI, and USB, all CPU signals routed to the TQMa8MPxL LGA pads can be configured as GPIO. The electrical characteristics of the GPIOs are to be taken from the i.MX 8M Plus Data Sheet (2). The following table shows the GPIO signals primarily configured as GPIO.

Table 12: GPIO signals
Signal GPIO1_IO00 GPIO1_IO01 GPIO1_IO03 GPIO1_IO06 GPIO1_IO07 GPIO1_IO09 GPIO3_IO14 GPIO2_IO06 GPIO2_IO07 GPIO2_IO10 GPIO2_IO11 GPIO3_IO19 GPIO3_IO20 GPIO3_IO21 GPIO4_IO18 GPIO4_IO19 GPIO4_IO20 GPIO4_IO28 GPIO4_IO27 GPIO4_IO21 GPIO4_IO22 GPIO4_IO24 GPIO4_IO25 GPIO4_IO29 GPIO5_IO04 GPIO5_IO05 GPIO5_IO03 GPIO5_IO27 GPIO5_IO26 GPIO5_IO07 GPIO5_IO06 GPIO5_IO09 GPIO5_IO08

i.MX 8M Plus A7 E8 D6 A3 F6 B8 R26 U26
AA29 W25 W26 AC14 AD14 AE16 AC12 AJ13 AE12 AJ19 AJ15 AH17 AJ16 AJ17 AH15 AJ18 AD18 AC18 AE18 AJ4 AE6 AC20 AF20 AE20 AD20

TQMa8MPxL E16 E15 E14 E12 E11 D11 C16 U8 U9 V6 W7 D2 A2 C2 N4 T2 L1 A9 A6 B6 A7 C7 C9 A10 L5 L6 M6 E9 F9 G1 H1 F2 G2

Power group
V_SD1
V_SAI1_SAI5
V_SAI2_SAI3_SPDIF

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3.2.5.9 MIPI CSI
The i.MX 8M Plus provides two MIPI-CSI camera interfaces with four data pairs each. When using one camera interface, the maximum image format is 4K at 45 fps or 12MP at 30 fps. When using both camera interfaces, up to 1080p at 80 fps is supported. The maximum bit rate is 1.5 Gbps. The differential signals are length matched on the TQMa8MPxL and routed with a differential impedance of 100 .

i.MX 8M Plus
MIPI_CSI[2:1]_CLK_N/P MIPI_CSI[2:1]_D[3:0]_N/P

LGA pads
MIPI_CSI[2:1]_CLKN/P MIPI_CSI[2:1]_DN/P[3:0]

Figure 9: Block diagram MIPI CSI

The following table shows the signals used by the MIPI CSI interface. Table 13: MIPI CSI signals

Signal

i.MX 8M Plus

CSI1_D1_N

E20

CSI1_D1_P

D20

CSI1_D3_N

E26

CSI1_D3_P

D26

CSI1_CLK_N

E22

CSI1_CLK_P

D22

CSI1_D0_N

E18

CSI1_D0_P

D18

CSI1_D2_N

E24

CSI1_D2_P

D24

CSI2_D1_N

B24

CSI2_D1_P

A24

CSI2_D3_N

B21

CSI2_D3_P

A21

CSI2_CLK_N

B23

CSI2_CLK_P

A23

CSI2_D0_N

B25

CSI2_D0_P

A25

CSI2_D2_N

B22

CSI2_D2_P

A22

TQMa8MPxL K20 L20 N20 P20 L22 M22 J21 K21 M21 N21 R21 T21 V21 W21 T20 U20 P22 R22 U22 V22

Power group 1.8 V

3.2.5.10 MIPI DSI
The i.MX 8M Plus provides a DSI interface with four data pairs to output serial display data at up to 1.5 Gbps. The MIPI-DSI PHY supports resolutions up to 1920×1200 @ 60 fps. The differential signals are length matched on the TQMa8MPxL and routed with a differential impedance of 100 .

i.MX 8M Plus
MIPI_DSI1_D[3:0]_P/N MIPI_DSI1_CLK_P/N

LGA pads
MIPI_DSI_DN/P[3:0] MIPI_DSI_CLKN/P

Figure 10: Block diagram MIPI DSI

The following table shows the signals used by the MIPI DSI interface.

Table 14: MIPI DSI signals
Signal DSI_CLK_N DSI_CLK_P DSI_D0_N DSI_D0_P DSI_D1_N DSI_D1_P DSI_D2_N DSI_D2_P DSI_D3_N DSI_D3_P

i.MX 8M Plus B18 A18 B16 A16 B17 A17 B19 A19 B20 A20

TQMa8MPxL F21 G21 D20 E20 E22 F22 G20 H20 H22 J22

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Power group 1.8 V

3.2.5.11 HDMI

The i.MX 8M Plus provides an HDMI interface according to the display specification “HDMI 2.0a” incl. eARC. The maximum resolutions are 3840×2160 @ 30 fps or 1920×1080 @ 120 fps. The interface operates with 1.8 V. The differential signals are length matched on the TQMa8MPxL and routed with a differential impedance of 100 .

Table 15: HDMI signals
Signal EARC_AUX EARC_N_HPD EARC_P_UTIL HDMI_CEC HDMI_TXC_N HDMI_TXC_P HDMI_DDC_SCL HDMI_DDC_SDA HDMI_HPD HDMI_TX0_N HDMI_TX0_P HDMI_TX1_N HDMI_TX1_P HDMI_TX2_N HDMI_TX2_P

i.MX 8M Plus AH23 AH22 AJ23 AD22 AJ24 AH24 AC22 AF22 AE22 AJ25 AH25 AJ26 AH26 AJ27 AH27

TQMa8MPxL V4 T1 U1 W4 U3 V3 AB3 AB2 Y3 V2 W2 W1 Y1 Y2 AA2

Power group 1.8 V

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3.2.5.12 LVDS
In addition to MIPI-DSI and HDMI, the CPU provides an LVDS interface. The CPU only offers one PHY, but supports up to two channels with up to four data lanes each. The maximum resolution is 1920 x 1200 at 60 fps. The interface operates with 1.8 V. The differential signals are length matched on the TQMa8MPxL and routed with a differential impedance of 100 .

i.MX 8M Plus
LVDS[1:0]_D[3:0]_N/P LVDS[1:0]_CLK_N/P
Figure 11: Block diagram LVDS

Table 16: LVDS signals
Signal LVDS0_D0_N LVDS0_D0_P LVDS0_D1_N LVDS0_D1_P LVDS0_D2_N LVDS0_D2_P LVDS0_D3_N LVDS0_D3_P LVDS0_CLK_N LVDS0_CLK_P LVDS1_D0_N LVDS1_D0_P LVDS1_D1_N LVDS1_D1_P LVDS1_D2_N LVDS1_D2_P LVDS1_D3_N LVDS1_D3_P LVDS1_CLK_N LVDS1_CLK_P

i.MX 8M Plus E28 D29 F28 E29 H28 G29 J28 H29 G28 F29 B26 A26 B27 A27 C28 B29 D28 C29 B28 A28

LGA pads
LVDS[1:0]_D[3:0]_N/P LVDS[1:0]_CLK_N/P

TQMa8MPxL Y10 Y11 AA11 AA12 AB12 AB13 AA14 AA15 Y13 Y14 AB15 AB16 Y16 Y17 AA17 AA18 AA19 AA20 AB18 AB19

Power group 1.8 V

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3.2.5.13 PCIe
The i.MX 8M Plus provides a PCIe Gen3 interface with one (x1) lane. The 100 MHz reference clock can be generated on the TQMa8MPxL and output to PCIE_REF_CLKN/P for the PCIe card. Alternatively, the reference clock can be provided from an external source to PCIE_REF_CLKN/P. In general, NXP recommends the use of an external source for accuracy reasons. The series capacitors required by the PCIe standard must be provided on the carrier board. The differential signals are length matched on the TQMa8MPxL and routed with a differential impedance of 85 . The signals must be terminated on the carrier board according to the PCIe specification.

i.MX 8M Plus PCIE_RESREF
PCIE_REF_PAD_CLK_P/N PCIE_RXN_P/N PCIE_TXN_P/N
Figure 12: Block diagram PCIe

LGA pads
GND
PCIE_REF_CLKP/N PCIE_RXP/N PCIE_TXP/N

Table 17: PCIe signals

Signal PCIE_REF_CLKN PCIE_REF_CLKP PCIE_RXN PCIE_RXP PCIE_TXN PCIE_TXP PCIE_RESREF

Direction I/O I O I

i.MX 8M Plus E16 D16 B14 A14 B15 A15 F16

TQMa8MPxL Y22 AA22 W20 Y20 AA21 AB21

Power group 1.8 V
8.2 k PD on TQMa8MPxL

Attention: Accelerated aging of PCI Express PHY
Due to an erratum of the i.MX 8M Plus the PCI Express PHY is subject to accelerated aging in lower power states. In the i.MX 8M Plus errata (5), NXP describes a workaround that must be followed to avoid the aging impact to the PCI Express PHY.

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3.2.5.14 SAI
The i.MX 8M Plus provides several SAI interfaces with different bus widths. The 8-bit SAI1 is not available since it is multiplexed as Ethernet interface. Modules from Rev.02xx use only the SAI3 interface. The supply voltage has to be set to 1.8 V or 3.3 V on the carrier board with LGA pad V_SAI2_SAI3_SPDIF. Clock pins can be used as input or output.

i.MX 8M Plus
SAI3_MCLK SAI3_TXFS
SAI3_TXC SAI3_TXD SAI3_RXD

LGA pads
SAI3_MCLK SAI3_TXFS SAI3_TXC SAI3_TXD0 SAI3_RXD0

Figure 13: Block diagram SAI1

The following table lists all SAI signals provided by the TQMa8MPxL:

Table 18:
Signal SAI3_TXFS SAI4_RXD SAI3_TXc SAI3_TXD SAI3_MCLK

SAI signals
Direction O I O O O

i.MX 8M Plus AC16 AF18 AH19 AH18 AJ20

TQMa8MPxL B11 A12 B12 A13 C10

Power group V_SAI2_SAI3_SPDIF

3.2.5.15 SPDIF
The i.MX 8M Plus has an SPDIF interface that is not used natively. Instead, the pins are multiplexed as GPIOs by default. This configuration can be changed if necessary, for example using the LGA pads shown in the following figure:

i.MX 8M Plus
SPDIF_RX SPDIF_TX SPDIF_EXT_CLK

LGA pads
GPIO5_IO04 GPIO5_IO03 GPIO5_IO05

Figure 14: Block diagram SPDIF

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3.2.5.16 QSPI / NAND
The NOR flash signals are routed to the TQMa8MPxL LGA pads. The NOR flash signals use a part of the NAND pins of the i.MX 8M Plus. All other NAND pins of the i.MX 8M Plus are used TQMa8MPxL-internally for the eMMC as uSDHC3 boot source. These LGA pads cannot be used if the QSPI NOR flash is equipped! For more information regarding QSPI see chapter 3.2.2.3.

Table 19: QSPI signals

Signal

Direction

QSPI_A_DATA3

I/O

QSPI_A_DATA2

I/O

QSPI_A_DATA1

I/O

QSPI_A_DATA0

I/O

QSPI_A_SS0#

O

QSPI_A_SCLK

O

i.MX 8M Plus N24 L24 L25 R25 L26 N25

TQMa8MPxL W12 W13 V13 V14 V15 W15

Power group 1.8 V

3.2.5.17 ECSPI
The full-duplex SPI interfaces of the i.MX 8M Plus support both master and slave modes with data rates of up to 52 Mbit/s. All SPI interfaces provide one chip select each and are directly routed to the TQMa8MPxL LGA pads. ECSPI2 is supplied with 1.8 V. ECSPI3, which is multiplexed with the UART signals, is supplied with 3.3 V.

i.MX 8M Plus ECSPI2_SS0
ECSPI2_MOSI ECSPI2_MISO ECSPI2_SCLK
UART2_TXD UART1_TXD UART2_RXD UART1_RXD
Figure 15: Block diagram ECSPI

LGA pads
ECSPI2_CS0 ECSPI2_SDO ECSPI2_SDI ECSPI2_SCK
ECSPI3_CS0 ECSPI3_SDO ECSPI3_SDI ECSPI3_SCK

The following table shows the signals used by the ECSPI interface.

Table 20:
Signal ECSPI2_MOSI ECSPI2_MISO ECSPI2_SCLK ECSPI2_SS0 ECSPI3_MOSI ECSPI3_MISO ECSPI3_SCLK ECSPI3_SS0

ECSPI signals
Direction O I O O O I O O

i.MX 8M Plus
AJ21 AH20 AH21 AJ22 AJ3 AF6 AD6 AH4

TQMa8MPxL
P5 N5 M5 P6 J6 J5 K5 H5

Power group 1.8 V
3.3 V

3.2.5.18 UART
The i.MX 8M Plus provides four UART interfaces, which are all routed to TQMa8MPxL LGA pads. The voltage supply for UART1, UART2 and UART3 must be externally set to 1.8 V or 3.3 V via LGA pad Y19, V_SD1. UART4 is fixed supplied with 3.3 V.

i.MX 8M Plus
SD1_CLK SD1_CMD SD1_DATA6 SD1_DATA7 UART4_TX UART4_RX SD1_DATA2 SD1_DATA3

LGA pads
UART1_TX UART1_RX UART3_TX UART3_RX UART4_TX UART4_RX UART2_TX UART2_RX

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Figure 16: Block diagram UART interfaces

The following table shows the signals used by the UART interfaces.

Table 21:
Signal UART1_TXD UART1_RXD UART2_TXD UART2_RXD UART3_TXD UART3_RXD UART4_TXD UART4_RXD

UART signals
Direction O I O I O I O I

i.MX 8M Plus W28 W29 V29 V28 AA28 U25 AH5 AJ5

TQMa8MPxL V11 V12 V9 W9 V7 V8 G6 H6

Power group V_SD1 3.3 V

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3.2.5.19 USB
The i.MX 8M Plus provides two USB 3.0 interfaces with integrated PHYs via USB1 and USB2. These support Super-Speed (5 Gbit/s), High-Speed (480 Mbit/s), Full- Speed (12 Mbit/s), as well as Low-Speed (1.5 Mbit/s) and offer host, device and OTG 2.0 functionalities. The OTG signals are provided via GPIO1 pins. All signals have 3.3 V level. Up to 5 V can be applied to the VBUS pins. The 30 k resistors required by NXP are already provided on the module. The differential signals are length matched on the TQMa8MPxL and routed with a differential impedance of 90 .

i.MX 8M Plus
USB1_VBUS USB1_DN/DP USB1_RX_N/RX_P USB1_TX_N/TX_P
GPIO1_IO13 GPIO1_IO12 GPIO1_IO10 USB1_DNU
USB2_VBUS USB2_DN/DP USB2_RX_N/RX_P USB2_TX_N/TX_P
GPIO1_IO15 GPIO1_IO14 GPIO1_IO11 USB2_DNU

LGA pads
USB1_VBUS USB1_DN/DP USB1_RXN/RXP USB1_TXN/TXP USB1_OTG_OC USB1_OTG_PWR USB1_OTG_ID USB1_ID
USB2_VBUS USB2_DN/DP USB2_RXN/RXP USB2_TXN/TXP GPIO1_IO15 (USB2_OTG_OC) GPIO1_IO14 (USB2_OTG_PWR) GPIO1_IO11 (USB2_OTG_ID) USB2_ID

Figure 17: Block diagram USB interfaces

Table 22: USB signals

Signal
USB1_VBUS USB1_OTG_OC USB1_OTG_PWR USB1_OTG_ID USB1_ID USB1_DN USB1_DP USB1_RXN USB1_RXP USB1_TXN USB1_TXP
USB2_VBUS USB2_OTG_OC USB2_OTG_PWR USB2_OTG_ID USB2_ID USB2_DN USB2_DP USB2_RXN USB2_RXP USB2_TXN USB2_TXP

Direction
P I O I I I/O I/O I I O O
P I O I I I/O I/O I I O O

i.MX 8M Plus
A11 A6 A5 B7 B11 E10 D10 B9 A9 B10 A10
D12 B5 A4 D8 E12 E14 D14 B12 A12 B13 A13

TQMa8MPxL
F18 H19 H18 G18 F19 C22 B22 B20 B19 A21 A20
E17 D18 D17 E19 D19 C19 C18 B17 B16 A18 A17

Power group 5 V tolerant
3.3 V
5 V tolerant
3.3 V

Note
NXP: Do not use
Multiplexed as GPIO1_IO15 Multiplexed as GPIO1_IO14 Multiplexed as GPIO1_IO11
NXP: Do not use

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3.2.5.20 uSDHC The i.MX 8M Plus provides three uSDHC interfaces: uSDHC1, uSDHC2 and uSDHC3. uSDHC1 is configured as UART and I2C, see chapters 3.2.5.18 and 3.2.5.6. All three interfaces support the SD standard up to version 3.0, the MMC standard up to version 5.1, and 1.8 V and 3.3 V operation. uSDHC1 and uSDHC3 provide 8-bit wide interfaces, uSDHC2 provides a 4-bit wide interface.
uSDHC1 The voltage level of uSDHC1 can be set to 1.8 V or 3.3 V by TQMa8MPxL LGA pad V_SD1, Y19. Since all essential i.MX 8M Plus signals are routed to TQMa8MPxL LGA pads, an eMMC can be connected on the carrier board. In this case the supply voltage must be set to 1.8 V. Booting from uSDHC1 is only possible after burning boot fuses and is therefore not supported by default.
uSDHC2
An SD card can be connected to the uSDHC2 interface. All i.MX 8M Plus signals required are routed to TQMa8MPxL LGA pads. SD2_VSELECT (GPIO1_IO04) is used to control the SD card supply voltage and is not routed to a TQMa8MPxL LGA pad. The signal SD2_RESET_B can be ignored if the SD card is supplied by the TQMa8MPxL. The voltage V_SD2 is provided for external pull-ups.

i.MX 8M Plus
SD2_CLK SD2_CMD SD2_DATA[3:0] SD2_CD_B
SD2_WP SD2_RESET_B SD2_VSELECT
NVCC_SD2

LGA pads
SD2_CLK SD2_CMD SD2_DATA[3:0] SD2_CD_B SD2_WP SD2_RESET_B V_3V3_SD V_SD2

PMIC PCA9450
LDO5 SD_VSEL
SW_EN SWOUT

Figure 18: Block diagram SD card interface

Table 23:
Signal SD2_DATA3 SD2_DATA2 SD2_DATA1 SD2_DATA0 SD2_CLK SD2_CD# SD2_CMD SD2_WP SD2_RST# 3

USDHC2 signals
Direction I/O I/O I/O I/O O I I/O I O

i.MX 8M Plus AA25 AA26 AC29 AC28 AB29 AD29 AB28 AC26 AD28

TQMa8MPxL T5 U5 V5 W5 T4 R6 U6 T7 U7

uSDHC3 The uSDHC3 interface uses a part of the NAND pins, on the TQMa8MPxL the eMMC is connected to it.

3: 4.7 k PU on TQMa8MPxL.

Power group SD2_VSELECT

3.2.5.21 External clock sources
The i.MX 8M Plus has the option to use two external oscillators as clock sources. All four i.MX 8M Plus signals provided for this purpose are routed to TQMa8MPxL LGA pads. The following table shows these clock signals.

Table 24: CLK signals
Signal CLK1_IN CLK2_IN CLK1_OUT CLK2_OUT

i.MX 8M Plus K28 L28 K29 L29

TQMa8MPxL W18 W16 W17 V17

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Power group 1.8 V

3.2.6

Unspecific signals

The following table lists all signals that are not assigned to a specific group. ISO_7816 and ISO_14443 signals are only available with assembled Trust Secure Element, see chapter 3.2.3.

Table 25: Unspecific signals

Signal PMIC_WDOG_OUT# PMIC_WDOG_IN# M7_NMI TEMP_EVENT# RTC_EVENT# ISO_7816_CLK ISO_7816_RST ISO_7816_IO1 ISO_7816_IO2 ISO_14443_LA ISO_14443_LB

Direction O I I OOD OOD I I I/O I/O I/O I/O

i.MX 8M Plus B6 B4

TQMa8MPxL F8 F6 V19 U19 U18 J19 L18 K18 J18 D21 C21

Remark 3.3 V 3.3 V, 100 k PU on TQMa8MPxL 3.3 V active high 0.9 V to 3.6 V 0.7 V to 5.5 V
Use with populated Trust Secure Element

3.2.7

Reset

Reset inputs or outputs are available at the TQMa8MPxL LGA pads. The following block diagram shows the wiring of the reset signals.

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LGA pads
RESET_IN# ONOFF
PMIC_RST# RESET_OUT#
Figure 19: Block diagram Reset

1.8 V SYS_RST#

i.MX 8M Plus
ONOFF POR_B
PCA9450
PMIC_RST# POR_B

The following table describes the reset signals available at the TQMa8MPxL LGA pads:

Table 26: Reset signals

Signal

Direction TQMa8MPxL

RESET_IN#

I

E7

RESET_OUT#

O

F7

Power group 3.3 V

Remark
· Activates RESET (POR_B) of the i.MX 8M Plus; low-active. · External pull-up to 3.3 V required. · Pull to GND to activate.
· Open drain output; low-active. · Activates RESET of carrier board components. · External pull-up required (max. 5.5 V).

PMIC_RST#

I

E6

1.8 V

· No pull-up on carrier board required; low-active. · Programmable PMIC response (warm reset, cold reset).

ONOFF

· ON/OFF function of the i.MX 8M Plus (see CPU data sheet (2)).

I

G7

1.8 V

· No pull-up on carrier board required; low-active.

· Pull to GND for 5 s to activate.

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3.2.8

Power

3.2.8.1 Power supply

The TQMa8MPxL requires a supply voltage of 5 V ±5 %. The characteristics and functions of a certain pin or signal is to be taken from the PMIC Data Sheet (4), and the i.MX 8M Plus Data Sheet (2).

3.2.8.2 Power consumption
The given power consumption has to be seen as an approximate value. The TQMa8MPxL power consumption strongly depends on the application, the mode of operation and the operating system. For more information on power consumption and savings options, see NXP Application Note AN12410 (6).

The following table shows TQMa8MPxL (with i.MX 8M Plus Quad) power supply (V_5V_IN) and power consumption parameters:

Table 27: Power consumption
Mode of operation Theoretical calculated peak (worst case) U-Boot prompt Linux-Idle Linux with 100 % CPU load Reset Suspend to RAM mode

Current @ 5 V 3.625 A 0.36 A
341.7 mA 716.1 mA 0.140 mA 25.60 mA

Power consumption @ 5 V 18.1 W 1.8 W 1.7 W 3.6 W 0.7 mW
128 mW

3.2.8.3 Voltage monitoring The TQMa8MPxL features a supervisor which monitors the input voltage (VIN). If the input voltage drops below 4.38 V, a Reset is triggered and the TQMa8MPxL is held in reset until the input voltage is in the permitted range again.
Attention: Destruction or malfunction, supply voltage exceedance
The voltage monitoring does not detect an exceedance of the permitted input voltage. An exceedance of the permitted input voltage may cause malfunction, destruction or accelerated ageing of the TQMa8MPxL.

3.2.8.4 Other supply voltages USBx_VBUS: The voltage inputs USB1_VBUS and USB2_VBUS are used to detect the USB-VBUS voltage and are usually connected to the VBUS voltage switched by USB[2:1]_PWR. Protective circuitry on the TQMa8MPxL permits up to 5 V to be applied to these LGA pads. It is recommended to provide one 220 nF capacitor (10 V) each between USBx_VBUS and Ground on the carrier board.
V_LICELL: A coin cell can be connected to the TQMa8MPxL LGA pad D15, V_LICELL, to supply the optional discrete RTC. See chapter 3.2.4.2 for information on the LICELL or RTC options.
Note: RTC power supply
If a discrete RTC is supplied by a coin cell, the CPU-internal RTC is not reset in case of a supply voltage failure.

Page 34

3.2.8.5 Supply outputs The TQMa8MPxL provides three voltages that can be used on the carrier board.

Table 28:
Voltage V_1V8 V_3V3 V_3V3_SD

Voltages provided by TQMa8MPxL

TQMa8MPxL N1 P1 G5

Usage General usage on carrier board General usage on carrier board SD card supply

Max. load 500 mA 500 mA 400 mA

The voltage V_3V3 can be used as Power-Good signal for the supply of circuitry on the carrier board.

Attention: Destruction or malfunction, current exceedance
A load of up to 500 mA at V_1V8 or V_3V3, as well as up to 400 mA at V_3V3_SD causes an increased power consumption of the TQMa8MPxL and thus a higher self- heating. These three voltages are outputs and must never be supplied from external sources! Furthermore the outputs are not short-circuit proof. Overloading the voltage outputs can damage the TQMa8MPxL.

3.2.8.6 Configurable voltages
The TQMa8MPxL provides four LGA pads that define the I/O voltages for specific rails of the CPU. These are listed in the following table and must be defined on the carrier board. If not defined, the corresponding I/O signals are not supplied with voltage. For this purpose the outgoing voltages V_1V8 or V_3V3 can be used.

Table 29: Configurable voltages

Signal

TQMa8MPxL

V_ENET

AB10

V_SAI1_SAI5

B15

Permitted voltages 1.8 V or 3.3 V 1.8 V or 3.3 V

Remark RGMII: 1.8 V RMII: 1.8 V or 3.3 V

V_SAI2_SAI3_SPDIF

A15

1.8 V or 3.3 V

V_SD1

Y19

1.8 V or 3.3 V

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3.2.8.7 Power-Up sequence TQMa8MPxL / carrier board
Since the TQMa8MPxL operates with 5 V and the I/O voltages of the CPU signals are generated on the TQMa8MPxL, there are timing requirements for the carrier board design with respect to the voltages generated on the carrier board: After power up of the 5V supply for the TQMa8MPxL, the PMIC power-up sequence starts. External TQMa8MPxL inputs driven by the carrier board may only be switched on after the power-up of V_3V3. LGA pad P1 (V_3V3) can be used as feedback.

VIN

TQMa8MPxL

5 V

V_5V_IN

V_3V3

Carrier board

VIN

VOUT 3.3 V / 1.8 V / …

DC/DC 3V3 Start-up < 4 ms

ENABLE

Figure 20: Block diagram power supply carrier board

Attention: Destruction or malfunction, Power-Up sequence
To avoid cross-supply and errors in the power-up sequence, no I/O pins may be driven by external components until the power-up sequence has been completed. The end of the power-up sequence is indicated by a high level of signal V_3V3, LGA pad P1.

3.2.8.8 Standby and SNVS
In standby mode, several voltage controllers on the TQMa8MPxL are switched off. The rails V_1V8_SNVS and V_0V8_SNVS remain active, which ensures the correct function of the RTC.

User’s Manual l TQMa8MPxL UM 0105 l © 2024, TQ-Systems GmbH
3.2.8.9 PMIC The characteristics and functions of all pins and signals have to be taken from the i.MX 8M Plus Reference Manual (1) and the PMIC Data Sheet (4). The PMIC is controlled by the I2C1 bus.
The PMIC has I2C address 0x25 / 010 0101b

Page 36

The following PMIC and power management signals are available on the TQMa8MPxL LGA pads

Table 30: Signal

PMIC signals Direction

PMIC_WDOG_IN#

IPU

PMIC_RST#

I

RESET_OUT#

OOD

TQMa8MPxL F6 E6 F7

Power group V_3V3
V_1V8_SNVS 1.8 V

Remark · Low-ctive PMIC Reset input · Triggers Cold Reset · Deactivated by default
· Low-active PMIC Rest input with internal PU · Triggers Cold Reset by default
· Low-active output · Connected to PMIC POR# · Can signal a TQMa8MPxL reset

SD_VSEL

· See chapter 3.2.5.20

Attention: Destruction or malfunction, PMIC programming
Improper programming of the PMIC may result in the i.MX 8M Plus or periphery being operated outside its specification. This may lead to malfunctions, accelerated aging or destruction of the TQMa8MPxL.

3.2.9

Impedances

By default, all single-ended signals have a nominal impedance of 50 ±10 %. However, some interfaces on the TQMa8MPxL are routed with different impedances, depending on the signal requirements.

The following table is taken from the Hardware Developer’s Guide (3) and shows the respective interfaces:

Table 31: Impedances
Signal / Interface DDR DQS/CLK; PCIe CLK, TX/RX data pairs Differential USB signals Differential MIPI (CSI, DSI), HDMI, EARC, LVDS signals Differential RGMII signals

Impedance on TQMa8MPxL 85 , differential 90 , differential
100 , differential 100 , differential

Recommendation for carrier board 85 ±10 %, differential 90 ±10 %, differential
100 ±10 %, differential 100 ±10 %, differential

SOFTWARE

The TQMa8MPxL is delivered with a preinstalled boot loader U-Boot. The BSP provided by TQ-Systems GmbH is configured for the combination of TQMa8MPxL and MBa8MPxL. The boot loader U-Boot provides TQMa8MPxL-specific as well as board- specific settings, e.g.:

· i.MX 8M Plus configuration · PMIC configuration · SDRAM configuration · eMMC configuration · Multiplexing · Clocks · Pin configuration · Driver strengths

Further information can be found in the https://support.tq- group.com/TQMa8MPxL. If another bootloader is used, this data must be adapted. Contact TQ-Support for detailed information.

Page 37

MECHANICS

5.1

Dimensions

Page 38

Figure 21: TQMa8MPxL dimensions, side view

Table 32: TQMa8MPxL heights

Dim.

Value

A

0.125 mm

Tolerance
+0.075 mm 0.025 mm

B

1.6 mm

±0.16 mm

TQMa8MPxL LGA pads height PCB without solder resist

Remark

C

1.43 mm

±0.16 mm Height CPU

C1

1.17 mm

±0.1 mm Height of eMMC and NOR flash

D

0.57 mm

±0.2 mm Highest component, bottom side

E

3.18 mm

±0.23 mm Top edge CPU above carrier board, with soldered TQMa8MPxL

Figure 22: TQMa8MPxL dimensions, top view

Figure 23: TQMa8MPxL dimensions, top through view

5.2

Component placement

Page 39

Figure 24: TQMa8MPxL, component placement top

The labels on the TQMa8MPxL show the following information:

Table 33:
Label AK1 AK2 AK3

Labels on TQMa8MPxL
TQMa8MPxL version and revision Serial number MAC address

Content

22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

B22 C22 D22 E22 F22 G22 H22 J22 K22 L22 M22 N22 P22 R22 T22 U22 V22 W22 Y22 AA22

A21 B21 C21 D21 E21 F21 G21 H21 J21 K21 L21 M21 N21 P21 R21 T21 U21 V21 W21 Y21 AA21 AB21

A20 B20 C20 D20 E20 F20 G20 H20 J20 K20 L20 M20 N20 P20 R20 T20 U20 V20 W20 Y20 AA20 AB20

A19 B19 C19 D19 E19 F19 G19 H19 J19 K19 L19 M19 N19 P19 R19 T19 U19 V19 W19 Y19 AA19 AB19

A18 B18 C18 D18 E18 F18 G18 H18 J18 K18 L18 M18 N18 P18 R18 T18 U18 V18 W18 Y18 AA18 AB18

A17 B17 C17 D17 E17

V17 W17 Y17 AA17 AB17

A16 B16 C16 D16 E16

V16 W16 Y16 AA16 AB16

A15 B15 C15 D15 E15

V15 W15 Y15 AA15 AB15

A14 B14 C14 D14 E14

V14 W14 Y14 AA14 AB14

A13 B13 C13 D13 E13

V13 W13 Y13 AA13 AB13

A12 B12 C12 D12 E12

V12 W12 Y12 AA12 AB12

A11 B11 C11 D11 E11

V11 W11 Y11 AA11 AB11

A10 B10 C10 D10 E10

V10 W10 Y10 AA10 AB10

A9 B9 C9 D9 E9 F9 G9 H9

R9 T9 U9 V9 W9 Y9 AA9 AB9

A8 B8 C8 D8 E8 F8 G8 H8

R8 T8 U8 V8 W8 Y8 AA8 AB8

A7 B7 C7 D7 E7 F7 G7 H7

R7 T7 U7 V7 W7 Y7 AA7 AB7

A6 B6 C6 D6 E6 F6 G6 H6 J6 K6 L6 M6 N6 P6 R6 T6 U6 V6 W6 Y6 AA6 AB6

A5 B5 C5 D5 E5 F5 G5 H5 J5 K5 L5 M5 N5 P5 R5 T5 U5 V5 W5 Y5 AA5 AB5

A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 V4 W4 Y4 AA4 AB4

A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P3 R3 T3 U3 V3 W3 Y3 AA3 AB3

A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 U2 V2 W2 Y2 AA2 AB2

B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 T1 U1 V1 W1 Y1 AA1

A B C D E F G H J K L M N P R T U V W Y AA AB
Figure 25: TQMa8MPxL, LGA pad numbering scheme, top through view

5.3

Adaptation to the environment

The TQMa8MPxL has overall dimensions (length × width) of 38 mm × 38 mm (± 0,1 mm). The TQMa8MPxL has a maximum height above the carrier board of approximately 3.18 mm. The TQMa8MPxL has 366 LGA pads with a diameter of 1.0 mm and a grid of 1.7 mm. The TQMa8MPxL weighs approximately 10 g.

Page 40

5.4

Protection against external effects

The TQMa8MPxL does not provide protection against dust, external impact and contact (IP00). Adequate protection has to be guaranteed by the surrounding system.

5.5

Thermal management

To cool the TQMa8MPxL, noteTable 28. The power dissipation originates primarily in the i.MX 8M Plus, the LPDDR4 SDRAM and the PMIC.
The power dissipation also depends on the software used and can vary according to the application.
See NXP documents (6) and (7) for further information.

Attention: Destruction or malfunction, TQMa8MPxL cooling
The i.MX 8M Plus belongs to a performance category in which a cooling system is essential.
It is the user’s sole responsibility to define a suitable heat sink (weight and mounting position) depending on the specific mode of operation (e.g., dependence on clock frequency, stack height, airflow, and software).
Particularly the tolerance chain (PCB thickness, board warpage, BGA balls, BGA package, thermal pad, heatsink) as well as the maximum pressure on the i.MX 8M Plus must be taken into consideration when connecting the heat sink, see (6). The i.MX 8M Plus is not necessarily the highest component.
Inadequate cooling connections can lead to overheating of the TQMa8MPxL and thus malfunction, deterioration or destruction.

5.6

Structural requirements

The TQMa8MPxL has to be soldered on the carrier board. To ensure a high- quality connection of the LGA pads during reflow soldering of the TQMa8MPxL, the LGA pads must be free of grease and dirt.
Please contact TQ-Support for soldering instructions (11).

Page 41

SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS

6.1

EMC

The TQMa8MPxL was developed according to the requirements of electromagnetic compatibility (EMC). Depending on the target system, anti-interference measures may still be necessary to guarantee the adherence to the limits for the overall system. Following measures are recommended:
· Robust ground planes (adequate ground planes) on the printed circuit board
· A sufficient number of blocking capacitors in all supply voltages
· Fast or permanently clocked lines (e.g., clock signals) should be kept short; avoid interference of other signals by distance and/or shielding, also pay attention to frequencies and signal rise times
· Filtering of all signals, which can be connected externally (also “slow signals” and DC can radiate RF indirectly)
· Direct signal routing without stubs

6.2

ESD

In order to avoid interspersion on the signal path from the input to the protection circuit in the system, the protection against electrostatic discharge should be arranged directly at the inputs of a system. As these measures always have to be implemented on the carrier board, no special preventive measures were planned on the TQMa8MPxL.

Following measures are recommended for a carrier board:

· Generally applicable:

Shielding of inputs (shielding connected well to ground / housing on both ends)

· Supply voltages:

Suppressor diode(s)

· Slow signals:

RC filtering, Zener diode(s)

· Fast signals:

Protection components, e.g., suppressor diode arrays

6.3

Shock and Vibration

Table 34: Shock resistance

Shock Shock form Acceleration Residence time Number of shocks Excitation axes

Parameter

Table 35: Vibration resistance
Parameter Oscillation, sinusoidal Frequency ranges Wobble rate Excitation axes

Acceleration

Details According to DIN EN 60068-2-27 Half sine 30 g 10 ms 3 shocks per direction 6X, 6Y, 6Z

Details

According to DIN EN 60068-2-6

2 ~ 9 Hz, 9 ~ 200 Hz, 200 ~ 500 Hz

1.0 octaves / min

X Y Z axis

2 Hz to 9 Hz: 9 Hz to 200 Hz: 200 Hz to 500 Hz:

3.5 m/s² 10 m/s² 15 m/s²

Page 42

6.4

Climate and operational conditions

The TQMa8MPxL is available in three different variants (Consumer, Extended and Industrial) with different ambient temperature ranges. The operating temperature range for the TQMa8MPxL strongly depends on the installation situation (heat dissipation by heat conduction and convection); hence, no fixed value can be given for the TQMa8MPxL.
In general, a reliable operation is given when following conditions are met:

Table 36: Climate and operational conditions

Parameter

Ambient temperature TQMa8MPxL

Consumer Extended Industrial

TJ temperature i.MX 8M Plus TJ temperature PMIC Case temperature LPDDR4

Case temperature other ICs

Consumer Extended Industrial

Storage temperature TQMa8MPxL

Relative humidity (operating / storage)

Range 0 °C to +85 °C 25 °C to +85 °C 40 °C to +85 °C 40 °C to +105 °C 40 °C to +125 °C 40 °C to +95 °C 0 °C to +85 °C 25 °C to +85 °C 40 °C to +85 °C 40 °C to +85 °C 10 % to 90 %

Remark
Not condensing

Detailed information concerning the i.MX 8M Plus thermal characteristics is to be taken from NXP documents (6) and (7).

Attention: Destruction or malfunction, TQMa8MPxL cooling
The i.MX 8M Plus belongs to a performance category in which a cooling system is essential.
It is the user’s sole responsibility to define a suitable heat sink (weight and mounting position) depending on the specific mode of operation (e.g., dependence on clock frequency, stack height, airflow, and software).
Particularly the tolerance chain (PCB thickness, board warpage, BGA balls, BGA package, thermal pad, heatsink) as well as the maximum pressure on the i.MX 8M Plus must be taken into consideration when connecting the heat sink, see (6). The i.MX 8M Plus is not necessarily the highest component.
Inadequate cooling connections can lead to overheating of the TQMa8MPxL and thus malfunction, deterioration or destruction.

6.5

Intended Use

TQ DEVICES, PRODUCTS AND ASSOCIATED SOFTWARE ARE NOT DESIGNED, MANUFACTURED OR INTENDED FOR USE OR RESALE FOR THE OPERATION IN NUCLEAR FACILITIES, AIRCRAFT OR OTHER TRANSPORTATION NAVIGATION OR COMMUNICATION SYSTEMS, AIR TRAFFIC CONTROL SYSTEMS, LIFE SUPPORT MACHINES, WEAPONS SYSTEMS, OR ANY OTHER EQUIPMENT OR APPLICATION REQUIRING FAIL-SAFE PERFORMANCE OR IN WHICH THE FAILURE OF TQ PRODUCTS COULD LEAD TO DEATH, PERSONAL INJURY, OR SEVERE PHYSICAL OR ENVIRONMENTAL DAMAGE. (COLLECTIVELY, “HIGH RISK APPLICATIONS”)

You understand and agree that your use of TQ products or devices as a component in your applications are solely at your own risk. To minimize the risks associated with your products, devices and applications, you should take appropriate operational and design related protective measures.

You are solely responsible for complying with all legal, regulatory, safety and security requirements relating to your products. You are responsible for ensuring that your systems (and any TQ hardware or software components incorporated into your systems or products) comply with all applicable requirements. Unless otherwise explicitly stated in our product related documentation, TQ devices are not designed with fault tolerance capabilities or features and therefore cannot be considered as being designed, manufactured or otherwise set up to be compliant for any implementation or resale as a device in high risk applications. All application and safety information in this document (including application descriptions, suggested safety precautions, recommended TQ products or any other materials) is for reference only. Only trained personnel in a suitable work

Page 43

area are permitted to handle and operate TQ products and devices. Please follow the general IT security guidelines applicable to the country or location in which you intend to use the equipment.

6.6

Export Control and Sanctions Compliance

The customer is responsible for ensuring that the product purchased from TQ is not subject to any national or international export/import restrictions. If any part of the purchased product or the product itself is subject to said restrictions, the customer must procure the required export/import licenses at its own expense. In the case of breaches of export or import limitations, the customer indemnifies TQ against all liability and accountability in the external relationship,irrespective of the legal grounds. If there is a transgression or violation, the customer will also be held accountable for any losses, damages or fines sustained by TQ. TQ is not liable for any delivery delays due to national or international export restrictions or for the inability to make a delivery as a result of those restrictions. Any compensation or damages will not be provided by TQ in such instances.

The classification according to the European Foreign Trade Regulations (export list number of Reg. No. 2021/821 for dual-usegoods) as well as the classification according to the U.S. Export Administration Regulations in case of US products (ECCN according to the U.S. Commerce Control List) are stated on TQ´s invoices or can be requested at any time. Also listed is the Commodity code (HS) in accordance with the current commodity classification for foreign trade statistics as well as the country of origin of the goods requested/ordered.

6.7

Warranty

TQ-Systems GmbH warrants that the product, when used in accordance with the contract, fulfills the respective contractually agreed specifications and functionalities and corresponds to the recognized state of the art.

The warranty is limited to material, manufacturing and processing defects. The manufacturer’s liability is void in the following cases:

·

Original parts have been replaced by non-original parts.

·

Improper installation, commissioning or repairs.

·

Improper installation, commissioning or repair due to lack of special equipment.

·

Incorrect operation

·

Improper handling

·

Use of force

·

Normal wear and tear

6.8

Operational safety and personal security

Due to the occurring voltages (5 V DC), tests with respect to the operational and personal safety have not been carried out.

6.9

Reliability and service life

The MTBF calculated for the TQMa8MPxL is 1,192,246 hours with a constant error rate @ +40 °C, Ground Benign. The TQMa8MPxL is designed to be insensitive to shock and vibration. The TQMa8MPxL must be assembled in accordance with the processing instructions provided by TQ-Systems GmbH. Detailed information concerning the i.MX 8M Plus service life under different operational conditions is to be taken from the NXP Application Note (7).

Page 44

ENVIRONMENT PROTECTION

7.1

RoHS

The TQMa8MPxL is manufactured RoHS compliant. All components, assemblies and soldering processes are RoHS compliant.

7.2

WEEE®

The final distributor is responsible for compliance with the WEEE® regulation. Within the scope of the technical possibilities, the TQMa8MPxL was designed to be recyclable and easy to repair.

7.3

REACH®

The EU-chemical regulation 1907/2006 (REACH® regulation) stands for registration, evaluation, certification and restriction of substances SVHC (Substances of very high concern, e.g., carcinogen, mutagen and/or persistent, bio accumulative and toxic). Within the scope of this juridical liability, TQ- Systems GmbH meets the information duty within the supply chain with regard to the SVHC substances, insofar as suppliers inform TQ-Systems GmbH accordingly.

7.4

Statement on California Proposition 65

California Proposition 65, formerly known as the Safe Drinking Water and Toxic Enforcement Act of 1986, was enacted as a ballot initiative in November 1986. The proposition helps protect the state’s drinking water sources from contamination by approximately 1,000 chemicals known to cause cancer, birth defects, or other reproductive harm (“Proposition 65 Substances”) and requires businesses to inform Californians about exposure to Proposition 65 Substances.
The TQ device or product is not designed or manufactured or distributed as consumer product or for any contact with endconsumers. Consumer products are defined as products intended for a consumer’s personal use, consumption, or enjoyment. Therefore, our products or devices are not subject to this regulation and no warning label is required on the assembly.
Individual components of the assembly may contain substances that may require a warning under California Proposition 65. However, it should be noted that the Intended Use of our products will not result in the release of these substances or direct human contact with these substances. Therefore you must take care through your product design that consumers cannot touch the product at all and specify that issue in your own product related documentation.
TQ reserves the right to update and modify this notice as it deems necessary or appropriate.

7.5

EuP

The Energy using Products (EuP) is applicable for end user products with an annual quantity of >200,000. Thus the TQMa8MPxL always has to be considered in combination with the complete system. The compliance regarding EuP directive is basically possible for the TQMa8MPxL on account of available Standby or Sleep-Modes of the components on the TQMa8MPxL.

7.6

Battery

No batteries are assembled on the TQMa8MPxL.

7.7

Packaging

The TQMa8MPxL is delivered in reusable packaging.

7.8

Other entries

By environmentally friendly processes, production equipment and products, we contribute to the protection of our environment. To be able to reuse the TQMa8MPxL, it is produced in such a way (a modular construction) that it can be easily repaired and disassembled. The energy consumption of the TQMa8MPxL is minimised by suitable measures.
Because currently there is still no technical equivalent alternative for printed circuit boards with bromine-containing flame protection (FR-4 material), such printed circuit boards are still used.
No use of PCB containing capacitors and transformers (polychlorinated biphenyls).
These points are an essential part of the following laws:
· The law to encourage the circular flow economy and assurance of the environmentally acceptable removal of waste as at 27.9.94 (Source of information: BGBl I 1994, 2705)
· Regulation with respect to the utilization and proof of removal as at 1.9.96 (Source of information: BGBl I 1996, 1382, (1997, 2860))

User’s Manual l TQMa8MPxL UM 0105 l © 2024, TQ-Systems GmbH
· Regulation with respect to the avoidance and utilization of packaging waste as at 21.8.98 (Source of information: BGBl I 1998, 2379)
· Regulation with respect to the European Waste Directory as at 1.12.01 (Source of information: BGBl I 2001, 3379)
This information is to be seen as notes. Tests or certifications were not carried out in this respect.

Page 45

APPENDIX

8.1

Acronyms and definitions

The following acronyms and abbreviations are used in this document:

Table 37: Acronyms

Acronym
ARM® BGA BIOS BSP CAN CAN-FD CPU CSI DDR DIN DNC DSI EARC ECSPI EEPROM EMC eMMC EN ESD EuP FR-4 Gbps GPIO GPT HDMI I I/O I2C IP00 IPU JEDEC JTAG® LGA LPDDR4 LVDS MAC MIPI ML/AI MMC MTBF

Meaning
Advanced RISC Machine Ball Grid Array Basic Input/Output System Board Support Package Controller Area Network CAN with Flexible Data-Rate Central Processing Unit CMOS Sensor Interface Double Data Rate Deutsche Industrienorm (German industry standard) Do Not Connect Display Serial Interface Enhanced Audio Return Channel Enhanced Configurable SPI Electrically Erasable Programmable Read-Only Memory Electromagnetic Compatibility embedded Multimedia Card (Flash) Europäische Norm (European standard) Electrostatic Discharge Energy using Products Flame Retardant 4 Gigabit per second General Purpose Input/Output General-Purpose Timer High-Definition Multimedia Interface Input Input/Output Inter-Integrated Circuit Ingress Protection 00 Input with Pull-Up Joint Electronic Device Engineering Council Joint Test Action Group Land Grid Array Low Power DDR4 Low-Voltage Differential Signaling Media Access Control Mobile Industry Processor Interface Machine Learning / Artificial Intelligence Multimedia Card Mean operating Time Between Failures

Page 46

8.1

Acronyms and definitions (continued)

Table 37: Acronyms (continued)

Acronym
NAND NOR O OD OOD OTG P PCB PCIe PCMCIA PD PHY PMIC PU PWM PWP QSPI RAM RC REACH® RF RGMII RMII RoHS ROM RTC RWP SAI SCU SD SDRAM SNVS SPDIF SPI SVHC TBD TSE UART UM USB uSDHC WEEE® WP

Meaning
Not-And Not-Or Output Open Drain Output with Open Drain On-The-Go Power Printed Circuit Board Peripheral Component Interconnect Express People Can’t Memorize Computer Industry Acronyms Pull-Down (resistor) Physical (layer of the OSI model) Power Management Integrated Circuit Pull-Up (resistor) Pulse- Width Modulation Permanent Write Protected Quad Serial Peripheral Interface Random Access Memory Resistor-Capacitor Registration, Evaluation, Authorisation (and restriction of) Chemicals Radio Frequency Reduced Gigabit Media Independent Interface Reduced Media Independent Interface Restriction of (the use of certain) Hazardous Substances Read-Only Memory Real-Time Clock Reversible Write Protection Serial Audio Interface System Control Unit Secure Digital Synchronous Dynamic Random Access Memory Secure Non-Volatile Storage Sony-Philips Digital Interface Format Serial Peripheral Interface Substances of Very High Concern To Be Determined Trust Secure Element Universal Asynchronous Receiver/Transmitter User’s Manual Universal Serial Bus Ultra- Secured Digital Host Controller Waste Electrical and Electronic Equipment Write-Protection

Page 47

Page 48

8.2

References

Table 38: Further applicable documents

No.

Name

(1) i.MX 8M Plus Applications Processor Reference Manual

(2) i.MX 8M Plus Applications Processors Data Sheet

(3) i.MX 8M Plus Hardware Developer’s Guide

(4) PMIC PCA9450 Data Sheet

(5) i.MX 8M Plus Mask Set Errata for Mask P33A

(6) i.MX 8M Plus Power Consumption Measurement, AN12410

(7) i.MX 8M Plus Product Lifetime Usage, AN12468

(8) SE050 Trust Secure Element Data Sheet

(9) MBa8MPxL User’s Manual

(10) TQMa8MPxL Support-Wiki

(11) TQMa8MPxL Processing instructions

Rev., Date Rev. 1, Jun 2021 Rev 1, Aug 2021 Rev 0, Mar 2021 Rev 2.2, Sep 2021 Rev. 2, Oct 2021 Rev. 0, 14 Apr 2019 Rev.0, 23 Jun 2019 Rev. 3.1, Dec 2020
current current current

Company NXP NXP NXP NXP NXP NXP NXP NXP TQ-Systems TQ-Systems TQ-Systems

TQ-Systems GmbH Mühlstraße 2 l Gut Delling l 82229 Seefeld Info@TQ-Group | TQ- Group