onsemi CAT1021 Supervisory Circuits Instructions

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CAT1021 Supervisory Circuits
Instructions
ORDERING INFORMATION
For Ordering Information details, see page 13.
Supervisory Circuits with
EEPROM Serial 2k-bit I 2 C Manual Reset and
Watchdog Timer

Description

The CAT1021, CAT1022 and CAT1023 are complete memory and supervisory solutions for microcontroller−based systems. A EEPROM Serial 2k−bit I 2C memory and a system power supervisor with brown−out protection are integrated together in low power CMOS technology. Memory interface is via a 400 kHz I 2 C bus.
The CAT1021 and CAT1023 provide a precision VCC sense circuit and two open drain outputs: one (RESET) drives high and the other (RESET) drives low whenever VCC falls below the reset threshold voltage. The CAT1022 has only a RESET output and does not have a Write Protect input. The CAT1021 also has a Write Protect input (WP). Write operations are disabled if WP is connected to a logic high.
All supervisors have a 1.6 second watchdog timer circuit that resets a system to a known state if software or a hardware glitch halts or “hangs” the system. For the CAT1021 and CAT1022, the watchdog timer monitors the SDA signal. The CAT1023 has a separate watchdog timer interrupt input pin, WDI.
The power supply monitor and reset circuit protect memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V systems. If power supply voltages are out of tolerance reset  ignals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 200 ms after the supply voltage exceeds the reset threshold level. With both active high and low reset signals, interface to microcontrollers and other ICs is simple. In addition, the RESET pin or a separate input, MR, can be used as an input for push−button manual reset capability.
The on−chip, 2k−bit EEPROM memory features a 16−byte page. In addition, hardware data protection is provided by a VCC sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the reset threshold during power up.
Available packages include an surface mount 8−pin SOIC, 8−pin TSSOP, 8−pin TDFN and 8−pin MSOP packages. The TDFN package thickness is 0.8 mm maximum. TDFN footprint options are 3 x 3 mm.

Features

• Precision Power Supply Voltage Monitor
  ♦ 5 V, 3.3 V and 3 V Systems
  ♦ Five Threshold Voltage Options

• Watchdog Timer

• Active High or Low Reset
  ♦ Valid Reset Guaranteed at VCC = 1 V

• 400 kHz I2C Bus

• 2.7 V to 5.5 V Operation

• Low Power CMOS Technology

• 16−Byte Page Write Buffer

•  Built−in Inadvertent Write Protection
  ♦ WP Pin (CAT1021)

• 1,000,000 Program/Erase Cycles

• Manual Reset Input

• 100 Year Data Retention

• Industrial and Extended Temperature Ranges

• 8−pin SOIC, TSSOP, MSOP or TDFN (3 x 3 mm Foot−print) Packages
  ♦ TDFN Max Height is 0.8 mm

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

CAT1021, CAT1022, CAT1023

Table 1. THRESHOLD VOLTAGE OPTION

BLOCK DIAGRAM

CAT1021, CAT1022, CAT1023
PIN CONFIGURATION

PIN DESCRIPTION

RESET/RESET: RESET OUTPUT
(RESET CAT1021/23 Only)
These are open drain pins and RESET can be used as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull−down resistor, and the RESET pin must be connected through a pull−up resistor.
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire−ORed with other open drain or open collector outputs.
SCL: SERIAL CLOCK Serial clock input.
MR: MANUAL RESET INPUT
Manual Reset input is a debounced input that can be connected to an external source for Manual Reset. Pulling the MR input low will generate a Reset condition. Reset outputs are active while MR input is low and for the reset timeout period after MR returns to high. The input has an internal pull up resistor.
WP (CAT1021 Only): WRITE PROTECT INPUT
When WP input is tied to VSS or left unconnected write operations to the entire array are allowed. When tied to VCC, the entire array is protected. This input has an internal pull down resistor.

WDI (CAT1023 Only): WATCHDOG TIMER INTERRUPT
Watchdog Timer Interrupt Input is used to reset the watchdog timer. If a transition from high to low or low to high does not occur every 1.6 seconds, the RESET outputs will be driven active.

Table 2. PIN FUNCTION

Table 3. OPERATING TEMPERATURE RANGE

CAT1021, CAT1022, CAT1023

Table 4. CAT102X FAMILY OVERVIEW

Device| Manual Reset Input Pin| Watchdog| Watchdog Monitor Pin| Write Protection Pin| Independent Auxiliary Voltage Sense| RESET: Active High and LOW| EEPROM
---|---|---|---|---|---|---|---
CAT1021| | | SDA| | | | 2k
CAT1022| | | SDA| | | | 2k
CAT1023| | | WDI| | | | 2k
CAT1024| | | | | | | 2k
CAT1025| | | | | | | 2k
CAT1026| | | | | | | 2k
CAT1027| | | WDI| | | | 2k

NOTE : Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm.

SPECIFICATIONS

Table 5. ABSOLUTE MAXIMUM RATINGS

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
   Table 6. D.C. OPERATING CHARACTERISTICS
   VCC = 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified. Symbol| Parameter| Test Conditions| Min| Typ| Max| Units
   ---|---|---|---|---|---|---
   ILI| Input Leakage Current| VIN = GND to VCC| −2| | 10| µA
   ILO| Output Leakage Current| VIN = GND to VCC| −10| | 10| µA
   ICC1| Power Supply Current (Write)| fSCL = 400 kHz VCC = 5.5 V| | | 3| mA
   ICC2| Power Supply Current (Read)| fSCL = 400 kHz VCC = 5.5 V| | | 1| mA
   ISB| Standby Current| VCC = 5.5 V

VIN = GND to VCC

| | | 60| µA
VIL (Note 3)| Input Low Voltage| | −0.5| | 0.3 x VCC| V
VIH (Note 3)| Input High Voltage| | 0.7 x VCC| | VCC + 0.5| V
VOL| Output Low Vo ltage (SDA, RESET)| IOL = 3 mA VCC = 2.7 V| | | 0.4| V
VOH| Output High Voltage (RESET)| IOH = −0.4 mA VCC = 2.7 V| VCC − 0.75| | | V

CAT1021, CAT1022, CAT1023
Table 6. D.C. OPERATING CHARACTERISTICS
V = 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.

Symbol| Parameter| Test Conditions| Min| Typ| Max| Units
---|---|---|---|---|---|---
VTH| Reset Threshold| CAT102x−45 (VCC = 5.0 V)| 4.50| | 4.75| V
CAT102x−42 (VCC = 5.0 V)| 4.25| | 4.50
CAT102x−30 (VCC = 3.3 V)| 3.00| | 3.15
CAT102x−28 (VCC = 3.3 V)| 2.85| | 3.00
CAT102x−25 (VCC = 3.0 V)| 2.55| | 2.70
VRVALID| Reset Output Valid VCC Voltage| | 1.00| | | V
VRT (Note 4)| Reset Threshold Hysteresis| | 15| | | mV

3. VIL min and VIH max are reference values only and are not tested.
4. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
   Table 7. CAPACITANCE
   TA = 25°C, f = 1.0 MHz, VCC = 5 V Symbol| Test| Test Conditions| Max| Units
   ---|---|---|---|---
   COUT (Note 5)| Output Capacitance| VOUT = 0 V| 8| pF
   CIN (Note 5)| Input Capacitance| VIN = 0 V| 6| pF

Table 8. AC CHARACTERISTICS
VCC = 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle (Note 6)

5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. Test Conditions according to “AC Test Conditions” table.
7. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.

CAT1021, CAT1022, CAT1023

Table 9. RESET CIRCUIT AC CHARACTERISTICS

Symbol| Parameter| Test Conditions| Min| Typ| Max| Units
---|---|---|---|---|---|---
tPURST| Power−Up Reset Timeout| Note 2| 130| 200| 270| ms
tRDP| VTH to RESET output Delay| Note 3| | | 5| µs
tGLITCH| VCC Glitch Reject Pulse Width| Notes 4 and 5| | | 30| ns
MR Glitch| Manual Reset Glitch Immunity| Note 1| | | 100| ns
tMRW| MR Pulse Width| Note 1| 5| | | µs
tMRD| MR Input to RESET Output Delay| Note 1| | | 1| µs
tWD| Watchdog Timeout| Note 1| 1.0| 1.6| 2.1| sec

Table 10. POWER−UP TIMING (Notes 5 and 6)

Symbol| Parameter| Test Conditions| Min| Typ| Max| Units
---|---|---|---|---|---|---
tPUR| Power−Up to Read Operation| | | | 270| ms
tPUW| Power−Up to Write Operation| | | | 270| ms

Table 11. AC TEST CONDITIONS

Table 12. RELIABILITY CHARACTERISTICS

Symbol| Parameter| Reference Test Method| Min| Max| Units
---|---|---|---|---|---
NEND (Note 5)| Endurance| MIL−STD−883, Test Method 1033| 1,000,000| | Cycles/Byte
TDR (Note 5)| Data Retention| MIL−STD−883, Test Method 1008| 100| | Years
VZAP (Note 5)| ESD Susceptibility| MIL−STD−883, Test Method 3015| 2000| | Volts
ILTH (Notes 5 & 7)| Latch−Up| JEDEC Standard 17| 100| | mA

1. Test Conditions according to “AC Test Conditions” table.
2. Power−up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
3. Power−Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
4. VCC Glitch Reference Voltage = VTHmin; Based on characterization data
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.
7. Latch−up protection is provided for stresses up to 100 mA on input and output pins from −1 V to VCC + 1 V.

CAT1021, CAT1022, CAT1023
DEVICE OPERATON

Reset Controller Description
The CAT1021/22/23 precision RESET controllers ensure correct system operation during brownout and power up/down conditions. They are configured with open drain RESET outputs.
During power−up, the RESET outputs remain active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200 ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive the reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/down resistors.
During power−down, the RESET outputs will be active when VCC falls below VTH. The RESET output will be valid so long as VCC is >1.0 V (VRVALID). The device is designed to ignore the fast negative going VCC transient pulses (glitches).
Reset output timing is shown in Figure 1.

Manual Reset Operation
The RESET pin can operate as reset output and manual reset input. The input is edge triggered; that is, the RESET input will initiate a reset timeout after detecting a high to low transition.
When RESET I/O is driven to the active state, the 200 ms timer will begin to time the reset interval. If external reset is shorter than 200 ms, Reset outputs will remain active at least 200 ms.
The CAT1021/22/23 also have a separate manual reset input. Driving the MR input low by connecting a pushbutton (normally open) from MR pin to GND will generate a reset condition. The input has an internal pull up resistor.
Reset remains asserted while MR is low and for the Reset Timeout period after MR input has gone high.
Glitches shorter than 100 ns on MR input will not generate a reset pulse. No external debouncing circuits are required.
Manual reset operation using MR input is shown in Figure 2.

Hardware Data Protection
The CAT1021/22/23 supervisors have been designed to solve many of the data corruption issues that have long been associated with serial EEPROMs. Data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data.
Whenever the device is in a Reset condition, the embedded EEPROM is disabled for all operations, including write operations. If the Reset output(s) are active, in progress communications to the EEPROM are aborted and no new communications are allowed. In this condition an internal write cycle to the memory can not be started, but an in progress internal nonvolatile memory write cycle can not be aborted. An internal write cycle initiated before the Reset condition can be successfully finished if there is
enough time (5ms) before VCC reaches the minimum value of 2V.
In addition, the CAT1021 includes a Write Protection Input which when tied to VCC will disable any write operations to the device.

Watchdog Timer
The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, CAT1021/22/23 devices will provide a reset signal after a time−out interval of 1.6 seconds for a lack of activity. The CAT1023 is designed with the Watchdog timer feature on the WDI pin. The CAT1021 and CAT1022 monitor the SDA line. If WDI or SDA does not toggle within a 1.6 second interval, the reset condition will be generated on the reset outputs. The watchdog timer is cleared by any transition on a monitored line.
As long as reset signal is asserted, the watchdog timer will not count and will stay cleared.

CAT1021, CAT1022, CAT1023

CAT1021, CAT1022, CAT1023
EMBEDDED EEPROM OPERATON

The CAT1021/22/23 feature a 2−kbit embedded serial EEPROM that supports the I 2C Bus data transmission
protocol. This Inter−Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access.
Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated.
2 I C Bus Protocol C bus protocol are defined as follows:

1. Data transfer may be initiated only when the bus is not busy.
   The features of the I 2

2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition.

Start Condition
The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT1021/22/23 monitor the SDA and SCL lines and will not respond until this condition is met.

Stop Condition
A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.

DEVICE ADDRESSING

The Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8−bit slave address are programmable in metal and the default is 1010.
The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave address byte, the CAT1021/22/23 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT1021/22/23 then perform a Read or Write operation depending on the R/W bit.

CAT1021, CAT1022, CAT1023
ACKNOWLEDGE

After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data.
All devices respond with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8−bit byte.
When a device begins a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the device will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.

WRITE OPERATIONS

Byte Write
In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends a 8−bit address that is to be written into the address pointers of the device.
After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The device acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to non−volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device.

CAT1021, CAT1022, CAT1023

Page Write
The CAT1021/22/23 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted, the CAT1021/22/23 will respond with an acknowledge and internally increment the lower order address bits by one. The high order bits remain unchanged.
If the Master transmits more than 16 bytes before sending the STOP condition, the address counter ‘wraps around,’ and previously transmitted data will be overwritten.
When all 16 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT1021/22/23 in a single write cycle.

Acknowledge Polling
Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write opration, the CAT1021/22/23 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the device is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation.

WRITE PROTECTION PIN (WP)

The Write Protection feature (CAT1021 only) allows the user to protect against inadvertent memory array programming. If the WP pin is tied to VCC, the entire memory array is protected and becomes read only. The CAT1021 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received.

READ OPERATIONS

The READ operation for the CAT1021/22/23 is initiated in the same manner as the write operation with one exception, the R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ.

CAT1021, CAT1022, CAT1023

Immediate/Current Address Read
The CAT1021/22/23 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. For N = E = 255, the counter will wrap around to zero and continue to clock out valid data. After the CAT1021/22/23 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8−bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition.

Selective/Random Read
Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read.
After the CAT1021/22/23 acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT1021/22/23 then responds with its acknowledge and sends the 8−bit byte requested. The master device does not send an acknowledge but will generate a STOP condition.

Sequential Read
The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1021/22/23 sends the inital 8− bit byte requested, the Master will responds with an acknowledge which tells the device it requires more data. The CAT1021/22/23 will continue to output an 8− bit byte for each acknowledge, thus sending the STOP condition.
The data being transmitted from the CAT1021/22/23 is sent sequentially with the data from address N followed by data from address N + 1. The READ operation address counter increments all of the CAT1021/22/23 address bits so that the entire memory array can be read during one operation.

CAT1021, CAT1022, CAT1023

ORDERING INFORMATION

Orderable Part Numbers − CAT1021 Series (See Notes 1 − 5)

Device| Reset Threshold| Package| Shipping†
CAT1021WI−45−GT3| 4.50 V − 4.75 V| ****

SOIC

| ****

3000 Tape & Reel

CAT1021WI−42−GT3| 4.25 V − 4.50 V
CAT1021WI−30−GT3| 3.00 V − 3.15 V
CAT1021WI−28−GT3| 2.85 V − 3.00 V
CAT1021WI−25−GT3| 2.55 V − 2.70 V
CAT1021YI−45−GT3| 4.50 V − 4.75 V| ****

TSSOP

CAT1021YI−42−GT3| 4.25 V − 4.50 V
CAT1021YI−30−GT3| 3.00 V − 3.15 V
CAT1021YI−28−GT3| 2.85 V − 3.00 V
CAT1021YI−25−GT3| 2.55 V − 2.70 V
CAT1021ZI−45−GT3| 4.50 V − 4.75 V| ****

MSOP

CAT1021ZI−42−GT3| 4.25 V − 4.50 V
CAT1021ZI−30−GT3| 3.00 V − 3.15 V
CAT1021ZI−28−GT3| 2.85 V − 3.00 V
CAT1021ZI−25−GT3| 2.55 V − 2.70 V
CAT1021ZD4I−45T3*| 4.50 V − 4.75 V| ****

TDFN

CAT1021ZD4I−42T3| 4.25 V − 4.50 V
CAT1021ZD4I−30T3| 3.00 V − 3.15 V
CAT1021ZD4I−28T3| 2.85 V − 3.00 V
CAT1021ZD4I−25T3| 2.55 V − 2.70 V

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
4. TDFN not available in NiPdAu (–G) version.
5. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com

CAT1021, CAT1022, CAT1023

Orderable Part Numbers − CAT1022 Series
(See Notes 1 − 5)

Device| Reset Threshold| Package| Shipping†
CAT1022WI−45−GT3| 4.50 V − 4.75 V|

SOIC

|

3000 Tape & Reel

CAT1022WI−42−GT3| 4.25 V − 4.50 V
CAT1022WI−30−GT3| 3.00 V − 3.15 V
CAT1022WI−28−GT3| 2.85 V − 3.00 V
CAT1022WI−25−GT3| 2.55 V − 2.70 V
CAT1022YI−45−GT3| 4.50 V − 4.75 V|

TSSOP

CAT1022YI−42−GT3| 4.25 V − 4.50 V
CAT1022YI−30−GT3| 3.00 V − 3.15 V
CAT1022YI−28−GT3| 2.85 V − 3.00 V
CAT1022YI−25−GT3| 2.55 V − 2.70 V
CAT1022ZI−45−GT3| 4.50 V − 4.75 V|

MSOP

CAT1022ZI−30−GT3| 3.00 V − 3.15 V
CAT1022ZI−28−GT3| 2.85 V − 3.00 V
CAT1022ZI−25−GT3| 2.55 V − 2.70 V
CAT1022ZD4I−45T3*| 4.50 V − 4.75 V|

TDFN

CAT1022ZD4I−42T3| 4.25 V − 4.50 V
CAT1022ZD4I−30T3| 3.00 V − 3.15 V
CAT1022ZD4I−28T3| 2.85 V − 3.00 V
CAT1022ZD4I−25T3| 2.55 V − 2.70 V

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
4. TDFN not available in NiPdAu (–G) version.
5. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
   Nomenclature document, TND310/D, available at www.onsemi.com

CAT1021, CAT1022, CAT1023

Orderable Part Numbers − CAT1023 Series (See Notes 1 − 5)

Device| Reset Threshold| Package| Shipping†
CAT1023WI−45−GT3| 4.50 V − 4.75 V|

SOIC

|

3000 Tape & Reel

CAT1023WI−42−GT3| 4.25 V − 4.50 V
CAT1023WI−30−GT3| 3.00 V − 3.15 V
CAT1023WI−28−GT3| 2.85 V − 3.00 V
CAT1023WI−25−GT3| 2.55 V − 2.70 V
CAT1023YI−45−GT3| 4.50 V − 4.75 V|

TSSOP

CAT1023YI−42−GT3| 4.25 V − 4.50 V
CAT1023YI−30−GT3| 3.00 V − 3.15 V
CAT1023YI−28−GT3| 2.85 V − 3.00 V
CAT1023YI−25−GT3| 2.55 V − 2.70 V
CAT1023ZI−45−GT3| 4.50 V − 4.75 V|

MSOP

CAT1023ZI−42−GT3| 4.25 V − 4.50 V
CAT1023ZI−30−GT3| 3.00 V − 3.15 V
CAT1023ZI−28−GT3| 2.85 V − 3.00 V
CAT1023ZI−25−GT3| 2.55 V − 2.70 V
CAT1023ZD4I−45T3*| 4.50 V − 4.75 V|

TDFN

CAT1023ZD4I−42T3| 4.25 V − 4.50 V
CAT1023ZD4I−30T3| 3.00 V − 3.15 V
CAT1023ZD4I−28T3| 2.85 V − 3.00 V
CAT1023ZD4I−25T3| 2.55 V − 2.70 V

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
4. TDFN not available in NiPdAu (–G) version.
5. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
   Nomenclature document, TND310/D, available at www.onsemi.com

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC−8, 150 mils
CASE 751BD
ISSUE O

Notes:

1. All dimensions are in millimeters. Angles in degrees.
2. Complies with JEDEC MS-012.

DOCUMENT NUMBER:| 98AON34272E| Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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DESCRIPTION:| SOIC 8, 150 MILS| PAGE 1 OF 1

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
MSOP 8, 3×3
CASE 846AD−01
ISSUE O

DATE 19 DEC 2008

Notes:

1. All dimensions are in millimeters. Angles in degrees.
2.  Complies with JEDEC MO-187.

DOCUMENT NUMBER:| 98AON34074E| Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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DESCRIPTION:| MSOP 8, 3X3| PAGE 1 OF 1

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