NXP UM11666 SC18IS606-EVB SPI Bridge Evaluation Board User Manual
- June 4, 2024
- NXP
Table of Contents
NXP UM11666 SC18IS606-EVB SPI Bridge Evaluation Board
Introduction
SC18IS606 is designed to operate as an I2C target and an SPI master. SC18IS606 controls all the SPI bus specific sequences, protocol, and timing. SC18IS606 has its own internal oscillator, and it supports three SPI chip select outputs that may be configured as GPIO when not used as SPI chip selects. This document is intended to help the users to quickly setup, configure and operate the SC18IS606-EVB evaluation board in the users’ hardware platform.
Important notice
NXP provides the enclosed product(s) under the following conditions: This evaluation kit is intended for use of ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY. It is provided as a sample IC pre-soldered to a printed circuit board to make it easier to access inputs, outputs, and supply terminals. This evaluation board may be used with any development system or other source of I/O signals by simply connecting it to the host MCU or computer board via off- theshelf cables. This evaluation board is not a Reference Design and is not intended to represent a final design recommendation for any particular application. Final device in an application will be heavily dependent on proper printed circuit board layout and heat sinking design as well as attention to supply filtering, transient suppression, and I/O signal quality. The goods provided may not be complete in terms of required design, marketing, and or manufacturing-related protective considerations, including product safety measures typically found in the end product incorporating the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. In order to minimize risks associated with the customers applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. For any safety concerns, contact NXP sales and technical support services.
Document information
| Information | Content |
|---|---|
| Keywords | SC18IS606, I2C to SPI, SC18IS602, SPI Controller, SPI master, I2C |
bridge, SPI bridge
Abstract| SC18IS606 is designed to serve as an interface between a standard
I2C- bus of a microcontroller and an SPI bus. This allows the microcontroller
to communicate directly with SPI devices through its I2C-bus. SC18IS606
operates as an I2C target and an SPI master.
Finding kit resources and information on the NXP web site
NXP Semiconductors provides online resources for this evaluation board and its supported device(s) on http://www.nxp.com The information page for the SC18IS606-EVB evaluation board is at http://www.nxp.com/ SC18IS606-EVB. The information page provides overview information, documentation, parametric, ordering information and a Getting Started tab. The Getting Started tab provides quick-reference information applicable to using the SC18IS606-EVB evaluation board, including the downloadable assets referenced in this document.
Collaborate in the NXP community
The NXP community is for sharing ideas and tips, ask and answer technical questions, and receive input on just about any embedded design topic. The NXP community is at http://community.nxp.com
Getting ready
Working with the SC18IS606-EVB evaluation board requires the kit contents.
Kit contents
- Assembled and tested evaluation board in an anti-static bag
- Quick Start Guide
Getting to know the hardware
The SC18IS606-EVB evaluation board is designed to be connected to an external I2C controller via a 6-pin male (JP2) header. The SC18IS606-EVB evaluation board has an on-board SPI slave serial EEPROM, which can be directly accessed by the external I2C controller via SC18IS606. The external I2C controller can write, read, and program the serial EEPROM without requiring an SPI slave to be connected to the board. The 3V3 power for the SC18IS606-EVB evaluation board should be supplied via this I2C interface header as well. The SC18IS606-EVB evaluation board also has an SPI interface header (JP1) to allow other SPI slave devices to be connected to the evaluation board. These SPI slave devices can be accessed directly by the I2C controller via the SC18IS606 I2C to SPI bridge.
Headers and jumpers
Please refer to Figure 1 to find the location of connectors and jumpers on the
SC18IS606-EVB evaluation board.
Jumper settings
Table 1. Jumper settings
| Header | Jumper on | Comment |
|---|---|---|
| JP3 | 1-2, 3-4, 5-6 | I2C target address 0x50 |
| JP4 | 1-2, 3-4 | Pull out jumpers if pull ups on I2C controller |
| JP5 | 1-2 | Pull out and insert current meter if SC18IS606 current is to be |
measured
Table 2. JP1 – SPI header
| JP1 – SPI header | Function |
|---|---|
| 1 | Ground |
| 2 | SPICLK |
| 3 | MOSI |
| 4 | MISO |
| 5 | -CS2 |
| 6 | -CS1 |
| 7 | -CS0 |
Table 3. JP2 – I 2C
| JP2 – I 2C Header | Function |
|---|---|
| 1 | -Reset |
| 2 | -INT (interrupt) |
| 3 | SCL |
| 4 | Ground |
| 5 | VCC |
| 6 | SDA |
Table 4. JP3 – SC18IS606 I 2C target address
JP3 – SC18IS606 I 2C
target address
| 1 -2| 3 -4| 5 -6
---|---|---|---
0x50| ON| ON| ON
0x51| OFF| ON| ON
0x52| ON| OFF| ON
0x53| OFF| OFF| ON
0x54| ON| ON| OFF
0x55| OFF| ON| OFF
0x56| ON| OFF| OFF
0x57| OFF| OFF| OFF
Schematic, board layout and bill of materials
The schematic, board layout and bill of materials for the SC18IS606-EVB evaluation board are available at http://www.nxp.com/SC18IS606-EVB
Sample control sequences from I2C controller
GPIO as input
GPIO as output
SPI mode and clock configuration
Device ID read
On-board EEPROM write and read
Errata list
| Date | Errata Description | Demo Impact | Solution |
|---|---|---|---|
| – | None | None | None |
Legal information
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References
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