MICROCHIP SAMRH71-TFBGA-EB Evaluation Board User Guide

: June 10, 2024
: MICROCHIP

Table of Contents

Introduction
Features
Kit Overview
Getting Started
Hardware User Guide
Revision History
Microchip Information
Worldwide Sales and Service
Documents / Resources

SAMRH71-TFBGA-EB User Guide

Introduction

The Microchip SAMRH71-TFBGA-EB evaluation board is a hardware platform to evaluate the SAMRH71 microcontroller in the Hi-Rel plastic package. It supports Microchip’s MPLAB® Harmony integrated development platform, providing easy access to the Radiation-Hardened SAMRH71F20 microcontroller features. The SAMRH71TFBGA-EB is also compliant with extension boards expanding its functionalities.

Features

SAMRH71F20C-HFB-HP Engineering Sample
On-board Memory
– SST38VF6401 – 64 MB of PROM – 16 bits wide PROM
On-board Clock Management
– 32.768 kHz Crystal
– 10 MHz Oscillator
Communication Interfaces
– Universal Asynchronous Receiver-Transmitter (UART) through a USB bridge
– Ethernet MAC with External IEEE ® 802.3az 10Base-T/100Base-TX Ethernet RMII PHY (VSC8540 Transceiver)
– CAN (ATA6563 Transceiver)
– External Debug Probe Connector
– PKoB4 Embedded Debugger Accessible through USB
Extension Capability
– 3x Headers Compatible with Xplained Extension Boards
– 4x Connectors with Direct Access to the Processor Pins
On-board End User Interface
– One Mechanical Reset Button
– Three Mechanical User Pushbuttons
– Four User LEDs
5V Power Supply
– USB-C® Connector

Kit Overview

The SAMRH71-TFBGA-EB evaluation board is designed to be more affordable than the SAMRH71F20-EK. It has a compact form factor and embedded debugger, which makes it an ideal board for training or development on the go. It is built around a SAMRH71F20 in TFBGA625 package and provides a reference design for this package. This board is compatible with MPLAB X and the Harmony framework to accelerate your software development. The following figure shows the board layout of SAMRH71-TFBGA-EB.
Figure 1-1. SAMRH71-TFBGA-EB Board Layout

MICROCHIP SAMRH71 TFBGA EB Evaluation Board

Getting Started

This section provides information about the software tool for the SAMRH71 -TFBGA-EB evaluation board.
2.1 Start with MPLAB X IDE
MPLAB X Integrated Development Environment (IDE) is an expandable, highly configurable software program that incorporates powerful tools to help you discover, configure, develop, debug, and qualify embedded designs for most of our microcontrollers and Digital Signal Controllers (DSC). MPLAB X IDE works seamlessly with the MPLAB development ecosystem of software and tools, many of which are completely free.

Hardware User Guide

The following sections provide information about power distribution, SST38VF6401 PROM external memory, connectors, and peripherals.
3.1 Power Distribution
The SAMRH71-TFBGA-EB evaluation board is powered by an external 5V through J1. The board uses a MIC7401 Power Management IC to supply power to the AMRH71 and all the other components on the board:

3.3V for SAMRH71 VDDIO and peripherals power supply
1.8V for SAMRH71 CORE and PLLs
1.25V for SpaceWire reference voltage
1V and 2.5V for Ethernet PHY transceiver
5V for CAN transceiver
The following figure shows the block diagram of power supply in the SAMRH71 -TFBGA-EB evaluation board.

MICROCHIP SAMRH71 TFBGA EB Evaluation Board - Power
Distribution

3.2 SST38VF6401 PROM External Memory
The following sections describe SST38VF6401 PROM External Memory.
3.2.1 Memory Overview
The SAMRH71-TFBGA-EB embeds one SST38VF6401 64M (4M x 16) flash memory (U6). This memory is connected to CS0 and can be selected as boot memory via SW4. The following figure shows memory structure of the SAMRH71-TFBGA-EB kit.

MICROCHIP SAMRH71 TFBGA EB Evaluation Board - Power Distribution
1

3.2.2 Boot Memory Configuration
SW4 provides the option to select an internal flash or external PROM as the boot memory (onboard SST38VF6401 flash). When you select the external PROM, additional configuration options are available (ECC state and mode).
Note: In version 2.0 of the board, the “ON” and the “OFF” are swapped.
Table 3-1. DIP Switch Configuration

|

OFF

| ON| SAMRH71 Connections| State| Default State
---|---|---|---|---|---
Pull up on lines| Pull down on lines| 0|

1

Boot Mode| —| —| PF24| Internal Flash| External PROM| Internal Flash
PROM ECC| —| —| PG26| ECC OFF| ECC ON| ECC OFF
ECC Code| —| —| PG27| Hamming (32, 7)| BCH (32, 12)| Hamming

3.3 Connectors
The following section describes the SAMRH71-TFBGA-EB connectors and headers pinout.
3.3.1 Extension Headers
The SAMRH71-TFBGA-EB extension headers are compatible with the Microchip Xplained Extension Board format.
The following tables provide the description of the signals that are shared between the headers and on-board features.
Table 3-2. Extension Header 1 (J5)

EXT1 Pin| SAMRH71 PIN| PIO PeriphA| PIO PeriphB|

PIO PeriphC

---|---|---|---|---
1 [IDEX]| —| —| —| —
2 [GND]| —| —| —| —
3 [ADC+]| PA9| FLEXCOM5_IO2| —| PWMC0_PWMFI1
4 [ADC-]| PA10| FLEXCOM5_IO3| PCK2| PWMC0_PWMEXTRG0
5 [GPIO]| PA11| FLEXCOM5_IO4| PCK0| PWMC0_PWMEXTRG1
6 [GPIO]| PA5| —| TIOB1| PWMC0_PWML1
7 [PWM+]| PA0| —| TCLK0| PWMC0_PWMH0
8 [PWM-]| PA4| —| TIOA1| PWMC0_PWML0
9 [GPIO]| PA1| —| TIOA0| PWMC0_PWMH1
10 [GPIO]| PA3| FLEXCOM2_IO4| TCLK1| PWMC0_PWMH3
11 [TWI_SDA]| PA25| FLEXCOM9_IO0| —| —
12 [TWI_SCL]| PA26| FLEXCOM9_IO1| —| —
13 [UART_RX]| PC10| FLEXCOM5_IO1| —| —
14 [UART_TX]| PC9| FLEXCOM5_IO0| —| —
15 [SPI_SS]| PA7| FLEXCOM2_IO3| TIOA2| PWMC0_PWML3
16 [SPI_MOSI]| PA2| FLEXCOM2_IO0| TIOB0| PWMC0_PWMH2
17 [SPI_MISO]| PA6| FLEXCOM2_IO1| TCLK2| PWMC0_PWML2
18 [SPI_SCK]| PA8| FLEXCOM2_IO2| TIOB2| PWMC0_PWMFI0
19 [GND]| —| —| —| —
20 [VCC]| —| —| —| —

Table 3-3. Extension Header 2 (J7)

EXT2 Pin| SAMRH71 PIN| PIO PeriphA| PIO PeriphB| PIO PeriphC
---|---|---|---|---
1 [IDEX]| —| —| —| —
2 [GND]| —| —| —| —
3 [ADC+]| PA23| FLEXCOM3_IO2| —| QIO1
4 [ADC-]| PA24| FLEXCOM3_IO3| —| QIO0
5 [GPIO]| PA21| FLEXCOM3_IO4| —| QSCK
6 [GPIO]| PA22| FLEXCOM3_IO5| —| QCS
7 [PWM+]| PA12| FLEXCOM3_IO6| —| PWMC0_PWMFI2
8 [PWM-]| PC6| FLEXCOM4_IO6| —| —
9 [GPIO]| PA20| FLEXCOM3_IO0| PCK0| QIO2
10 [GPIO]| PA19| FLEXCOM3_IO1| —| QIO3
11 [TWI_SDA]| PC5| FLEXCOM4_IO5| —| —
12 [TWI_SCL]| PC4| FLEXCOM4_IO4| —| —
13 [UART_RX]| PB15| TIOA5| —| —
14 [UART_TX]| PB16| TIOB5| NWDT1| —
15 [SPI_SS]| PC3| FLEXCOM4_IO3| —| —
16 [SPI_MOSI]| PC0| FLEXCOM4_IO0| —| —
17 [SPI_MISO]| PC1| FLEXCOM4_IO1| —| —
18 [SPI_SCK]| PC2| FLEXCOM4_IO2| —| —
19 [GND]| —| —| —| —
20 [VCC]| —| —| —| —

Table 3-4. Extension Header 3 (J9)

EXT4 Pin| SAMRH71 PIN| PIO PeriphA| PIO PeriphB| PIO PeriphC
---|---|---|---|---
1 [IDEX]| —| —| —| —
2 [GND]| —| —| —| —
3 [ADC+]| PC26| FLEXCOM0_IO5| —| TIOA11
4 [ADC-]| PC27| FLEXCOM0_IO6| —| TIOB11
5 [GPIO]| PB8| TCLK3| —| —
6 [GPIO]| PB9| TIOA3| —| —
7 [PWM+]| PB10| TIOB3| —| —
8 [PWM-]| PB11| TCLK4| —| —
9 [GPIO]| PC28| FLEXCOM0_IO7| —| TCLK10
10 [GPIO]| PC25| FLEXCOM0_IO4| —| TCLK11
11 [TWI_SDA]| PA27| FLEXCOM8_IO0| —| —
12 [TWI_SCL]| PA28| FLEXCOM8_IO1| —| —
13 [UART_RX]| PB12| TIOA4| —| —
14 [UART_TX]| PB13| TIOB4| —| —
15 [SPI_SS]| PCP| FLEXCOM0_IO3| —| TIOB9
16 [SPI_MOSI]| PC21| FLEXCOM0_IO0| —| —
17 [SPI_MISO]| PC22| FLEXCOM0_IO1| —| —
18 [SPI_SCK]| PC23| FLEXCOM0_IO2| —| —
19 [GND]| —| —| —| —
20 [VCC]| —| —| —| —

3.3.2 Observability Connectors
Four headers (J3, J4, J8, and J10) are located around the SAMRH71 device to provide access to every signal.
3.4 Peripherals
The following sections provide information about the peripherals in the SAMRH71-TFBGA-EB.
3.4.1 Crystals
The SAMRH71-TFBGA-EB has four crystals or oscillators used as clock sources for the board.

Y1—50 MHz oscillator for the VSC8540 ethernet PHY
Y2—32.768 kHz crystal for the SAMRH71 slow clock
Y3—10 MHz oscillator for the SAMRH71 fast clock
Y4—12 MHz oscillator for the PKoB4 embedded debugger
To test oscillator frequency, all four crystals/oscillators have adjacent test points.

3.4.2 LEDs
PIOs control the four LEDs on the SAMRH71-TFBGA-EB. The following table lists the LED pin connections along with their shared functionality.
Table 3-5. LED Pin Connections

SAMRH71 PIN| Function|

Shared Functionality

---|---|---
PB19| LED0| PWMC1_PWMH0
PB23| LED1| PWMC1_PWML0
PF19| LED2| NWR0
PF20| LED3| NWR1

3.4.3 Mechanical Push Buttons
There are three pushbuttons on the SAMRH71-TFBGA-EB:

SW5—Reset button
SW1–SW3—User buttons
When you press a button, it drives the PIO line to GND. The following table lists the mechanical end user push button pin connections.

Table 3-6. Mechanical End User Push Buttons Pin Connections

SAMRH71 PIN| Function|

Shared functionality

---|---|---
PC29| PushButton0| —
PC30| PushButton1| —
PC31| PushButton2| —

3.4.4 Ethernet
The SAMRH71F20 microcontroller has a built-in 10/100 Mbps ethernet, IEEE 802.3 compatible MAC with RMII, and MII interfaces. The SAMRH71F20-TFBGA-EB features a Microchip VSC8540 RMII physical layer transceiver (PHY) and a compact RJ45 Ethernet connector with built-in magnetics and status LEDs.
Table 3-7. VSC8540 Connections

SAMRH71 PIN|

Function

---|---
PC11| RXD1
PC12| RXD0
PC13| TXD1
PC14| TXD0
PC15| RXER
PC16| CRSDV
PC17| TXEN
PC18| REFCK
PC19| GMDIO
PC20| GMDC
PF28| NRESET

The VSC8540 default configuration is set via several bootstrap resistors as defined in the following table.
For more information, see the Hardware Mode Strapping in the VSC8540 datasheet.
Table 3-8. VSC8540 Configuration Parameters

Configuration Name

| Default Value on SAMRH71 TFBGA Evaluation Board|

Default Configuration

---|---|---
PHY_ADDRESS| 000| The default address is 00000
MANAGED_MODE| 1| The Unmanaged mode is activated
CONFIG| 00001| Delay 0.2 ns 10/100/1000 FDX/HDX, Autoneg ON RMII
CLKOUT Enable| 0| CLKOUT disable
CLKOUT Frequency| 01| CLKOUT Frequency = 50 MHz
GMII/MII or RGMII/RMII| 0| GRMII/RMII enable

3.4.5 SpaceWire
Both SAMRH71 SpaceWire link 0 and link 1 are grouped on a header (J6). To facilitate loopback test, outputs from one link face inputs from the other (Jumpers are provided in the kit). The following table lists the SpaceWire connections.
Table 3-9. SpaceWire Connections

SAMRH71 PIN|

Function

---|---
SPWDINP1 and SPWDINN1| SpaceWire Data Input 1
SPWDOUTP1 and SPWDOUTN1| SpaceWire Data Output 1
SWPSOUTPP1 1 SWPSOUTPN1| SpaceWire Strobe Output 1
SPWSINP1 and SPWSINN1| SpaceWire Strobe Input 1
SPWDINP0 and SPWDINN0| SpaceWire Data Input 0
SWPDOUTP0 and SWPDOUTN0| SpaceWire Data Output 0
SWPSOUTPP0 and SOUTHAMPTON| SpaceWire Strobe Output 0
SPWSINP0 and SPWSINN0| SpaceWire Strobe Input 0

3.4.6 CAN
The SAMRH71-TFBGA-EB has one CAN interface connected through an ATA6563 CAN physical transceiver.
The following table lists connections between the SAMRH71 and the ATA6563 transceiver.
Table 3-10. CAN Connections

SAMRH71 PIN	Function	ATA6563 Function
PB6	CANTX0	TXD
PB7	CANRX0	RXD
PC7	GPIO	CAN0 Standby

3.4.7 UART
The SAMRH71-TFBGA-EB has one UART routed to the DEBUG USB connector (J15). The SAMRH71 UART from FLEXTIME is converted to USB via a CP2103 UART-To-USB converter (U9). For more information, see CP2103 VCP driver. The following table lists the connections between the SAMRH71 and the CP2103 USB to UART bridge.
Table 3-11. UART Connections

SAMRH71 PIN	Function	CP2103 Function
PF29	FLEXCOM1_IO1	TXD
PF30	FLECOM1_IO0	RXD

3.4.8 Debugger
The following sections describe embedded debugger and external debug probe connector.
3.4.8.1 Embedded Debugger
The SAMRH71-TFBGA-EB features an embedded debugger (PKoB4). The debugger shares the same DEBUG USB port as the virtual COM port mentioned in 3.4.7. UART. When not programming, the PKoB4 keeps its I/Os in high impedance to not interfere with an external debugger if such device is needed.
Table 3-12. PKoB4 Connection

SAMRH71 PIN|

Utility

---|---
PA16| PKoB4 SWCLK
PA17| PKoB4 SWDIO

3.4.8.2 External Debug Probe Connector
The SAMRH71-TFGBA-EB has a 2 x 5-pin Debug Probe Connector (J32CON) supporting the SWD protocol. These pins are shared with the on-board debugger (PKoB4) and use if you prefer an external debugger (J32, ICD4, PicKit4 and so on).
Table 3-13. J32CON Header

Header Pin| SAMRH71 PIN|

Utility

---|---|---
1| —| Power 3V3
7| —| NC
3-5-9| —| Ground
8| PB1| TDI
2| PA17| TMS/SWDIO
4| PA16| TCK/SWCLK
6| PB3| TDO
10| —| NRESET

Revision History

Revision	Date	Description
A	Nov-22	Initial Revision

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