MICROCHIP PIC24 Flash Programming User Guide

MICROCHIP PIC24 Flash Programming

Product Information

Flash Programming
The dsPIC33/PIC24 families of devices have an internal programmable Flash program memory for execution of user code. There are up to three methods to program this memory:

• Table Instruction Operation
• In-Circuit Serial Programming (ICSP)
• In-Application Programming (IAP)

Table instructions provide the method of transferring data between the Flash program memory space and the data memory space of dsPIC33/PIC24 devices. The TBLRDL instruction is used to read from bits[15:0] of program memory space. The TBLWTL instruction is used to write to bits[15:0] of Flash program memory space. TBLRDL and TBLWTL can access Flash program memory in Word mode or Byte mode.

In addition to the Flash program memory address, the table instruction also specifies a W register (or a W Register Pointer to a memory location), that is the source of the Flash program memory data to be written, or the destination for a Flash program memory read.

This section describes the technique for programming Flash program memory. The dsPIC33/ PIC24 families of devices have an internal programmable Flash program memory for execution of user code. There are up to three methods to program this memory:

• Run-Time Self-Programming (RTSP)
• In-Circuit Serial Programming™ (ICSP™)
• Enhanced In-Circuit Serial Programming (EICSP)

RTSP is performed by the application software during execution, while ICSP and EICSP are performed from an external programmer using a serial data connection to the device. ICSP and EICSP allow much faster programming time than RTSP. RTSP techniques are described in Section 4.0 “Run-Time Self-Programming (RTSP)”. The ICSP and EICSP protocols are defined in the Programming Specification documents for the respective devices, which can be downloaded from the Microchip website (http://www.microchip.com). When programming in the C language, several built-in functions are available that facilitate Flash programming. See the “MPLAB® XC16 C Compiler User’s Guide” (DS50002071) for details regarding built-in functions.

Product Usage Instructions

To program the Flash program memory, follow these steps:

1. Refer to the device data sheet to check whether the family reference manual section supports the device you are using.
2. Download the device data sheet and family reference manual sections from the Microchip Worldwide Website at: http://www.microchip.com.
3. Choose one of the three methods to program the memory (Table Instruction Operation, In-Circuit Serial Programming (ICSP), In-Application Programming (IAP)).
4. If using Table Instruction Operation, use the TBLRDL instruction to read from bits[15:0] of program memory space and the TBLWTL instruction to write to bits[15:0] of Flash program memory space.
5. Make sure to specify a W register (or a W Register Pointer to a memory location) as the source of the Flash program memory data to be written, or the destination for a Flash program memory read.

For further information and details on programming the Flash program memory, refer to the dsPIC33/PIC24 Family Reference Manual.

TABLE INSTRUCTION OPERATION

The table instructions provide the method of transferring data between the Flash program memory space and the data memory space of dsPIC33/PIC24 devices. This section provides a summary of the table instructions used during programming of the Flash program memory. There are four basic table instructions:

• TBLRDL: Table Read Low
• TBLRDH: Table Read High
• TBLWTL: Table Write Low
• TBLWTH: Table Write High

The TBLRDL instruction is used to read from bits[15:0] of program memory space. The TBLWTL instruction is used to write to bits[15:0] of Flash program memory space. TBLRDL and TBLWTL can access Flash program memory in Word mode or Byte mode.

The TBLRDH and TBLWTH instructions are used to read or write to bits[23:16] of program memory space. TBLRDH and TBLWTH can access Flash program memory in Word or Byte mode. Because the Flash program memory is only 24 bits wide, the TBLRDH and TBLWTH instructions can address an upper byte of Flash program memory that does not exist. This byte is called the “phantom byte”. Any read of the phantom byte will return 0x00. A write to the phantom byte has no effect. The 24-bit Flash program memory can be regarded as two side-by-side 16-bit spaces, with each  space sharing the same address range. Therefore, the TBLRDL and TBLWTL instructions accessthe “low” program memory space (PM[15:0]). The TBLRDH and TBLWTH instructions access the “high” program memory space (PM[31:16]). Any reads or writes to PM[31:24] will access the phantom (unimplemented) byte. When any of the table instructions are used in Byte mode, the Least Significant bit (LSb) of the table address will be used as the byte select bit. The LSb determines which byte in the high or low program memory space is accessed.

Figure 2-1 illustrates how the Flash program memory is addressed using the table instructions. A 24-bit program memory address is formed using bits[7:0] of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction. The 24-bit Program Counter (PC) is illustrated in Figure 2-1 for reference. The upper 23 bits of the EA are used to select the Flash program memory location.

For the Byte mode table instructions, the LSb of the W register EA is used to select which byte of the 16-bit Flash program memory word is addressed; ‘1’ selects bits[15:8] and ‘0’ selects bits[7:0]. The LSb of the W register EA is ignored for a table instruction in Word mode. In addition to the Flash program memory address, the table instruction also specifies a W register (or a W Register Pointer to a memory location), that is the source of the Flash program memory data to be written, or the destination for a Flash program memory read. For a table write operation in Byte mode, bits[15:8] of the source Working register are ignored.

Using Table Read Instructions
Table reads require two steps:

1. The Address Pointer is set up using the TBLPAG register and one of the W registers.

2. The Flash program memory contents at the address location may be read.

3. READ WORD MODE
   The code shown in Example 2-1 and Example 2-2 shows how to read a word of Flash program memory using the table instructions in Word mode.

4. READ BYTE MODE
   The code shown in Example 2-3 shows the post-increment operator on the read of the low byte, which causes the address in the Working register to increment by one. This sets EA[0] to a ‘1’ for access to the middle byte in the third write instruction. The last post-increment sets W0 back to an even address, pointing to the next Flash program memory location.

5. TABLE WRITE LATCHES
   Table write instructions do not write directly to the nonvolatile program memory. Instead, the table write instructions load write latches that store the write data. The NVM Address registers must be loaded with the first address where latched data should be written. When all of the write latches have been loaded, the actual memory programming operation is started by executing a special sequence of instructions. During programming, the hardware transfers the data in the write latches to Flash memory. The write latches always start at address 0xFA0000, and extend through 0xFA0002 for word programming, or through 0xFA00FE for devices which have row programming.

Note: The number of write latches varies by device. Refer to the “Flash Program Memory” chapter of the specific device data sheet for the number of available write latches.

CONTROL REGISTERS

Several Special Function Registers (SFRs) are used to program the Flash program memory erase and write operations: NVMCON, NVMKEY, and the NVM Address registers, NVMADR and NVMADRU.

NVMCON Register
The NVMCON register is the primary control register for Flash and program/erase operations. This register selects whether an erase or program operation will be performed and can start the program or erase cycle. The NVMCON register is shown in Register 3-1. The lower byte of NVMCON configures the type of NVM operation that will be performed.

NVMKEY Register
The NVMKEY register (see Register 3-4) is a write-only register used to prevent accidental writes of NVMCON that can corrupt Flash memory. Once unlocked, writes to NVMCON are allowed for one instruction cycle in which the WR bit can be set to invoke an erase or program routine. Given the timing requirements, disabling interrupts is required.
Perform the following steps to start an erase or programming sequence:

1. Disable interrupts.
2. Write 0x55 to NVMKEY.
3. Write 0xAA to NVMKEY.
4. Start the programming write cycle by setting the WR bit (NVMCON[15]).
5. Execute two NOP instructions.
6. Restore interrupts.

DISABLING INTERRUPTS
Disabling interrupts is required for all Flash operations to ensure a successful result. If an interrupt occurs during the NVMKEY unlock sequence, it can block the write to the WR bit. The NVMKEY unlock sequence must be executed without interruption, as discussed in Section 3.2 “NVMKEY Register”.

Interrupts can be disabled in one of two methods, by disabling the Global Interrupt Enable (GIE bit), or by using the DISI instruction. The DISI instruction is not recommended since it only disables interrupts of Priority 6 or below; therefore, the Global Interrupt Enable method should be used.

CPU writes to GIE take two instruction cycles before affecting the code flow. Two NOP instructions are needed afterwards, or can be replaced with any other useful work instructions, such as loading NVMKEY; this is applicable to both set and clear operations. Care should be taken when re-enabling interrupts so that the NVM targeted routine does not allow interrupts when a previous called function has disabled them for other reasons. To address this in Assembly, a stack push and pop can be used to retain the state of the GIE bit. In C, a variable in RAM can be used to store INTCON2 prior to clearing GIE. Use the following sequence to disable interrupts:

1. Push INTCON2 onto the stack.
2. Clear the GIE bit.
3. Two NOPs or writes to NVMKEY.
4. Start the programming cycle by setting the WR bit (NVMCON[15]).
5. Restore GIE state by POP of INTCON2.

NVM Address Registers
The two NVM Address registers, NVMADRU and NVMADR, when concatenated, form the 24-bit EA of the selected row or word for programming operations. The NVMADRU register is used to hold the upper eight bits of the EA, and the NVMADR register is used to hold the lower 16 bits of the EA. Some devices may refer to these same registers as NVMADRL and NVMADRH. The NVM Address registers should always point to a double instruction word boundary when performing a double instruction word programming operation, a row boundary when performing a row programming operation or a page boundary when performing a page erase operation.

Register 3-1: NVMCON: Flash Memory Control Register

Note

1. This bit can only be reset (i.e., cleared) on a Power-on Reset (POR).
2. When exiting Idle mode, there is a power-up delay (TVREG) before Flash program memory becomes operational. Refer to the “Electrical Characteristics” chapter of the specific device data sheet for more information.
3. All other combinations of NVMOP[3:0] are unimplemented.
4. This functionality is not available on all devices. Refer to the “Flash Program Memory” chapter in the specific device data sheet for available operations.
5. Entry into a power-saving mode after executing a PWRSAV instruction is contingent on completion of all pending NVM operations.
6. This bit is only available on devices that support RAM buffered row programming. Refer to the device-specific data sheet for availability.

Note

1. This bit can only be reset (i.e., cleared) on a Power-on Reset (POR).
2. When exiting Idle mode, there is a power-up delay (TVREG) before Flash program memory becomes operational. Refer to the “Electrical Characteristics” chapter of the specific device data sheet for more information.
3. All other combinations of NVMOP[3:0] are unimplemented.
4. This functionality is not available on all devices. Refer to the “Flash Program Memory” chapter in the specific device data sheet for available operations.
5. Entry into a power-saving mode after executing a PWRSAV instruction is contingent on completion of all pending NVM operations.
6. This bit is only available on devices that support RAM buffered row programming. Refer to the device-specific data sheet for availability.

Register 3-2: NVMADRU: Nonvolatile Memory Upper Address Register

Register 3-3: NVMADR: Nonvolatile Memory Address Register

Register 3-4: NVMKEY: Nonvolatile Memory Key Register

RUN-TIME SELF-PROGRAMMING (RTSP)

RTSP allows the user application to modify Flash program memory contents. RTSP is accomplished using the TBLRD (Table Read) and TBLWT (Table Write) instructions, the TBLPAG register, and the NVM Control registers. With RTSP, the user application can erase a single page of Flash memory and program either two instruction words or up to 128 instruction words on certain devices.

RTSP Operation
The dsPIC33/PIC24 Flash program memory array is organized into erase pages that can contain up to 1024 instructions. The double-word programming option is available in all devices in the dsPIC33/PIC24 families. In addition, certain devices have row programming capability, which allows the programming of up to 128 instruction words at a time. Programming and erase operations always occur on an even double programming word, row or page boundaries. Refer to the “Flash Program Memory” chapter of the specific device data sheet for the availability and sizes of a programming row, and the page size for erasing. The Flash program memory implements holding buffers, called write latches, that can contain up to 128 instructions of programming data depending on the device. Prior to the actual programming operation, the write data must be loaded into the write latches. The basic sequence for RTSP is to set up the Table Pointer, TBLPAG register, and then perform a series of TBLWT instructions to load the write latches. Programming is performed by setting the control bits in the NVMCON register. The number of TBLWTL and TBLWTH instructions needed to load the write latches is equal to the number of program words to be written.

Note: It is recommended that the TBLPAG register be saved prior to modification and restored after use.

CAUTION
On some devices, the Configuration bits are stored in the last page of program Flash user memory space in a section called, “Flash Configuration Bytes”. With these devices, performing a page erase operation on the last page of program memory erases the Flash Configuration bytes, which enables code protection. Therefore, users should not perform page erase operations on the last page of program memory. This is not a concern when the Configuration bits are stored in Configuration memory space in a section called, “Device Configuration Registers”. Refer to the Program Memory Map in the “Memory Organization” chapter of the specific device data sheet to determine where Configuration bits are located.

Flash Programming Operations
A program or erase operation is necessary for programming or erasing the internal Flash program memory in RTSP mode. The program or erase operation is automatically timed by the device (refer to the specific device data sheet for timing information). Setting the WR bit (NVMCON[15]) starts the operation. The WR bit is automatically cleared when the operation is finished. The CPU stalls until the programming operation is finished. The CPU will not execute any instructions or respond to interrupts during this time. If any interrupts occur during the programming cycle, they will remain pending until the cycle completes. Some dsPIC33/PIC24 devices may provide auxiliary Flash program memory (refer to the “Memory Organization” chapter of the specific device data sheet for details), which allows instruction execution without CPU Stalls while user Flash program memory is being erased and/ or programmed. Conversely, auxiliary Flash program memory can be programmed without CPU Stalls, as long as code is executed from the user Flash program memory. The NVM interrupt can be used to indicate that the programming operation is complete.

Note

1. If a POR or BOR event occurs while an RTSP erase or programming operation is in progress, the RTSP operation is aborted immediately. The user should execute the RTSP operation again after the device comes out of Reset.
2. If an EXTR, SWR, WDTO, TRAPR, CM or IOPUWR Reset event occurs while an RTSP erase or programming operation is in progress, the device will be reset only after the RTSP operation is complete.

RTSP PROGRAMMING ALGORITHM
This section describes RTSP programming, which consists of three major processes.

Creating a RAM Image of the Data Page to be Modified
Perform these two steps to create a RAM image of the data page to be modified:

1. Read the page of Flash program memory and store it into data RAM as a data “image”. The RAM image must be read starting from a page address boundary.
2. Modify the RAM data image as needed.

Erasing Flash Program Memory
After completing Steps 1 and 2 above, perform the following four steps to erase the Flash program memory page:

1. Set the NVMOP[3:0] bits (NVMCON[3:0]) to erase the page of Flash program memory read from Step 1.
2. Write the starting address of the page to be erased into the NVMADRU and NMVADR registers.
3. With interrupts disabled:
   • a) Write the key sequence to the NVMKEY register to enable setting the WR bit (NVMCON[15]).
   • b) Set the WR bit; this will start the erase cycle.
   • c) Execute two NOP instructions.
4. The WR bit is cleared when the erase cycle is complete.

Programming the Flash Memory Page
The next part of the process is to program the Flash memory page. The Flash memory page is programmed using the data from the image created in Step 1. The data are transferred to the write latches in increments of either double instruction words or rows. All devices have double instruction word programming capability. (Refer to the “Flash Program Memory” chapter in the specific device data sheet to determine if, and what type of, row programming is available.) After the write latches are loaded, the programming operation is initiated, which transfers the data from the write latches into Flash memory. This is repeated until the entire page has been programmed. Repeat the following three steps, starting at the first instruction word of the Flash page and incrementing in steps of either double program words, or instruction rows, until the entire page has been programmed:

1. Load the write latches:

   • a) Set the TBLPAG register to point to the location of the write latches.
   • b) Load the desired number of latches using pairs of TBLWTL and TBLWTH instructions:
   • For double-word programming, two pairs of TBLWTL and TBLWTH instructions are required
   • For row programming, a pair of TBLWTL and TBLWTH instructions are required for each instruction word row element

2. Initiate the programming operation:

   • a) Set the NVMOP[3:0] bits (NVMCON[3:0]) to program either double instruction words or an instruction row, as appropriate.
     b) Write the first address of either the double instruction word or instruction row to be programmed into the NVMADRU and NVMADR registers.
     c) With interrupts disabled:
     • Write the key sequence to the NVMKEY register to enable setting the WR bit (NVMCON[15])
     • Set the WR bit; this will start the erase cycle
     • Execute two NOP instructions

3. The WR bit is cleared when the programming cycle is complete.

Repeat the entire process as needed to program the desired amount of Flash program memory.

Note

1. The user should remember that the minimum amount of Flash program memory that can be erased using RTSP is a singe erased page. Therefore, it is important that an image of these locations be stored in general purpose RAM before an erase cycle is initiated.
2. A row or word in Flash program memory should not be programmed more than twice before being erased.
3. On devices with Configuration bytes stored in the last page of Flash, performing a page erase operation on the last page of program memory clears the Configuration bytes, which enables code protection. On these devices, the last page of Flash memory should not be erased.

ERASING ONE PAGE OF FLASH
The code sequence shown in Example 4-1 can be used to erase a page of Flash program memory. The NVMCON register is configured to erase one page of program memory. The NVMADR and NMVADRU registers are loaded with the starting address of the page to be erased. The program memory must be erased at an “even” page address boundary. See the “Flash Program Memory” chapter of the specific device data sheet to determine the size of the Flash page.
The erase operation is initiated by writing a special unlock, or key sequence, to the NVMKEY register before setting the WR bit (NVMCON[15]). The unlock sequence needs to be executed in the exact order, as shown in Example 4-1, without interruption; therefore, interrupts must be disabled.
Two NOP instructions should be inserted in the code after the erase cycle. On certain devices, the Configuration bits are stored in the last page of program Flash. With these devices, performing a page erase operation on the last page of program memory erases the Flash Configuration bytes, enabling code protection as a result. Users should not perform page erase operations on the last page of program memory.

LOADING WRITE LATCHES
The write latches are used as a storage mechanism between the user application Table Writes and the actual programming sequence. During the programming operation, the device will transfer the data from the write latches into Flash memory. For devices that support row programming, Example 4-3 shows the sequence of instructions that can be used to load 128 write latches (128 instruction words). 128 TBLWTL and 128 TBLWTH instructions are needed to load the write latches for programming a row of Flash program memory. Refer to the “Flash Program Memory” chapter of the specific device data sheet to determine the number of programming latches available on your device. For devices that do not support row programming, Example 4-4 shows the sequence of instructions that can be used to load two write latches (two instruction words). Two TBLWTL and two TBLWTH instructions are needed to load the write latches.

Note

1. The code for Load_Write_Latch_Row is shown in Example 4-3 and the code for Load_Write_Latch_Word is shown in Example 4-4. The code in both of these examples is referred to in subsequent examples.
2. Refer to the specific device data sheet for the number of latches.

SINGLE ROW PROGRAMMING EXAMPLE
The NVMCON register is configured to program one row of Flash program memory. The program operation is initiated by writing a special unlock, or key sequence, to the NVMKEY register before setting the WR bit (NVMCON[15]). The unlock sequence needs to be executed without interruption, and in the exact order, as shown in Example 4-5. Therefore, interrupts must be disabled prior to writing the sequence.

Note: Not all devices have row programming capability. Refer to the “Flash Program Memory” chapter of the specific device data sheet to determine if this option is available.

Two NOP instructions should be inserted in the code after the programming cycle.

ROW PROGRAMMING USING THE RAM BUFFER
Select dsPIC33 devices permit row programming to be performed directly from a buffer space in data RAM, rather than going through the holding latches to transfer data with TBLWT instructions. The location of the RAM buffer is determined by the NVMSRCADR register(s), which are loaded with the data RAM address containing the first word of program data to be written.

Prior to performing the program operation, the buffer space in RAM must be loaded with the row of data to be programmed. The RAM can be loaded in either a compressed (packed) or uncompressed format. Compressed storage uses one data word to store the Most Significant Bytes (MSBs) of two adjacent program data words. The uncompressed format uses two data words for each program data word, with the upper byte of every other word being 00h. Compressed format uses about 3/4 of the space in data RAM as compared to the uncompressed format. Uncompressed format, on the other hand, mimics the structure of the 24-bit program data word, complete with the upper phantom byte. The data format is selected by the RPDF bit (NVMCON[9]). These two formats are shown in Figure 4-1.

Once the RAM buffer is loaded, the Flash Address Pointers, NVMADR and NVMADRU, are loaded with the 24-bit start address of the Flash row to be written. As with programming the write latches, the process is initiated by writing the NVM unlock sequence, followed by setting the WR bit. Once initiated, the device automatically loads the right latches and increments the NVM Address registers until all bytes have been programmed. Example 4-7 shows an example of the process. If NVMSRCADR is set to a value such that a data underrun error condition occurs, the URERR bit (NVMCON[8]) will be set to indicate the condition.
Devices which implement RAM buffer row programming also implement one or two write latches. These are loaded using the TBLWT instructions and are used to perform word programming operations.

WORD PROGRAMMING
The NVMCON register is configured to program two instruction words of Flash program memory. The program operation is initiated by writing a special unlock, or key sequence, to the NVMKEY register before setting the WR bit (NVMCON[15]). The unlock sequence needs to be executed in the exact order, as shown in Example 4-8, without interruption. Therefore, interrupts should be disabled prior to writing the sequence.
Two NOP instructions should be inserted in the code after the programming cycle.

Writing to Device Configuration Registers
On certain devices, the Configuration bits are stored in configuration memory space in a section called, “Device Configuration Registers”. On other devices, the Configuration bits are stored in the last page of program Flash user memory space in a section called, “Flash Configuration Bytes”. With these devices, performing a page erase operation on the last page of program memory erases the Flash Configuration bytes, which enables code protection. Therefore, users should not perform page erase operations on the last page of program memory. Refer to the Program Memory Map in the “Memory Organization” chapter of the specific device data sheet to determine where Configuration bits are located.

When the Configuration bits are stored in configuration memory space, RTSP can be used to write to the device Configuration registers, and RTSP allows each Configuration register to be individually rewritten without first performing an erase cycle. Caution must be exercised when writing the Configuration registers since they control critical device operating parameters, such as the system clock source, PLL and WDT enable.

The procedure for programming a device Configuration register is similar to the procedure for programming Flash program memory, except that only TBLWTL instructions are required. This is because the upper eight bits in each device Configuration register are unused. Furthermore, bit 23 of the Table Write address must be set to access the Configuration registers. Refer to “Device Configuration” (DS70000618) in the “dsPIC33/PIC24 Family Reference Manual” and the “Special Features” chapter in the specific device data sheet for a full description of the device Configuration registers.

Note

1. Writing to device Configuration registers is not available in all devices. Refer to the “Special Features” chapter in the specific device data sheet to determine the modes that are available according to the device-specific NVMOP[3:0] bits’ definition.
2. While performing RTSP on device Configuration registers, the device must beoperating using the internal FRC Oscillator (without PLL). If the device is operating from a different clock source, a clock switch to the internal FRC Oscillator (NOSC[2:0] = 000) must be performed prior to performing RTSP operation in the device Configuration registers.
3. If the Primary Oscillator Mode Select bits (POSCMD[1:0]) in the Oscillator Configuration register (FOSC) are being reprogrammed to a new value, the user must ensure that the Clock Switching Mode bits (FCKSM[1:0]) in the FOSC register have an initial programmed value of ‘0’, prior to performing this RTSP operation.

CONFIGURATION REGISTER WRITE ALGORITHM
The general procedure is as follows:

1. Write the new configuration value to the Table Write latch using a TBLWTL instruction.
2. Configure NVMCON for a Configuration register write (NVMCON = 0x4000).
3. Write the address of the Configuration register to be programmed into the NVMADRU and NVMADR registers.
4. Disable interrupts, if enabled.
5. Write the key sequence to the NVMKEY register.
6. Start the write sequence by setting the WR bit (NVMCON[15]).
7. Re-enable interrupts, if needed.

Example 4-10 shows the code sequence that can be used to modify a device Configuration register.

REGISTER MAP

A summary of the registers associated with Flash Programming is provided in Table 5-1.

RELATED APPLICATION NOTES

This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC33/PIC24 product families, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to Flash Programming are:

Note: Please visit the Microchip website (www.microchip.com) for additional Application Notes and code examples for the dsPIC33/PIC24 families of devices.

REVISION HISTORY

Revision A (August 2009)
This is the initial released version of this document.

Revision B (February 2011)
This revision includes the following updates:

• Examples:
  • Removed Example 5-3 and Example 5-4
  • Updated Example 4-1, Example 4-5 and Example 4-10
  • Any references to #WR were updated to #15 in Example 4-1, Example 4-5 and Example 4-8
  • Updated the following in Example 4-3:
• Updated the title “Word Programming” to “Loading Write Latches for Row Programming”
• Any reference to #ram_image was updated to #0xFA
  • Added Example 4-4
  • Updated the title in Example 4-8
• Notes:
  • Added two notes in Section 4.2 “Flash Programming Operations”
  • Updated the note in Section 4.5.2 “Loading Write Latches”
  • Added three notes in Section 4.6 “Writing to Device Configuration Registers”
  • Added Note 1 in Table 5-1
• Registers:
  • Updated the bit values for NVMOP[3:0]: NVM Operation Select bits in the Flash Memory Control (NVMCON) register (see Register 3-1)
• Sections:
  • Removed sections 5.2.1.4 “Write Word Mode” and 5.2.1.5 “Write Byte Mode”
  • Updated Section 3.0 “Control Registers”
  • Updated the following in Section 4.5.5 “Word Programming”:
• Changed the section title “Programming One Word of Flash Memory” to “Word Programming”
• Updated the first paragraph
• Changed the terms “one word” to “a pair of words” in the second paragraph
  • Added a new Step 1 to Section 4.6.1 “Configuration Register Write Algorithm”
• Tables:
  • Updated Table 5-1
• A few references to program memory were updated to Flash program memory
• Other minor updates such as language and formatting updates were incorporated throughout the document

Revision C (June 2011)
This revision includes the following updates:

• Examples:
  • Updated Example 4-1
  • Updated Example 4-8
• Notes:
  • Added a note in Section 4.1 “RTSP Operation”
  • Added Note 3 in Section 4.2 “Flash Programming Operations”
  • Added Note 3 in Section 4.2.1 “RTSP Programming Algorithm”
  • Added a note in Section 4.5.1 “Erasing One Page of Flash”
  • Added Note 2 in Section 4.5.2 “Loading Write Latches”
• Registers:
  • Updated the bit description for bits 15-0 in the Nonvolatile Memory Address register(see Register 3-3)
• Sections:
  • Updated Section 4.1 “RTSP Operation”
  • Updated Section 4.5.5 “Word Programming”
• Other minor updates such as language and formatting updates were incorporated throughout the document

Revision D (December 2011)
This revision includes the following updates:

• Updated Section 2.1.3 “Table Write Latches”
• Updated Section 3.2 “NVMKEY Register”
• Updated the notes in NVMCON: Flash Memory Control Register (see Register 3-1)
• Extensive updates were made throughout Section 4.0 “Run-Time Self-Programming (RTSP)”
• Other minor updates such as language and formatting updates were incorporated throughout the document

Revision E (October 2018)
This revision includes the following updates:

• Added Example 2-2, Example 4-2, Example 4-6 and Example 4-9
• Added Section 4.5.4 “Row Programming Using the RAM Buffer”
• Updated Section 1.0 “Introduction”, Section 3.3 “NVM Address Registers”, Section 4.0 “Run-Time Self-Programming (RTSP)” and Section 4.5.3 “Single Row Programming Example”
• Updated Register 3-1
• Updated Example 4-7
• Updated Table 5-1

Revision F (November 2021)
Added Section 3.2.1 “Disabling Interrupts”.
Updated Example 3-1, Example 4-1, Example 4-2, Example 4-5, Example 4-6, Example 4-7, Example 4-8, Example 4-9 and Example 4-10.
Updated Section 3.2 “NVMKEY Register”, Section 4.5.1 “Erasing One Page of Flash”, Section 4.5.3 “Single Row Programming Example” and Section 4.6.1 “Configuration Register Write Algorithm”.

Note the following details of the code protection feature on Microchip products:

• Microchip products meet the specifications contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions.
• Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products

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Trademarks

The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, NVM Express, NVMe, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, Symmcom, and Trusted Time are registered trademarks of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2009-2021, Microchip Technology Incorporated and its subsidiaries.
All Rights Reserved.
ISBN: 978-1-5224-9314-3

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Note:

This family reference manual section is meant to serve as a complement to device data sheets. Depending on the device variant, this manual section may not apply to all dsPIC33/PIC24 devices. Please consult the note at the beginning of the “Flash Program Memory” chapter in the current device data sheet to check whether this document supports the device you are using.
Device data sheets and family reference manual sections are available for download from the Microchip Worldwide Website at: http://www.microchip.com.

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