MICROCHIP UG0877 SLVS-EC Receiver for PolarFire FPGA User Guide
- June 10, 2024
- MICROCHIP
Table of Contents
MICROCHIP UG0877 SLVS-EC Receiver for Polar Fire FPGA User Guide
Revision History
The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the current publication.
Revision 4.0
The following is a summary of the changes made in revision 4.0 of this
document.
- Replaced Figure 2, page 2, Figure 3, page 3, Figure 8, page 6, and Figure 9, page 7.
- Removed section Transmit PLL, page 4.
- Updated Table 1, page 3, Table 3, page 7, Table 4, page 7, and Table 5, page 8.
- Updated section PLL for Pixel Clock Generation, page 4.
- Updated section Configuration Parameters, page 7.
Revision 3.0
The following is a summary of the changes made in revision 3.0 of this
document.
- SLVS-EC IP, page 2
- Table 3 on page 7
Revision 2.0
The following is a summary of the changes made in revision 2.0 of this
document.
- SLVS-EC IP, page 2
- Transceiver Configuration, page 3
- Table 3 on page 7
Revision 1.0
Revision 1.0 was the first publication of this document
SLVS-EC IP
SLVS-EC is Sony’s high-speed interface for next-generation high-resolution CMOS image sensors. This standard is tolerant of lane-to-lane skew because of embedded clock technology. It makes a board-level design easy in terms of high-speed and long-distance transmission. SLVS-EC Rx IP core provides SLVS-EC interface for PolarFire FPGA to receive image sensor data. The IP supports speed up to 4.752 Gbps. The IP core supports two, four, and eight lanes for RAW 8, RAW 10, and RAW 12 configurations. The following figure shows the system diagram for the SLVS-EC camera solution.
Figure 1 • SLVS-EC IP Block Diagram
Polar Fire® transceiver is used as the PHY interface for the SLVS-EC sensor since the SLVS-EC interface uses embedded clock technology. It also uses 8b10b encoding, which can be recovered using the PolarFire transceiver. PolarFire FPGA has up to 24 low-power 12.7 Gbps transceiver lanes. These transceiver lanes can be configured as the SLVS-EC PHY receiver lanes. As shown in the preceding figure, the transceiver outputs are connected to SLVS-EC Rx IP core.
SLVS-EC Receiver Solution
The following figure shows the Libero SoC software top level design
implementation of SLVS-EC IP and the required components for the SLVS-EC
receiver solution.
Figure 2 • SLVS-EC IP SmartDesign
Transceiver Configuration
The following figure shows the transceiver interface configuration.
Figure 3 • Transceiver Interface Configurator
The Transceiver can be configured to either two or four lanes. Also, the speed of the transceiver can be set at the “Transceiver data rate”. SLVS-EC interface supports two baud rates as listed in following table.
Table 1 • SLVS-EC Baud Rate
| Baud Grade | Baud Rate in Mbps |
|---|---|
| 1 | 1188 |
| 2 | 2376 |
| 3 | 4752 |
PLL for Pixel Clock Generation
A PLL is required to generate pixel clock from the Transceiver generated
Fabric clock that is, LANE0_RX_CLOCK. Following is the formula to generate
pixel clock.
Pixel clock = (LANE0_RX_CLOCK * 8)/DATA_WIDTH
Configure the PF_CCC for RAW 8 as shown in the following figure.
Figure 4 • Clock Conditioning Circuitry
Design Description
The following figure shows the SLVS-EC Frame Format structure.
Figure 5 • SLVS-EC Frame Format Structure
The Packet header contains information about the frame start and end signals along with the Valid lines. PHY control codes are added above the packet header to form the SLVS-EC packet. The following table lists the different PHY control codes used in the SLVS-EC protocol.
Table 2 • PHY Control Code
PHY Control Code 8b10b Symbol Combination
Start Code K.28.5 – K.27.7 – K.28.2 – K.27.7
End Code K.28.5 – K.29.7 – K.30.7 – K.29.7
Pad Code K.23.7 – K.28.4 – K.28.6 – K.28.3
Sync Code K.28.5 – D.10.5 – D.10.5 – D.10.5
Idle Code D.00.0 – D.00.0 – D.00.0 – D.00.0
SLVS-EC RX IP Core
This section describes the hardware implementation details of SLVS-EC Receiver
IP. The following figure shows the Sony SLVS-EC receiver solution that
contains the Polar Fire SLVS-EC RX IP. This IP is used in conjunction with the
Polar Fire transceiver interface block. The following figure shows the
internal blocks of the SLVS-EC Rx IP.
Figure 6 • Internal Blocks of the SLVS-EC RX IP
aligner
This module receives the data from the PolarFire transceiver blocks and aligns
to the sync code. This module looks for the sync code in the bytes received
from the transceiver and locks to the byte boundary.
slvsec_phy_rx
This module receives the data from the aligner and decodes the incoming SLVS
PHY packets. This module passes through the synchronization sequence and then,
generates the pkt_en signal starting from Start code and ends at the end code.
It also removes the PAD code from the data packets and sends the data to the
next module that is slvsrx_decoder.
slvsrx_decoder
This module receives the data from the slvsec_phy_rx module and extracts the
pixel data from the payload. This module extracts four pixels per clock per
lane and sends to the output. It generates the line valid signal for the
active lines validating the active video data. It also generates the Frame
valid signal by looking at the frame start and frame end bits in the packet
header of the SLVS-EC packets
FSM with Data Decoding States
The following figure shows the FSM for SLVS-EC RX IP.
Figure 7 • FSM for SLVS-EC RX IP
SLVS-EC Receiver IP Configuration
The following figure shows the SLVS-EC receiver IP configurator.
Figure 8 • SLVS-EC Receiver IP Configurator
Configuration Parameters
The following table lists the description of the configuration parameters used
in the hardware implementation of SLVS-EC receiver IP block. These are generic
parameters and can vary based on the application requirements.
Table 3 • Configuration Parameters
Name Description
DATA_WIDTH Input pixel data width. Supports RAW 8, RAW 10, and RAW 12.
LANE_WIDTH Number of SLVS-EC lanes. Supports two, four, and eight lanes.
BUFF_DEPTH Depth of the buffer. Number of active pixels in active video
line.
Buffer depth can be calculated by using the following equation:
BUFF_DEPTH = Ceil ((Horizontal Resolution RAW width) / (32 Lane width))
Example: RAW width = 8, Lane width = 4, and Horizontal Resolution = 1920
pixels
BUFF_DEPTH = Ceil ((1920 8)/ (32 4)) = 120
Inputs and Outputs
The following table lists the input and output ports of the SLVS-EC RX IP
configuration parameters
Table 4 • Input and Output Ports
| Signal Name | Direction | Width | Description |
|---|---|---|---|
| LANE#_RX_CLK | Input | 1 | Recovered clock from the transceiver for that |
particular Lane
LANE#_RX_READY| Input| 1| Data ready signal for Lane
LANE#_RX_VALID| Input| 1| Data Valid signal for Lane
LANE#_RX_DATA| Input| 32| Lane recovered data from transceiver
LINE_VALID_O| Output| 1| Data valid signal for active pixels in a line
FRAME_VALID_O| Output| 1| Valid signal for Active lines in a frame
DATA_OUT_O| Output| DATA_WIDTHLANE_WIDTH4| Pixel data output
Timing Diagram
The following figure shows the SLVS-EC IP timing diagram.
Figure 9 • SLVS-EC IP Timing Diagram
Resource Utilization
The following table shows the resource utilization of a sample SLVS-EC
Receiver Core implemented in a PolarFire FPGA (MPF300TS-1FCG1152I package),
for RAW 8 and four lanes and 1920 horizontal resolution configuration.
Table 5 • Resource Utilization
| Element | Usage |
|---|---|
| DFFs | 3001 |
| 4-input LUTs | 1826 |
| LSRAMs | 16 |