MICROCHIP Xilinx Spartan 6 Example Conversion User Guide
- June 9, 2024
- MICROCHIP
Table of Contents
MICROCHIP Xilinx Spartan 6 Example Conversion
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Create Libero® SoC Design Suite Project
Place conversion-script into ISE® project directory
python conv_xise_1v0.py -t
Open Libero SoC Design Suite and run created TCL-script
Project is created but missing:
- IP: BlockRAM, my_clocks
- Architectural base-blocks: bufg
Continued
Supported target architectures for conversion
- MPFS: PolarFire® SoC
- MPF: PolarFire FPGA
- M2S: SmartFusion®2
- M2GL: IGLOO®2
- AGL: IGLOO
- A3P: ProASIC®3
IGLOO and ProASIC3 devices require Libero SoC version 11.9 or earlier
Other architectures supported in latest version of Libero SoC
Replace PLLs and DCMs
- Select IP catalog in Libero ® SoC Design Suite
- Create Clock Conditioning Circuit (CCC) for required frequencies
- Choose Advanced“ tab for reset
Replace Individual Clock Buffers
Designs often contain instantiated clock buffers (BUFG)
- Vendor specific libraries
- Unisim => smartfusion, smartfusion2,polarfire
Change of instantiations
- BUFG => CLKINT
Documentation: Macro Library Guide
- SmartFusion®, IGLOO® and ProASIC®3
- SmartFusion2 and IGLOO2
- PolarFire ®
Replace Block RAM
- Create new LSRAM from IP catalog
- Configure LSRAM
Create Shim
- Take existing port map of Block RAM
- Create new HDL file
- Adapt port map of shim
Instantiate LSRAM into Shim
- Take entity declaration from IP file
- Connect shim ports with instance
Update Design Hierarchy
Click Build Hierarchy“
Integration of sources under root design
Correct errors in HDL
Run synthesis
- Correct potential typos reported by tools
Constraints
Double click Manage Constraints“
Enter timing constraints
Create Derived Constraints“
Derived constraints:
- Take PLL functionality (multiply/phase shift)
- Constraints “b ehind“ clock modification
Click on “Derive Constraints”
- Populates additional SDC file
Constrain clock domain crossings
Assign Pins
- Constraints manager
- Pin assignment via table
- Pin assignment via package
Implement Design
-
Place and route design
-
Check timing and do timing closure
(set_false_path on clock domain
-
Create bitstream
Done
Enjoy longevity of your new FPGA design
2022 Microchip Technology Inc. and its subsidiaries
References
- microsemi.com/document-portal/doc_download/1245848-smartfusion2-and-igloo2-macro-library-guide-for-libero-soc-v2021-2
- microsemi.com/document-portal/doc_download/130887-igloo-proasic3-smartfusion-and-fusion-macro-library-guide-for-software-v10-1
- microsemi.com/document-portal/doc_download/136918-polarfire-fpga-macro-library-guide