9R1 Alpha Data Parallel Systems User Manual

: May 15, 2024
: ALPHA DATA

Table of Contents

9R1 Alpha Data Parallel Systems User Manual
Read User Manual Online (PDF format)
Download This Manual (PDF format)

9R1 Alpha Data Parallel Systems User Manual

ADS-STANDALONE/9R1 User Manual

Document Revision: 1.2

10/05/2023

This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Ltd.

Head Office
Address: Suite L4A, 160 Dundee Street, Edinburgh, EH11 1DQ, UK
Telephone: +44 131 558 2600
Fax: +44 131 558 2700
email: sales@alpha-data.com
website: http://www.alpha-data.com

US Office
10822 West Toller Drive, Suite 250 Littleton, CO 80127
(303) 954 8768
(866) 820 9956 – toll free
sales@alpha-data.com
http://www.alpha-data.com

All trademarks are the property of their respective owners.

Introduction

The ADS-STANDALONE/9R1 is a stand-alone RFSoC enclosure providing 16-RF analogue channels, Ethernet, RS232 Serial COM, USB, and QSFP IO. The RF channels can run up to 10GSPS (DAC) and 5 GSPS(ADC)

The ADS-STANDALONE/9R1 uses a single 15V-30V input power supply. An on-board system monitor micro-controller provides voltage/current monitoring of the generated power supplies, as well as providing the capability to turn the supplies on/off via the micro USB interface. A USB to JTAG circuit is also provided, giving access to the JTAG chain without requiring an external JTAG box.

Key Features

Key Features

Xilinx RFSoC FPGA with PS block consisting of:
- Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5, Mali-400 GPU
- 1 bank of DDR4-2400 SDRAM 2GB
- Two Quad SPI Flash memory, 512Mb each
- USB
- RS232 serial COM port
- Gigabit Ethernet
Programmable Logic (PL) block consisting of:
- 4 HSSIO links to the QSFP connector
- 2 banks of DDR4-2400 SDRAM, 1GB per bank
RF Sampling block consisting of:
- 8 12-bit 4/5GSPS RF-ADCs
- 8 14-bit 6.5/10GSPS RF-DACs
- 8 soft-decision FECs (ZU28DR/ZU48DR only)
- Full Scale Input (100MHz/ZU27DR): 5.0dBm
- Full Scale Output (100MHz/20mA Mode/ZU27DR): -4.5dBm
- Full Scale Output (100MHz/32mA Mode/ZU48DR): 1.15dBm
Front Panel IO Interface with:
- 8 HF single ended ADC signals
- 8 HF single ended DAC signals
- Reference clock input for the RF sampling blocks
- Reference clock output from RF sampling blocks
- 2 digital GPIO

Figure 1 : ADS-STANDALONE/9R1

ADMC-XMC-STANDALONE User Manual:https://www.alpha- data.com/xml/user_manuals/adc-xmc-standalone%20user%20manual.pdf

ADM-XRC-9R1 User Manual:https://www.alpha-data.com/xml/user_manuals/adm- xrc-9r1%20user%20manual.pdf

ADM-XRC-9R1 Reference Design:https://www.alpha- data.com/resource/admxrc9r1

Main Input Power Supply Requirements

The total power requirement will vary depending on the particular FPGA design. A 60W supply would likely be more than enough for most FPGA designs before thermal limits of the device and heatsink become the limiting factor. Alpha- Data can provide a power supply estimator spreadsheet to estimate the total power requirements for a particular FPGA design. An example compatible power supple is RS PRO part number 175-3290: https://uk.rs-online.com/web/p/ac-dc- adapters/1753290

Table 1 : Suggested Input Supply Specifications

Installation and Power Up

Connect a serial cable to the serial port and connect the other end to a USB-to-serial converter.
Open a serial terminal with at 115200 baud, 8 data bits, 1 stop bit.
Turn the power switch on, and the PS should start to boot from then internal SD card.
Once booted login with the username “root” and password “root”
To run the RF example design, use the command “boardtest-9r1”

See the example design user guide for details on the operation of the boardtest-9r1 application

JTAG Interface

A USB to JTAG circuit is provided, giving access to the XMC JTAG interface without the need for an external programming box (e.g. Xilinx Platform Cable II). The USB to JTAG converter is compatible with Vivado, and will appear in hardware manager as a Digilent device. A 14-pin JTAG header is also available, with an on-board multiplexer to switch between the 14-pin header or the USB to JTAG converter. The multiplexer selects the USB to JTAG circuit when a micro USB cable is attached.

Current/Voltage Monitoring

The ADS-STANDALONE/9R1 provides current sense functionality on the 12V and combined 3V3 internal supplies. These values can be reported over the micro- USB interface, using the alpha-data “avr2util” utility.

Avr2util for Windows and the associated USB driver can be downloaded here:

https://support.alpha-data.com/pub/firmware/utilities/windows/

Avr2util for Linux can be downloaded here:

https://support.alpha-data.com/pub/firmware/utilities/linux/

Use “avr2util.exe /?” to see all options.

For example “avr2util.exe /usbcom \\.\com4 display-sensors” will display all sensor values.

Note that ‘com4’ is used here as an example, and should be changed to match the com port number assigned under windows device manager

On-Board Generated Power Supplies

The ADS-STANDALONE/9R1 generates the 3V3/3V3_AUX/12V0/-12V0 supplies required by the XMC site from a single 15V-30V input supply. Each supply has the following specifications:

Table 2

Table 2 : ADS-STANDALONE/9R1 Power Supplies

[1] The 3V3_DIG and 3V3_AUX rails are generated from the same supply, so the maximum current is the combination of 3V3_AUX + 3V3_DIG. The current monitoring also measures the combined current. [2] The 3V3_AUX rail is an always-on 3.3V auxiliary power supply from the 15V-30V input.

The 3V3_DIG/3V3_AUX/12V0_DIG current usage of a particular design can be estimated using a power estimation spreadsheet. Contact support@alpha- data.com for access to the spreadsheet.

Front-Panel I/O

The front panel interface consists of a 20-way high-speed connector. This connector Supports an external reference clock input and output, two GPIO pins, 8 DAC signals and 8 ADC signals. The connector part number is Nicomatic CMM342D000F51-0020-240002.

Table 3

Table 3 : Front panel I/O signals

Figure 2 : Front Panel Pinout

Rear-Panel I/O

The rear panel interface consists of Power, USB, Ethernet, QSFP, RS-232 UART, 14-pin JTAG and micro USB connectors.

Figure 3 : Rear Panel Pinout

Figure 4 : RS-232 Pinout

QSFP pinout

The QSFP cage is connected to FPGA bank 129.

Table 4 : ADM-XRC-9R1 pcb revision 3+ pinout for J16

Dimensions

Table 5 : ADS-STANDALONE/9R1 dimensions

Order Code

ADS-STANDALONE/X/T

Table 6

Table 6 : ADC-XMC-STANDALONE Order Code

Revision History

Address: Suite L4A, 160 Dundee Street,
Edinburgh, EH11 1DQ, UK
Telephone: +44 131 558 2600
Fax: +44 131 558 2700
email: sales@alpha-data.com
website: http://www.alpha-data.com

Address: 10822 West Toller Drive, Suite 250
Littleton, CO 80127
Telephone: (303) 954 8768
Fax: (866) 820 9956 – toll free
email: sales@alpha-data.com
website: http://www.alpha-data.com