ALPHA DATA ADM-PCIE-9V5 PCIe Card with Integrated User Manual Product Information
- May 15, 2024
- ALPHA DATA
Table of Contents
ADM-PCIE-9V5 PCIe Card with Integrated
“`html
Product Information
Specifications:
-
Model: ADM-PCIE-9V5
-
FPGA: Xilinx Virtex UltraScale+ Plus
-
Transceivers: Low latency
-
Connectivity: Four QSFP-DD cages
-
PCI Express Compliance: CEM revision 3.0
-
Dimensions (PCB only): 100.15mm x 181.5mm x
1.6mm -
Dimensions (Fully Assembled): 120.9mm x
181.5mm x 19.7mm, Weight: 590 grams -
PCIe Compatibility: PCIe Gen 3 with 8
lanes
Product Usage Instructions:
Installation:
To install the ADM-PCIE-9V5, follow these steps:
-
Ensure your system has an available PCIe slot that meets the
mechanical requirements (8 or 16 lanes). -
Gently insert the card into the PCIe slot, making sure it is
properly seated. -
Secure the card in place using the mounting screws
provided.
Configuration:
To configure the ADM-PCIE-9V5, you can refer to the complete
pinout table provided in the user manual or visit the
manufacturer’s website for detailed instructions.
Maintenance:
For maintenance, ensure the card is free from dust and debris to
prevent overheating. Use compressed air to clean the card if
necessary.
Frequently Asked Questions (FAQ):
Q: Where can I find the complete ordering options for
ADM-PCIE-9V5?
A: You can find the complete ordering options for ADM-PCIE-9V5
on the Alpha Data website at http://www.alpha-data.com/pdfs/adm-pcie-
9v5.pdf.
Q: What are the chassis requirements for ADM-PCIE-9V5?
A: The ADM-PCIE-9V5 requires a PCIe Gen 3 slot with 8 or 16
lanes for mechanical compatibility.
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ADM-PCIE-9V5 User Manual
Document Revision: 1.5 July 17th 2023
ADM-PCIE-9V5 User Manual
© 2023 Copyright Alpha Data Parallel Systems Ltd. All rights reserved.
This publication is protected by Copyright Law, with all rights reserved. No
part of this publication may be reproduced, in any shape or form, without
prior written consent from Alpha
Data Parallel Systems Ltd.
Head Office
Address: Suite L4A, 160 Dundee Street,
Edinburgh, EH11 1DQ, UK
Telephone: +44 131 558 2600
Fax:
+44 131 558 2700
email:
website: http://www.alpha-data.com
US Office
10822 West Toller Drive, Suite 250 Littleton, CO 80127 (303) 954 8768 (866)
820 9956 – toll free [email protected] http://www.alpha-data.com
All trademarks are the property of their respective owners.
ADM-PCIE-9V5 User Manual
Table Of Contents
1 1.1 1.2
2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.3.1 2.4
3 3.1 3.1.1 3.1.2 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.3 3.4 3.5 3.6
3.6.1 3.6.2 3.7 3.8 3.8.1 3.8.1.1 3.8.2 3.9 3.9.1 3.9.2 3.10
Introduction …………………………………………………………………………………………………………………….. 1 Key Features
…………………………………………………………………………………………………………………. 1 Order Code
…………………………………………………………………………………………………………………… 1
Board Information ……………………………………………………………………………………………………………. 2 Physical
Specifications …………………………………………………………………………………………………… 2 Chassis Requirements
……………………………………………………………………………………………………. 3 PCI Express
………………………………………………………………………………………………………………. 3 Mechanical Requirements
…………………………………………………………………………………………… 3 Power Requirements
………………………………………………………………………………………………….. 3 KN32 Emissions
………………………………………………………………………………………………………. 3 Thermal Performance
…………………………………………………………………………………………………….. 4 Active VS Passive Thermal
Management ………………………………………………………………………. 5 Customizations
……………………………………………………………………………………………………………… 5
Functional Description …………………………………………………………………………………………………….. 6 Overview
………………………………………………………………………………………………………………………. 6 Switches
……………………………………………………………………………………………………………………. 7 LEDs
………………………………………………………………………………………………………………………… 8 Clocking
……………………………………………………………………………………………………………………….. 9 Si5328
…………………………………………………………………………………………………………………….. 12 PCIe Reference Clocks
……………………………………………………………………………………………… 12 Fabric Clock
…………………………………………………………………………………………………………….. 12 Programming Clock (EMCCLK)
………………………………………………………………………………….. 12 QSFP-DD Clock
……………………………………………………………………………………………………….. 12 Ultraport SlimSAS (OpenCAPI)
………………………………………………………………………………….. 12 PCI Express
………………………………………………………………………………………………………………… 13 QSFP-DD
……………………………………………………………………………………………………………………. 14 OpenCAPI Ultraport SlimSAS
………………………………………………………………………………………… 15 System Monitor
……………………………………………………………………………………………………………. 16 System Monitor Status LEDs
……………………………………………………………………………………… 17 Fan Controllers
………………………………………………………………………………………………………… 17 USB Interface
………………………………………………………………………………………………………………. 18 Configuration
……………………………………………………………………………………………………………….. 18 Configuration From Flash
Memory ……………………………………………………………………………… 18 Building and Programming
Configuration Images ……………………………………………………… 19 Configuration via JTAG
……………………………………………………………………………………………… 19 GPIO Connector
………………………………………………………………………………………………………….. 20 Direct Connect FPGA Signals
…………………………………………………………………………………….. 20 Timing Input
…………………………………………………………………………………………………………….. 20 User EEPROM
…………………………………………………………………………………………………………….. 22
Appendix A Complete Pinout Table …………………………………………………………………………………………………… 23
List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7
Mechanical Dimensions (PCB only) ……………………………………………………………………………………… 2 Mechanical Dimensions (Fully Assembled) …………………………………………………………………………… 2 Available Power By Rail ……………………………………………………………………………………………………… 3 Switch Functions ……………………………………………………………………………………………………………….. 7 LED Details ………………………………………………………………………………………………………………………. 8 Voltage, Current, and Temperature Monitors ……………………………………………………………………….. 16 Status LED Definitions ……………………………………………………………………………………………………… 17
ADM-PCIE-9V5 User Manual
Table 8
Complete Pinout Table ……………………………………………………………………………………………………… 23
List of Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17
ADM-PCIE-9V5 Product Photo ……………………………………………………………………………………………. 1 ADM-PCIE-9V5 Top View …………………………………………………………………………………………………… 2 KN32 Emissions ……………………………………………………………………………………………………………… 3 Thermal Performance ………………………………………………………………………………………………………… 4 ADM-PCIE-9V5 Fan …………………………………………………………………………………………………………… 5 ADM-PCIE-9V5 2-slot enhanced heat sink ……………………………………………………………………………. 5 ADM-PCIE-9V5 Block Diagram …………………………………………………………………………………………… 6 Switches …………………………………………………………………………………………………………………………… 7 Front Panel LEDs ………………………………………………………………………………………………………………. 8 Clock Topology ………………………………………………………………………………………………………………….. 9 VU5P FPGA Clock Location ……………………………………………………………………………………………… 10 VU9P FPGA Clock Location ………………………………………………………………………………………………. 11 QSFP-DD Location ………………………………………………………………………………………………………….. 14 OpenCAPI Location …………………………………………………………………………………………………………. 15 OpenCAPI Pinout …………………………………………………………………………………………………………….. 15 GPIO Connector Schematic ………………………………………………………………………………………………. 20 GPIO Connector Location …………………………………………………………………………………………………. 20
ADM-PCIE-9V5 User Manual
1 Introduction
The ADM-PCIE-9V5 is a high-performance reconfigurable computing card intended
for Data Center applications, featuring a screened Xilinx Virtex UltraScale+
Plus FPGA with low latency transceivers and four QSFP-DD cages.
Figure 1 : ADM-PCIE-9V5 Product Photo
1.1 Key Features
Key Features · PCIe Gen3 x8 capable · Passive and active thermal management
configuration · 1/2 length, full profile, x8 edge PCIe form factor · Four
QSFP-DD cages for a total of 32 channels each capable of 28 Gpbs operation
(total 896 Gbps) · One 8-lane Ultraport SlimSAS connectors compliant with
OpenCAPI and suitable for IO expansion · Supports VU5P, VU9P Virtex
UltraScale+ FPGAs in the A2104 package. · Front panel and rear edge JTAG
access via USB port · FPGA configurable over USB/JTAG and SPI configuration
flash · Voltage, current, and temperature monitoring · 8 GPIO signals and 1
isolated timing input · User LEDs and timing input options.
1.2 Order Code
See http://www.alpha-data.com/pdfs/adm-pcie-9v5.pdf for complete ordering
options.
Introduction ad-ug-1385_v1_5.pdf
Page 1
ADM-PCIE-9V5 User Manual
2 Board Information
2.1 Physical Specifications
The ADM-PCIE-9V5 complies with PCI Express CEM revision 3.0.
Description PCB Dy Total Dx PCB Dz
Measure 100.15 mm 181.5 mm
1.6 mm
Table 1 : Mechanical Dimensions (PCB only)
Description Total Dy Total Dx Total Dz
Weight
Measure 120.9 mm 181.5 mm 19.7 mm 590 grams (without
fan)
Table 2 : Mechanical Dimensions (Fully Assembled)
Page 2
Figure 2 : ADM-PCIE-9V5 Top View
Board Information ad-ug-1385_v1_5.pdf
ADM-PCIE-9V5 User Manual
2.2 Chassis Requirements
2.2.1 PCI Express
The ADM-PCIE-9V5 is capable of PCIe Gen 3 with 8 lanes, using the Xilinx Integrated Block for PCI Express.
2.2.2 Mechanical Requirements
An 8 or 16 lane physical PCIe slot is required for mechanical compatibility.
2.2.3 Power Requirements
The ADM-PCIE-9V5 draws power from the PCIe Edge and the 6-pin ATX power
connector. The ADM-PCIE-9V5 does not use or require the 3.3V power from the
PCIe Edge (though it does use 3.3V AUX). Revision 1 cards (serial number less
than 110) require both PCIe edge and 6-pin ATX power connector. Revision 2 and
onward can operate with only the PCIe edge. To operate with PCIe edge only,
ensure SW1-3 is OFF (see Switches). As per PCIe specification, users should
limit the board power consumption to 66W when using only the PCIe edge power.
Adding the 6-pin ATX connector provides additional 75W of power, bringing the
total board power dissipation maximum to 141W.
Power consumption estimation requires the use of the Xilinx XPE spreadsheet
and a power estimator tool available from Alpha Data. Please contact support
@alpha-data.com to obtain this tool.
The power available to the rails calculated using XPE are as follows:
Voltage 0.85-0.90
0.9 1.2 1.8 1.8 3.3
Source Name VCC_INT + VCCINT_IO + VCC_BRAM
MGTAVCC MGTAVTT VCCAUX + VCCAUX_IO + VCCO_1.8V MGTVCCAUX 3.3V for Optics
Current Capability 80A 8A 15A 3A 1A 9A
Table 3 : Available Power By Rail
2.2.4 KN32 Emissions
Board Information ad-ug-1385_v1_5.pdf
Figure 3 : KN32 Emissions
Page 3
ADM-PCIE-9V5 User Manual
2.3 Thermal Performance
If the FPGA core temperature exceeds 105 degrees Celsius, the FPGA design will
be cleared to prevent the card from over-heating.
The ADM-PCIE-9V5 comes with a heat sink to help avoid thermal overstress of
FPGA, since it is typically the hottest point on the card. The FPGA die
temperature must remain under 100 degrees Celsius. To calculate the FPGA die
temperature, take your application power, multiply by Theta JA from the table
below, and add to your system internal ambient temperature. If you are using
the fan provided with the board, you will find theta JA is approximately 0.88
degC/W for the board in still air.
The power dissipation can be estimated by using the Alpha Data power estimator
in conjunction with the Xilinx Power Estimator (XPE) downloadable at
http://www.xilinx.com/products/technology/power/xpe.html. Download the
UltraScale tool and set the device according to your part number details:
Virtex UltraScale+, VU13P/VU9P, A2104 package, -2/-3 speed grade, extended.
Set the ambient temperature to your system ambient and select ‘user override’
for the effective theta JA and enter the figure associated with your system
LFM in the blank field. Proceed to enter all applicable design elements and
utilization in the following spreadsheet tabs. Next acquire the 9V5 power
estimator from Alpha Data by contacting [email protected]. You will then
plug in the FPGA power figures along with Optical module figures to get a
board level estimate.
Theta JA
ADM-PCIE-9H7 Board Level Thermal Performance
1.60 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30
0.00
200.00 400.00 600.00 800.00 1000.00 1200.00 1400.00 1600.00 1800.00 2000.00 Linear Feet per Minute (LFM)
Figure 4 : Thermal Performance
Page 4
Board Information ad-ug-1385_v1_5.pdf
ADM-PCIE-9V5 User Manual
2.3.1 Active VS Passive Thermal Management
The ADM-PCIE-9V5 ships with a small optional blower for active cooling in
systems with poor airflow. If the ADM-PCIE-9V5 will be installed in a server
with controlled airflow, the card may be ordered without the additional fan
hardware. The fans have a much shorter mean time between failure (MTBF) than
the rest of the assembly, so passive cards have much longer life expectance
before requiring maintenance. The ADM-PCIE-9V5 also includes a fan speed
controller, allowing variable fan speed based on die temperature, and
detection of a failed fan (see section Fan Controllers).
Figure 5 : ADM-PCIE-9V5 Fan
2.4 Customizations
Alpha Data provides extensive customization options to existing commercial
off-the-shelf (COTS) products. Some options include, but are not limited to:
additional networking cages in adjacent slots, enhanced heat sinks, baffles,
and circuit additions. Please contact [email protected] to get a quote and
start your project today.
Figure 6 : ADM-PCIE-9V5 2-slot enhanced heat sink
Board Information ad-ug-1385_v1_5.pdf
Page 5
ADM-PCIE-9V5 User Manual
3 Functional Description
3.1 Overview
The ADM-PCIE-9V5 is a versatile reconfigurable computing platform with a
Virtex UltraScale+ VU5P/VU9P FPGA, a Gen3x8 PCIe interface, four QSFP-DD
cages, an OpenCAPI compatible Ultraport SlimSAS connector also capable of
28G/channel, an isolated input for a timing synchronization pulse, a 12 pin
header for general purpose use (clocking, control pins, debug, etc.), front
panel LEDs, and a robust system monitor.
Q(8QS(x8Q2S(Fx88Q2SFPxG82SFP-Gb8DpFP-GbsDDpP-b)sDDp-)sDD) D
(8x28Gbps)
USB (back)
USB to JTAG
Mux+Hub
System Monitor
PPS ISOLATION
GPIO
x32
MGT GPIO
x4
MGT
XCVU5P XCVU9P
FLGA2104
FireFly
(4x28Gbps)
0
MGT MGT
MGT x8
USB (front)
QSPI (Config)
I2C (0,4) (5,7)
x8 PCIe Gen3 Edge
ATX PWR Blower
SlimSAS
(8x28Gbps)
Figure 7 : ADM-PCIE-9V5 Block Diagram
Page 6
Functional Description ad-ug-1385_v1_5.pdf
ADM-PCIE-9V5 User Manual
3.1.1 Switches
The ADM-PCIE-9V5 has an octal DIP switch SW1, located on the rear side of the
board. The function of each switch in SW1 is detailed below:
Figure 8 : Switches
Switch
SW1-1 SW1-2
Factory Default
OFF OFF
Function
User Switch 0 User Switch 1
OFF State
Pin AW33 = ‘1’ Pin AY36 = ‘1’
ON State
Pin BF52 = ‘0’ Pin BF47 = ‘0’
SW1-3 ON
12V Auto-detect
12V PCIe edge auto-detect ATX AUX power required
SW1-4 OFF
Power Off
Board will power up
Immediately power down
SW1-5 OFF SW1-6 ON SW1-7 ON SW1-8 ON
Service Mode HOST_I2C_EN CAPI_VPD_EN OpenCAPI_VPD_WP
System Monitor normal operation
System Monitor Service Mode (firmware update etc.)
System Monitor connected to System Monitor isolated from
PCIe slot I2C
PCIe slot I2C
OpenCAPI VPD PROM connected to PCIe slot I2C
OpenCAPI VPD PROM isolated from PCIe slot I2C
OpenCAPI VPD is write protected
CAPI VPD is writable
Table 4 : Switch Functions Use I/O Standard “LVCMOS18” when constraining the User Switch pins.
Functional Description ad-ug-1385_v1_5.pdf
Page 7
ADM-PCIE-9V5 User Manual
3.1.2 LEDs
There are 9 LEDs on the ADM-PCIE-9V5, 6 of which are general purpose and whose
meaning can be defined by the user. The other 3 have fixed functions described
below:
User LEDs
D8
D6
LED_G2 LED_G4
D13
D12
LED_G3 LED_G5
D1
D2
LED_G0 LED_G1
Status LEDs
D4
D5
D7
DONE STAT_1 STAT_0
Figure 9 : Front Panel LEDs
Comp. Ref. D1 D2 D8 D13 D6 D12 D4 D5 D7
Function
USER_LED_G0_1V8 USER_LED_G1_1V8 USER_LED_G2_1V8 USER_LED_G3_1V8
USER_LED_G4_1V8 USER_LED_G5_1V8
DONE Status 1 Status 0
ON State
OFF State
User defined ‘0’
User defined ‘1’
User defined ‘0’
User defined ‘1’
User defined ‘0’
User defined ‘1’
User defined ‘0’
User defined ‘1’
User defined ‘0’
User defined ‘1’
User defined ‘0’
User defined ‘1’
FPGA is configured
FPGA is not configured
See Status LED Definitions
See Status LED Definitions
Table 5 : LED Details See Section Complete Pinout Table for full list of user controlled LED nets and pins
Page 8
Functional Description ad-ug-1385_v1_5.pdf
ADM-PCIE-9V5 User Manual
3.2 Clocking
The ADM-PCIE-9V5 provides flexible reference clock solutions for the many
multi-gigabit transceiver quads and FPGA fabric. Any programmable clock, from
the SI5338 Clock Synthesizer, is re-configurable from the front panel USB
Interface by using Alpha Data’s avr2util utility. This allows the user to
configure almost any arbitrary clock frequency during application run time.
The maximum clock frequency is 312.5MHz. Customers who purchase RD-9V5 also
have the option of embedding IP into their FPGA design that permits
programmable clock re-configuration via PCIe or from within the FPGA.
There is also two available Si5328 jitter attenuator. These can provide clean
and synchronous clocks to the QSFP-DD and OpenCAPI (SlimSAS) quad locations at
many clock frequencies. These devices only use volatile memory, so the FPGA
design will need to re-configure the register map after any power cycle event.
All clock names in the section below can be found in Complete Pinout Table.
J10
(OpenCAPI)
PCIe Edge
U36
(ASFLMPLV100.000MHZ-LR-T)
Buffer NB6N11S
25MHz 30ppm Source
0
Si5338
1
Clock Synth 2
3
Buffer NB6N11S
Buffer NB6N11S
FPGA Bank 64 (LVDS) SI5328_0_REFCLK_IN_P SI5328_0_REFCLK_IN_N
FPGA Bank 64 (LVDS) SI5328_1_REFCLK_IN_P SI5328_1_REFCLK_IN_N
FPGA Bank 64 (LVCMO18) SI5328_1V8_SDA SI5328_1V8_SCL
Crystal 114.285MHz
Crystal 114.285MHz
CLKIN1 Si5328_0 CLKOUT1
CLKIN2
(2.5V VCC)
CLKOUT2
XA/XB I2C
Address: 1101000 CS_CA = CMODE = GND
Other control pins = N/C
CLKIN1 Si5328_1 CLKOUT1
CLKIN2
(2.5V VCC)
CLKOUT2
XA/XB I2C
Address: 1101001 CS_CA = CMODE = GND
Other control pins = N/C
PCIE_REFCLK (MGTREFCLK0_227)
PCIE_LCL_REFCLK (MGTREFCLK1_225)
CAPI_CLK_1 156.25MHz std. MGTREFCLK0_224) CAPI_CLK_2 156.25MHz std.
MGTREFCLK0_225) MGT_PROGCLK_0 156.25 Default (MGTREFCLK0_121)
MGT_PROGCLK_1 156.25 Default (MGTREFCLK0_232) MGT_PROGCLK_2 156.25 Default
(MGTREFCLK0_126) FABRIC_CLK 300MHz Default (IO Bank 66) SI5328_0_OUT_0
(MGTREFCLK1_121) SI5328_0_OUT_1 (MGTREFCLK1_232)
SI5328_1_OUT_0 (MGTREFCLK1_126) SI5328_1_OUT_1 (MGTREFCLK1_224)
Figure 10 : Clock Topology
Functional Description ad-ug-1385_v1_5.pdf
Page 9
ADM-PCIE-9V5 User Manual
GTY Quad 133 X0Y36 – X0Y39
QSFP-DD 2 lanes 4 – 7
SI5328_1_OUT_0 QSFP-DD 2 lanes 0 – 3
MGT_PROG CL K_2
QSFP-DD 3 lanes 4 – 7
GTY Quad 132 X0Y32 – X0Y35
M [LN] 1 GTY Quad 131 X0Y28 – X0Y31
0 L [LN] (RCAL)
GTY Quad 130 X0Y24 – X0Y27
K [LN]
GTY Quad 129 X0Y20 – X0Y23
GTY Quad 128 X0Y16 – X0Y19
QSFP-DD 3 lanes 0 – 3
SI5328_0_OUT_0 QSFP-DD 1 lanes 0 – 3
MGT_PROG CL K_0
QSFP-DD 0 lanes 0 – 3
GTY Quad 127 X0Y12 – X0Y15
J [LS] 1 GTY Quad 126 X0Y8 – X0Y11
0 I [LS] (RCAL)
GTY Quad 125 X0Y4 – X0Y7
H [LS]
GTY Quad 124 X0Y0 – X0Y3
CMA C X0Y5
HP I/O Bank 53 M
HP I/O Bank 73 Q
ILKN X1Y5
PCIE4 X0Y3
HP I/O Bank 52 L
HP I/O Bank 72 P
ILKN X1Y4
CMA C X0Y4
HP I/O Bank 51 K
HP I/O Bank 71 O
SY SMON Configuration
ILKN X0Y3
HP I/O Bank 50 J
HP I/O Bank 70 N
Configuration
CMA C X0Y3
CMA C X0Y2
HP I/O Bank 49
HP I/O Bank 69
SLR Crossing
HP I/O Bank 48
HP I/O Bank 68
PCIE4 X1Y2
ILKN X1Y2
PCIE4 X0Y1
HP I/O Bank 47 I
HP I/O Bank 67 E
ILKN X1Y1
CMA C X0Y1
HP I/O Bank 46 H
HP I/O Bank 66 D
SY SMON Configuration
ILKN X0Y0
CMA C X0Y0
HP I/O Bank 45 G
HP I/O Bank 44 F
HP I/O Bank 65 C
HP I/O Bank 64 B
Configuration
PCIE4 X1Y0 (Tandem)
Key:
Unbonded (not connected to package pins)
GTY Quad 233 X1Y36 X1Y39
G [RN] GTY Quad 232 1 X1Y32 X1Y35
F [RN] 0
GTY Quad 231 X1Y28 X1Y31 E [RN] (RCAL)
QSFP-DD 0 lanes 4 – 7
SI5328_0_OUT_1 QSFP-DD 1 lanes 4 – 7
MGT_PROG CL K_1
FireFly (all 4 lanes)
GTY Quad 230 X1Y24 X1Y27
GTY Quad 229 X1Y20 X1Y23
GTY Quad 228 X1Y16 X1Y19
GTY Quad 227 X1Y12 X1Y15
D [RS] 0
GTY Quad 226 X1Y8 X1Y11 C [RS] (RCAL)
GTY Quad 225 1 X1Y4 X1Y7
B [RS] 0
GTY Quad 224 1 X1Y0 X1Y3
A [RS] 0
PCIe Edge (lanes 0 to 3) PCIE_REFCLK
PCIe Edge (lanes 4 to 7)
PCIE_LCL_REFCLK OpenCAPI (lanes 4 to 7)
CAPI_CLK_2 SI5328_1_OUT_1 OpenCAPI (lanes 0 to 3) CAPI_CLK_1
Figure 11 : VU5P FPGA Clock Location
Page 10
Functional Description ad-ug-1385_v1_5.pdf
ADM-PCIE-9V5 User Manual
GTY Quad 133 X0Y56 – X0Y59
GTY Quad 132 X0Y52 – X0Y55
GTY Quad 131 X0Y48 – X0Y51
(RCAL)
GTY Quad 130 X0Y44 – X0Y47
GTY Quad 129 X0Y40 – X0Y43
GTY Quad 128 X0Y36 – X0Y39
QSFP-DD 2 lanes 4 – 7
SI5328_1_OUT_0 QSFP-DD 2 lanes 0 – 3
MGT_PROG CL K_2
QSFP-DD 3 lanes 4 – 7
GTY Quad 127 X0Y32 – X0Y35
M [LN] 1 GTY Quad 126 X0Y28 – X0Y31
0 L [LN] (RCAL)
GTY Quad 125 X0Y24 – X0Y27
K [LN]
GTY Quad 124 X0Y20 – X0Y23
GTY Quad 123 X0Y16 – X0Y19
QSFP-DD 3 lanes 0 – 3
SI5328_0_OUT_0 QSFP-DD 1 lanes 0 – 3
MGT_PROG CL K_0
QSFP-DD 0 lanes 0 – 3
GTY Quad 122 X0Y12 – X0Y15
J [LS] 1 GTY Quad 121 X0Y8 – X0Y11
0 I [LS] (RCAL)
GTY Quad 120 X0Y4 – X0Y7
H [LS]
GTY Quad 119 X0Y0 – X0Y3
CMA C X0Y8
PCIE4 X0Y5
CMA C X0Y7
ILKN X0Y6
CMA C X0Y6
CMA C X0Y5
PCIE4 X0Y3
CMA C X0Y4
ILKN X0Y3
CMA C X0Y3
CMA C X0Y2
PCIE4 X0Y1
CMA C X0Y1
ILKN X0Y0
CMA C X0Y0
HP I/O Bank 53 HP I/O Bank 52 HP I/O Bank 51 HP I/O Bank 50
HP I/O Bank 73 Q
HP I/O Bank 72 P
HP I/O Bank 71 O
HP I/O Bank 70 N
HP I/O Bank 49
HP I/O Bank 69
SLR Crossing
HP I/O Bank 48 M
HP I/O Bank 68
HP I/O Bank 47 L
HP I/O Bank 67 E
HP I/O Bank 46 K
HP I/O Bank 66 D
HP I/O Bank 45 J
HP I/O Bank 65 C
HP I/O Bank 44
HP I/O Bank 64 B
SLR Crossing
HP I/O Bank 43 I
HP I/O Bank 63
HP I/O Bank 42 H
HP I/O Bank 62
HP I/O Bank 41 G
HP I/O Bank 61
HP I/O Bank 40 F
HP I/O Bank 60
HP I/O Bank 39
HP I/O Bank 59
ILKN X1Y8
ILKN X1Y7
SY SMON Configuration
Configuration
PCIE4 X1Y4
ILKN X1Y5
ILKN X1Y4
SY SMON Configuration
Configuration
PCIE4 X1Y2 (Tandem)
ILKN X1Y2
ILKN X1Y1
SY SMON Configuration
Configuration
PCIE4 X1Y0
Key:
Unbonded (not connected to package pins)
GTY Quad 233 X1Y56 X1Y59
G [RN] GTY Quad 232 1 X1Y52 X1Y55
F [RN] 0
GTY Quad 231 X1Y48 X1Y51 E [RN] (RCAL)
QSFP-DD 0 lanes 4 – 7
SI5328_0_OUT_1 QSFP-DD 1 lanes 4 – 7
MGT_PROG CL K_1
FireFly (all 4 lanes)
GTY Quad 230 X1Y44 X1Y47
GTY Quad 229 X1Y40 X1Y43
GTY Quad 228 X1Y36 X1Y39
GTY Quad 227 X1Y32 X1Y35
D [RS] 0
GTY Quad 226 X1Y28 X1Y31 C [RS] (RCAL)
GTY Quad 225 1 X1Y24 X1Y27
B [RS] 0
GTY Quad 224 1 X1Y20 X1Y23
A {RS] 0
PCIe Edge (lanes 0 to 3) PCIE_REFCLK
PCIe Edge (lanes 4 to 7)
PCIE_LCL_REFCLK OpenCAPI (lanes 4 to 7)
CAPI_CLK_2 SI5328_1_OUT_1 OpenCAPI (lanes 0 to 3) CAPI_CLK_1
GTY Quad 223 X1Y16 X1Y19
GTY Quad 222 X1Y12 X1Y15
GTY Quad 221 X1Y8 X1Y11
(RCAL)
GTY Quad 220 X1Y4 X1Y7
GTY Quad 219 X1Y0 X1Y3
Figure 12 : VU9P FPGA Clock Location
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ADM-PCIE-9V5 User Manual
3.2.1 Si5328
If jitter attenuation is required please see the reference documentation for
the Si5328.
https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5328.pdf The
circuit connections mirror the Xilinx VCU108 Development Kits (page 57 of the
schematic, component U57). The MGT RXOUTCLK can be used to pass a recovered
clock to the FPGA fabric. Please refer to Xilinx UG578 and the VCU108 for more
information. The CLKIN2 input of the SI5328, provided by the SI5338, is only
available in rev2 PCBs and onward (Serial number greater than 109).
3.2.2 PCIe Reference Clocks
The 8 MGT lanes connected to the PCIe card edge use MGT tiles 226 through 227
and use the system 100 MHz clock (net name PCIE_REFCLK). Alternatively, a
clean, onboard 100MHz clock is available as well (net name PCIE_LCL_REFCLK).
3.2.3 Fabric Clock
The design offers a fabric clock (net name FABRICCLK) which defaults to 300
MHz. This clock is intended to be used for IDELAY elements in FPGA designs.
The fabric clock is connected to a Global Clock (GC) pin. DIFF_TERM_ADV =
TERM_100 is required for LVDS termination
3.2.4 Programming Clock (EMCCLK)
A 100MHz clock (net name EMCCLK_B) is fed into the EMCCLK pin to drive the SPI
flash device during configuration of the FPGA. Note that this is not a global
clock capable IO pin.
3.2.5 QSFP-DD Clock
The QSFP-DD clocks have a default 156.25MHz reference clock. Note that this
clock frequency can be changed to any arbitrary clock frequency up to 312MHz
by re-programing the Si5338 reprogrammable clock oscillator. See details on
avr2util in the section: USB Interface. See net names MGTPROGCLK for pin
locations. The QSFP-DD cages are also located such that they can be clocked
from the Si5328 jitter attenuators. See net names SI5328OUT for pin
locations.
3.2.6 Ultraport SlimSAS (OpenCAPI)
The Ultraport SlimSAS connector is located in MGT tile 224 and 225. For
OpenCAPI an external 156.25MHz clock is provided over the cable. See net names
CAPICLK for cable clock pin locations. Another alternative clock source for
this interface is the PCIE_LCL_REFCLK clock synthesizer at 100MHz. For jitter
sensitive applications, this interface can be clocked from the Si5328 jitter
attenuator. See net names SI5328OUT* for pin locations.
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ADM-PCIE-9V5 User Manual
3.3 PCI Express
The ADM-PCIE-9V5 is capable of PCIe Gen 3 with 8 lanes. The FPGA drives these
lanes directly using the Integrated PCI Express block from Xilinx. Negotiation
of PCIe link speed and number of lanes used is generally automatic and does
not require user intervention. PCI Express reset (PERST#) connected to the
FPGA through a buffer. See Complete Pinout Table signal PERST0_1V8_L. The
other pin assignments for the high speed lanes are provided in the pinout
attached to the Complete Pinout Table The PCI Express specification requires
that all add-in cards be ready for enumeration within 120ms after power is
valid (100ms after power is valid + 20ms after PERST is released). The ADM-
PCIE-9V5 does meet this requirement when configured from a tandem bitstream
with the proper SPI constraints detailed in the section: Configuration From
Flash Memory. For more details on tandem configuration, see Xilinx xapp 1179.
Note: Different motherboards/backplanes will benefit from different RX
equalization schemes within the PCIe IP core provided by Xilinx. Alpha Data
recommends using the following setting if a user experiences link errors or
training issues with their system: within the IP core generator, change the
mode to “Advanced” and open the “GT Settings” tab, change the “form factor
driven insertion loss adjustment” from “Add-in Card” to “Chip-to-Chip” (See
Xilinx PG195, PG213, and PG239 for more details).
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ADM-PCIE-9V5 User Manual
3.4 QSFP-DD
Four QSFP-DD cages are available at the front panel. These cages are capable
of housing either QSFP28 or QSFP-DD cables (backwards compatible). Both active
optical and passive copper QSFP-DD/QSFP28 compatible models are fully
compliant. The communication interface can run at up to 28Gbps per channel.
Each QSFP-DD cage has 8 channels (total maximum bandwidth of 224Gbps per
cage). This cage is ideally suited for 8x 10G/25G, 2x 100G Ethernet, or any
other protocol supported by the Xilinx GTY Transceivers. Please see Xilinx
User Guide UG578 for more details on the capabilities of the transceivers. All
QSFP-DD cages have control signals connected to the FPGA. Their connectivity
is detailed in the Complete Pinout Table at the end of this document. The
notation used in the pin assignments is QSFP_0, QSFP_1, QSFP_2, and
QSFP_3, with locations clarified in the diagram below. The Management
Interface of each QSFP-DD cage is connected to the FPGA, as detailed in
Complete Pinout Table. The available signals are SDA/SCL (I2C), INT_L
(interrupt), LPMODE (low power mode), RST_L (reset), and MODPRS_L (module
present).
Note: The LPMODE (Low Power Mode) to the cage is pulled up by default. The
FPGA can either (a) drive the relevant LPMODE pin low or (b) issue I2C
transactions in order to power-up a given QSFP-DD/QSFP28 module
Figure 13 : QSFP-DD Location
It is possible for Alpha Data to pre-fit the ADM-PCIE-9V5 with QSFP-DD and
QSFP28 components. Please contact [email protected] for full details and
options.
Alpha Data has tested the ADM-PCIE-9V5 with an array of passive cables from
multiple manufacturers. Please contact [email protected] for more details
on appropriate and available cables. Cable types include: QSFP-DD to 8x SFP,
QSFP-DD to 2x QSFP, and QSFP-DD to QSFP-DD.
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3.5 OpenCAPI Ultraport SlimSAS
An Ultraport SlimSAS receptacle along the back of the board allows for
OpenCAPI compliant interfaces running at 200G (8 channels at 25G). Please
contact [email protected] or your IBM representative for more details on
OpenCAPI and its benefits. The SlimSAS connector can also be used to connect
multiple ADM-PCIE-9V5 cards within a chassis.
Figure 14 : OpenCAPI Location
CAPI_RX1_P CAPI_RX1_N CAPI_RX3_P CAPI_RX3_N
CAPI_RX4_P CAPI_RX4_N CAPI_RX6_P CAPI_RX6_N
CAPI_TX6_P CAPI_TX6_N CAPI_TX4_P CAPI_TX4_N
CAPI_TX3_P CAPI_TX3_N CAPI_TX1_P CAPI_TX1_N CAPI_TX0_P CAPI_TX0_N
C428 47nF C424 47nF C423 47nF C422 47nF
C418 47nF C413 47nF C408 47nF C407 47nF CAPI_I2C_SCL CAPI_I2C_SDA
C399 47nF C397 47nF C392 47nF C391 47nF
C378 47nF C366 47nF C363 47nF C358 47nF C356 47nF C354 47nF
A1 25V A2 25V A3
A4 25V A5 25V A6
A7 A8 A9 A10 25V A11 25V A12 A13 25V A14 25V A15 A16 A17 A18 A19 25V A20 25V
A21 A22 25V A23 25V A24 A25 A26 A27 A28 25V A29 25V A30 A31 25V A32 25V A33
A34 25V A35 25V A36 A37 MH1 MH2
J10
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 MH1 MH2
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 MH3 MH4
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 MH3 MH4
C115 47nF 25V C112 47nF 25V C110 47nF 25V C105 47nF 25V
C104 47nF 25V C102 47nF 25V C101 47nF 25V C99 47nF 25V
CAPI_PRE_DETECT
C96 47nF 25V C95 47nF 25V C94 47nF 25V C92 47nF 25V CAPI_CLK_0_P CAPI_CLK_0_N
C83 47nF 25V C82 47nF 25V
GND
U10-J074-242T
GND
CAPI_RX0_P CAPI_RX0_N CAPI_RX2_P CAPI_RX2_N
CAPI_RX5_P CAPI_RX5_N CAPI_RX7_P CAPI_RX7_N
CAPI_INT/RESET CAPI_TX7_P CAPI_TX7_N CAPI_TX5_P CAPI_TX5_N
CAPI_TX2_P CAPI_TX2_N
Figure 15 : OpenCAPI Pinout
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ADM-PCIE-9V5 User Manual
3.6 System Monitor
The ADM-PCIE-9V5 has the ability to monitor its own temperature and the
voltages and currents of certain power supply rails, in order to provide an
indication of board health. The monitoring is implemented using an Atmel AVR
microcontroller.
If the core FPGA temperature exceeds 105 degrees Celsius, the FPGA will be
cleared to prevent damage to the card.
The microcontroller monitors power supply rail voltages & currents and
temperatures at certain points on the board. This information can be read out
via USB using the avr2util utility, and also via PCIe if RD-9V5 is purchased.
Monitors ETC EC 12V_AUX 12V_AUX_I 12V_EDGE 12V_EDGE_I 3V3_EDGE 3V3_AUX 3V3_DIG
2V5_CLK 1V8_DIG 1V8_MGT_AUX 1V2_AVTT 0V9_AVCC
VCC_INT
GND uC_Temp Board0_Temp Board1_Temp FPGA_Temp
Identifier Purpose/Description
ETC
Elapsed time counter (seconds)
EC
Event counter (power cycles)
ADC00 ADC01 ADC02 ADC03 ADC04
12v board input supply from 6-pin ATX Cable 12V input current from 6-pin ATX Cable in amps 12V board input supply from PCIe Edge 12V board input current from PCIe Edge in amps 3.3V board input supply from PCIe edge (unused)
ADC05 3.3V auxilary board input supply from PCIE edge
ADC06 3.3V generated onboard for QSFP optics
ADC07 ADC08 ADC09 ADC10 ADC11
2.5V generated onboard for clock circuitry 1.8V generated onboard fpr FPGA IO voltage (VCCO) 1.8V generated onboard for transceiver power (AVCC_AUX) 1.2V generated onboard for transceiver Power (AVTT) 0.9V generated onboard for transceiver Power (AVCC)
ADC12
0.85-0.90V generated onboard for VccINT + VccBRAM + VccINT_IO
ADC13 0V electrical ground
TMP00 TMP01 TMP02 TMP03
uC on-die temperature Board temperature near front panel (U3) Board temperature near back edge (U23) FPGA on-die temperature
Table 6 : Voltage, Current, and Temperature Monitors
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ADM-PCIE-9V5 User Manual
3.6.1 System Monitor Status LEDs
LEDs D5 (Red) and D7 (Green) indicate the card health status.
LEDs Green Green + Red Flashing Green + Flashing Red (together) Flashing Green
- Flashing Red (alternating) Flashing Green + Red
Red
Flashing Red
Status Running and no alarms Standby (Powered off)
Attention – critical alarm active
Service Mode
Attention – alarm active Missing application firmware or invalid firmware FPGA
configuration cleared to protect board
Table 7 : Status LED Definitions
3.6.2 Fan Controllers
The onboard USB bus controlled by the system monitor has access to a MAX6620
fan controller. This device can be controlled through the multiple onboard
system monitor communication interfaces, including USB, PCIe Edge SMBUS, and
FPGA sysmon seral communication port. The fan controller is on I2C bus 1 at
address 0x2a. For additional questions. Contact [email protected] with
additional questions on utilizing these controllers.
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3.7 USB Interface
The FPGA can be configured directly from the USB connection on either the
front panel or the rear card edge. The ADM-PCIE-9V5 utilizes the Digilent USB-
JTAG converter box which is supported by the Xilinx software tool suite.
Simply connect a micro-USB AB type cable between the ADM-PCIE-9V5 USB port and
a host computer with Vivado installed. Vivado Hardware Manager will
automatically recognize the FPGA and allow you to configure the FPGA and the
SPI configuration Flash memory.
The same USB connector is used to directly access the system monitor system.
All voltages, currents, temperatures, and non-volatile clock configuration
settings can be accessed using Alpha Data’s avr2util software at this
interface.
Avr2util for Windows and the associated USB driver is downloadable here:
https://support.alpha-data.com/pub/firmware/utilities/windows/
Avr2util for Linux is downloadable here: https://support.alpha-
data.com/pub/firmware/utilities/linux/
Use “avr2util.exe /?” to see all options.
For example “avr2util.exe /usbcom com4 display-sensors” will display all
sensor values.
For example “avr2util.exe /usbcom com4 setclknv 1 100000000” will set the
MGT_PROGCLK_1 100MHz. setclk index 0 = MGT_PROGCLK_1, index 1 = MGT_PROGCLK_1,
index 2 = MGT_PROGCLK_2, index 3 = FABRIC_CLK.
Change ‘com4’ to match the com port number assigned under windows device
manager.
3.8 Configuration
There are two main ways of configuring the FPGA on the ADM-PCIE-9V5: · From
Flash memory, at power-on, as described in Section 3.8.1
· Using USB cable connected at either USB port Section 3.8.2
3.8.1 Configuration From Flash Memory
The FPGA can be automatically configured at power-on from two 1 Gbit QSPI
flash memory device configured as an x8 SPI device (Micron part numbers
MT25QU01GBBB8E12-0). These flash devices are typically divided into two
regions of 128 MiByte each, where each region is sufficiently large to hold an
uncompressed bitstream for a VU5P or VU9P FPGA.
The ADM-PCIE-9V5 is shipped with a simple PCIe endpoint bitstream which should
be visible to the operating system (using e.g. Windows Device Manager or
“lspci” in Linux) in order to provided confidence that the card is working
correctly when installed in a system. On request, Alpha Data can pre-load
custom bitstreams during production test. Please contact [email protected]
in order to discuss this possibility.
It is possible to use Multiboot with a fallback image on this hardware. The
master SPI configuration interface and the Fallback MultiBoot are discussed in
detail in Xilinx UG570.
At power-on, the FPGA attempts to configure itself automatically in SPI master
mode, depending on the header of the bitstream that has been flashed into the
card. This normally results in SPIx8 configuration at EMCCLK frequency. The
configuration scheme used in the ADM-PCIE-9V5 is compatible with Multiboot;
see Xilinx UG570 for details. The FPGA can also be made to reconfigure itself
from an arbitrary Flash address using the ICAPE3 primitive; this is also
described in Xilinx UG570.
The image loaded can also support tandem PROM or tandem PCIE with field update
configuration methods. These options reduce power-on load times to help meet
the PCIe reset timing requirements. Tandem with field also enables a host
system to reconfigure the user FPGA logic without losing the PCIe link, a
useful feature when system resets and power cycles are not an option.
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ADM-PCIE-9V5 User Manual
The Alpha Data System Monitor is also capable of reconfiguring the flash
memory and reprograming the FPGA. This provides a useful failsafe mechanism to
re-program the FPGA even if it drops off the PCIe bus. The system monitor can
be accessed with avr2util over USB at the front panel and rear edge.
3.8.1.1 Building and Programming Configuration Images
Generate a bitfile with these constraints (see xapp1233): · set_property
BITSTREAM.GENERAL.COMPRESS TRUE [ current_design ] · set_property
BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] · set_property
BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] · set_property
BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] · set_property
BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] · set_property
BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design] · set_property CFGBVS
GND [ current_design ] · set_property CONFIG_VOLTAGE 1.8 [ current_design ] ·
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
Generate an MCS file with these properties (write_cfgmem): · -format MCS ·
-size 256 · -interface SPIx8 · -loadbit “up 0x0000000
<directory/to/file/filename.bit>” (0th location) Program with vivado hardware
manager with these settings (see xapp1233): · SPI part: mt25qu01g-spi-
x1_x2_x4_x8 · State of non-config mem I/O pins: Pull-none
3.8.2 Configuration via JTAG
A micro-USB AB Cable may be attached to the front panel or rear edge USB port.
This permits the FPGA to be reconfigured using the Xilinx Vivado Hardware
Manager via the integrated Digilent JTAG converter box. The device will be
automatically recognized in Vivado Hardware Manager.
For more detailed instructions, please see “Using a Vivado Hardware Manager to
Program an FPGA Device” section of Xilinx UG908:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ ug908
-vivado-programming-debugging.pdf
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ADM-PCIE-9V5 User Manual
3.9 GPIO Connector
The GPIO option consists of a versatile shrouded connector from Molex with
part number 87832-1222. This connector gives users eight signals connected to
the FPGA. Recommended mating plug: Molex 0875681273 or 0511101260
Figure 16 : GPIO Connector Schematic
Figure 17 : GPIO Connector Location
3.9.1 Direct Connect FPGA Signals
8 nets are broken out to the GPIO header, as four sets of differential pairs.
These signal are suitable for any 1.8V signalling standards supported by the
Xilinx UltraScale architecture. See Xilinx UG571 for IO options. LVDS and 1.8
CMOS are popular options. The 0th GPIO signal index is suitable for a global
clock connection.
The direct connect GPIO signals are limited to 1.8V by a quickswitch
(74CBTLVD3245PW) in order to protect the FPGA from overvoltage on IO pins.
This quickswitch allows the signals to travel in either direction with only 4
ohms of series impedance and less than 1ns of propagation delay. The nets are
directly connected to the FPGA after the quickswitch.
Direct connect signal names are labeled GPIO_0_1V8_P/N and GPIO_1_1V8_P/N,
etc. to show polarity and grouping. The signal pin allocations can be found in
Complete Pinout Table
3.9.2 Timing Input
Pins 1 and 2 of J1 can be used as an isolated timing input signal (up to
25MHz). Applications can either directly connect to the GPIO connector, or
Alpha Data can provide a cabled solution with an SMA or similar connector on
the front panel. Contact [email protected] for front panel connector
options.
For pin locations, see signal name ISO_CLK in Complete Pinout Table.
Page 20
Functional Description ad-ug-1385_v1_5.pdf
ADM-PCIE-9V5 User Manual The signal is isolated through a optical isolator part number TLP2367 with 220 ohm of series resistance.
Functional Description ad-ug-1385_v1_5.pdf
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ADM-PCIE-9V5 User Manual
3.10 User EEPROM
A 2Kb I2C user EEPROM is provided for storing MAC addresses or other user
information. The EEPROM is part number CAT34C02HU4IGT4A The address pins A2,
A1, and A0 are all strapped to a logical ‘0’. Write protect (WP), Serial Clock
(SCL), and Serial Data (SDA) pin assignments can be found in Complete Pinout
Table with the names SPARE_WP, SPARE_SCL, and SPARE_SDA respectively. WP, SDA,
and SCL signals all have external pull-up resistors on the card.
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Appendix A: Complete Pinout Table
Pin Number
BF12 BD12 BC8 BE12 BC9 BF11 AR8 AR9 AL8 AL9 BE24 BF24 BC23 BB1 BB2 AY1 AY2 AV1
AV2 AT1 AT2 AP1 AP2 AM1 AM2 AK1 AK2 AJ3 AJ4 BE4 BE5 BC4 BC5
Signal Name
Pin Name
Bank Voltage
AVR_B2U_1V8
IO_L2P_T0L_N2_66
AVR_HS_B2U_1V8
IO_L1P_T0L_N0_DBC_66
AVR_HS_CLK_1V8
IO_L12N_T1U_N11_GC_66
AVR_HS_U2B_1V8
IO_L1N_T0L_N1_DBC_66
AVR_MON_CLK_1V8
IO_L12P_T1U_N10_GC_66
AVR_U2B_1V8
IO_L2N_T0L_N3_66
CAPI_CLK_1_PIN_N
MGTREFCLK0N_224
CAPI_CLK_1_PIN_P
MGTREFCLK0P_224
CAPI_CLK_2_PIN_N
MGTREFCLK0N_225
CAPI_CLK_2_PIN_P
MGTREFCLK0P_225
CAPI_I2C_SCL_1V8
IO_L1P_T0L_N0_DBC_64
CAPI_I2C_SDA_1V8
IO_L1N_T0L_N1_DBC_64
CAPI_INT/RESET_1V8
IO_L2P_T0L_N2_64
CAPI_RX0_N
MGTYRXN0_224
CAPI_RX0_P
MGTYRXP0_224
CAPI_RX1_N
MGTYRXN1_224
CAPI_RX1_P
MGTYRXP1_224
CAPI_RX2_N
MGTYRXN2_224
CAPI_RX2_P
MGTYRXP2_224
CAPI_RX3_N
MGTYRXN3_224
CAPI_RX3_P
MGTYRXP3_224
CAPI_RX4_N
MGTYRXN0_225
CAPI_RX4_P
MGTYRXP0_225
CAPI_RX5_N
MGTYRXN1_225
CAPI_RX5_P
MGTYRXP1_225
CAPI_RX6_N
MGTYRXN2_225
CAPI_RX6_P
MGTYRXP2_225
CAPI_RX7_N
MGTYRXN3_225
CAPI_RX7_P
MGTYRXP3_225
CAPI_TX0_N
MGTYTXN0_224
CAPI_TX0_P
MGTYTXP0_224
CAPI_TX1_N
MGTYTXN1_224
CAPI_TX1_P
MGTYTXP1_224
Table 8 : Complete Pinout Table (continued on next page)
1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8
(LVCMOS18)
MGT REFCLK MGT REFCLK MGT REFCLK MGT REFCLK 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8
(LVCMOS18)
MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT
MGT
Complete Pinout Table ad-ug-1385_v1_5.pdf
Page 23
ADM-PCIE-9V5 User Manual
Pin Number
BA4 BA5 AW4 AW5 AU4 AU5 AT6 AT7 AR4 AR5 AP6 AP7 AF13 AE12 AL20
BA9
AY9
G22 R21 G21 Y1 Y2 W3 W4 V1 V2 U3 U4 H22 H23 V6 V7 T6 T7
Signal Name
Pin Name
Bank Voltage
CAPI_TX2_N
MGTYTXN2_224
MGT
CAPI_TX2_P
MGTYTXP2_224
MGT
CAPI_TX3_N
MGTYTXN3_224
MGT
CAPI_TX3_P
MGTYTXP3_224
MGT
CAPI_TX4_N
MGTYTXN0_225
MGT
CAPI_TX4_P
MGTYTXP0_225
MGT
CAPI_TX5_N
MGTYTXN1_225
MGT
CAPI_TX5_P
MGTYTXP1_225
MGT
CAPI_TX6_N
MGTYTXN2_225
MGT
CAPI_TX6_P
MGTYTXP2_225
MGT
CAPI_TX7_N
MGTYTXN3_225
MGT
CAPI_TX7_P
MGTYTXP3_225
MGT
CCLK
CCLK_0
1.8 (LVCMOS18)
DONE_1V8
DONE_0
1.8 (LVCMOS18)
EMCCLK_B
IO_L24P_T3U_N10_EMCCLK_65
1.8 (LVCMOS18)
FABRIC_CLK_PIN_N
IO_L13N_T2L_N1_GC_QBC_66
1.8 (LVDS with DIFF_TERM_ADV)
FABRIC_CLK_PIN_P
IO_L13P_T2L_N0_GC_QBC_66
1.8 (LVDS with DIFF_TERM_ADV)
FIREFLY_INT_1V8_L
IO_L13P_T2L_N0_GC_QBC_72
1.8 (LVCMOS18)
FIREFLY_MODPRS_L
IO_L3P_T0L_N4_AD15P_72
1.8 (LVCMOS18)
FIREFLY_RST_1V8_L
IO_L13N_T2L_N1_GC_QBC_72
1.8 (LVCMOS18)
FIREFLY_RX0_N
MGTYRXN0_231
MGT
FIREFLY_RX0_P
MGTYRXP0_231
MGT
FIREFLY_RX1_N
MGTYRXN1_231
MGT
FIREFLY_RX1_P
MGTYRXP1_231
MGT
FIREFLY_RX2_N
MGTYRXN2_231
MGT
FIREFLY_RX2_P
MGTYRXP2_231
MGT
FIREFLY_RX3_N
MGTYRXN3_231
MGT
FIREFLY_RX3_P
MGTYRXP3_231
MGT
FIREFLY_SCL_1V8
IO_L14N_T2L_N3_GC_72
1.8 (LVCMOS18)
FIREFLY_SDA_1V8
IO_L14P_T2L_N2_GC_72
1.8 (LVCMOS18)
FIREFLY_TX0_N
MGTYTXN0_231
MGT
FIREFLY_TX0_P
MGTYTXP0_231
MGT
FIREFLY_TX1_N
MGTYTXN1_231
MGT
FIREFLY_TX1_P
MGTYTXP1_231
Table 8 : Complete Pinout Table (continued on next page)
MGT
Page 24
Complete Pinout Table ad-ug-1385_v1_5.pdf
ADM-PCIE-9V5 User Manual
Pin Number
P6 P7 M6 M7 AJ11 BF16 AP11 AN11 AM11 AL11
AM19
AM18
AN20 AP20 AV23 AU23 AV21 AU21 AV24 AU24 AR22 AR23 AC12 AT22 AK39 AK38
R8 R9 V39 V38 AJ8 AJ9 AC8 AC9
Signal Name
Pin Name
Bank Voltage
FIREFLY_TX2_N
MGTYTXN2_231
MGT
FIREFLY_TX2_P
MGTYTXP2_231
MGT
FIREFLY_TX3_N
MGTYTXN3_231
MGT
FIREFLY_TX3_P
MGTYTXP3_231
MGT
FPGA_FLASH_CE0_L
RDWR_FCS_B_0
1.8 (LVCMOS18)
FPGA_FLASH_CE1_L
IO_L2N_T0L_N3_FWE_FCS2_B_65
1.8 (LVCMOS18)
FPGA_FLASH_DQ0
D00_MOSI_0
1.8 (LVCMOS18)
FPGA_FLASH_DQ1
D01_DIN_0
1.8 (LVCMOS18)
FPGA_FLASH_DQ2
D02_0
1.8 (LVCMOS18)
FPGA_FLASH_DQ3
D03_0
1.8 (LVCMOS18)
FPGA_FLASH_DQ4
IO_L22P_T3U_N6_DBC_AD0P _D04_65
1.8 (LVCMOS18)
FPGA_FLASH_DQ5
IO_L22N_T3U_N7_DBC_AD0N _D05_65
1.8 (LVCMOS18)
FPGA_FLASH_DQ6
IO_L21P_T3L_N4_AD8P_D06_65
1.8 (LVCMOS18)
FPGA_FLASH_DQ7
IO_L21N_T3L_N5_AD8N_D07_65
1.8 (LVCMOS18)
GPIO_0_1V8_N
IO_L14N_T2L_N3_GC_64
1.8 (LVCMOS18or LVDS)
GPIO_0_1V8_P
IO_L14P_T2L_N2_GC_64
1.8 (LVCMOS18or LVDS)
GPIO_1_1V8_N
IO_L15N_T2L_N5_AD11N_64
1.8 (LVCMOS18or LVDS)
GPIO_1_1V8_P
IO_L15P_T2L_N4_AD11P_64
1.8 (LVCMOS18or LVDS)
GPIO_2_1V8_N
IO_L16N_T2U_N7_QBC_AD3N_64 1.8 (LVCMOS18or LVDS)
GPIO_2_1V8_P
IO_L16P_T2U_N6_QBC_AD3P_64 1.8 (LVCMOS18or LVDS)
GPIO_3_1V8_N
IO_L17N_T2U_N9_AD10N_64
1.8 (LVCMOS18or LVDS)
GPIO_3_1V8_P
IO_L17P_T2U_N8_AD10P_64
1.8 (LVCMOS18or LVDS)
INIT_B_1V8
INIT_B_0
1.8 (LVCMOS18)
ISO_CLK_1V8
IO_L13P_T2L_N0_GC_QBC_64
1.8 (LVCMOS18)
MGT_PROGCLK_0_PIN_N
MGTREFCLK0N_121
MGT REFCLK
MGT_PROGCLK_0_PIN_P
MGTREFCLK0P_121
MGT REFCLK
MGT_PROGCLK_1_PIN_N
MGTREFCLK0N_232
MGT REFCLK
MGT_PROGCLK_1_PIN_P
MGTREFCLK0P_232
MGT REFCLK
MGT_PROGCLK_2_PIN_N
MGTREFCLK0N_126
MGT REFCLK
MGT_PROGCLK_2_PIN_P
MGTREFCLK0P_126
MGT REFCLK
PCIE_LCL_REFCLK_PIN_N
MGTREFCLK1N_225
MGT REFCLK
PCIE_LCL_REFCLK_PIN_P
MGTREFCLK1P_225
MGT REFCLK
PCIE_REFCLK_PIN_N
MGTREFCLK0N_227
MGT REFCLK
PCIE_REFCLK_PIN_P
MGTREFCLK0P_227
Table 8 : Complete Pinout Table (continued on next page)
MGT REFCLK
Complete Pinout Table ad-ug-1385_v1_5.pdf
Page 25
ADM-PCIE-9V5 User Manual
Pin Number
AA3 AA4 AB1 AB2 AC3 AC4 AD1 AD2 AE3 AE4 AF1 AF2 AG3 AG4 AH1 AH2 Y6 Y7 AB6 AB7
AD6 AD7 AF6 AF7 AH6 AH7 AK6 AK7 AM6 AM7 AN4 AN5 AM17 AH11 T23 P22
Signal Name
Pin Name
Bank Voltage
PCIE_RX0_N
MGTYRXN3_227
PCIE_RX0_P
MGTYRXP3_227
PCIE_RX1_N
MGTYRXN2_227
PCIE_RX1_P
MGTYRXP2_227
PCIE_RX2_N
MGTYRXN1_227
PCIE_RX2_P
MGTYRXP1_227
PCIE_RX3_N
MGTYRXN0_227
PCIE_RX3_P
MGTYRXP0_227
PCIE_RX4_N
MGTYRXN3_226
PCIE_RX4_P
MGTYRXP3_226
PCIE_RX5_N
MGTYRXN2_226
PCIE_RX5_P
MGTYRXP2_226
PCIE_RX6_N
MGTYRXN1_226
PCIE_RX6_P
MGTYRXP1_226
PCIE_RX7_N
MGTYRXN0_226
PCIE_RX7_P
MGTYRXP0_226
PCIE_TX0_PIN_N
MGTYTXN3_227
PCIE_TX0_PIN_P
MGTYTXP3_227
PCIE_TX1_PIN_N
MGTYTXN2_227
PCIE_TX1_PIN_P
MGTYTXP2_227
PCIE_TX2_PIN_N
MGTYTXN1_227
PCIE_TX2_PIN_P
MGTYTXP1_227
PCIE_TX3_PIN_N
MGTYTXN0_227
PCIE_TX3_PIN_P
MGTYTXP0_227
PCIE_TX4_PIN_N
MGTYTXN3_226
PCIE_TX4_PIN_P
MGTYTXP3_226
PCIE_TX5_PIN_N
MGTYTXN2_226
PCIE_TX5_PIN_P
MGTYTXP2_226
PCIE_TX6_PIN_N
MGTYTXN1_226
PCIE_TX6_PIN_P
MGTYTXP1_226
PCIE_TX7_PIN_N
MGTYTXN0_226
PCIE_TX7_PIN_P
MGTYTXP0_226
PERST0_1V8_L
IO_T3U_N12_PERSTN0_65
PROGRAM_B_1V8
PROGRAM_B_0
QSFP_0_INT_1V8_L
IO_L6P_T0U_N10_AD6P_72
QSFP_0_LPMODE_1V8
IO_L5N_T0U_N9_AD14N_72
Table 8 : Complete Pinout Table (continued on next page)
MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18)
Page 26
Complete Pinout Table ad-ug-1385_v1_5.pdf
ADM-PCIE-9V5 User Manual
Pin Number
P20 R22 BC46 BC45 BA46 BA45 AW46 AW45 AU46 AU45 K1 K2 H1 H2 F1 F2 D1 D2 N22
M22 BD43 BD42 BB43 BB42 AY43 AY42 AV43 AV42 G4 G5 F6 F7 E4 E5 C4 C5
Signal Name
Pin Name
Bank Voltage
QSFP_0_MODPRS_L
IO_L1P_T0L_N0_DBC_72
QSFP_0_RST_1V8_L
IO_L5P_T0U_N8_AD14P_72
QSFP_0_RX0_N
MGTYRXN0_120
QSFP_0_RX0_P
MGTYRXP0_120
QSFP_0_RX1_N
MGTYRXN1_120
QSFP_0_RX1_P
MGTYRXP1_120
QSFP_0_RX2_N
MGTYRXN2_120
QSFP_0_RX2_P
MGTYRXP2_120
QSFP_0_RX3_N
MGTYRXN3_120
QSFP_0_RX3_P
MGTYRXP3_120
QSFP_0_RX4_N
MGTYRXN0_233
QSFP_0_RX4_P
MGTYRXP0_233
QSFP_0_RX5_N
MGTYRXN1_233
QSFP_0_RX5_P
MGTYRXP1_233
QSFP_0_RX6_N
MGTYRXN2_233
QSFP_0_RX6_P
MGTYRXP2_233
QSFP_0_RX7_N
MGTYRXN3_233
QSFP_0_RX7_P
MGTYRXP3_233
QSFP_0_SCL_1V8
IO_L4P_T0U_N6_DBC_AD7P_72
QSFP_0_SDA_1V8
IO_L4N_T0U_N7_DBC_AD7N_72
QSFP_0_TX0_N
MGTYTXN0_120
QSFP_0_TX0_P
MGTYTXP0_120
QSFP_0_TX1_N
MGTYTXN1_120
QSFP_0_TX1_P
MGTYTXP1_120
QSFP_0_TX2_N
MGTYTXN2_120
QSFP_0_TX2_P
MGTYTXP2_120
QSFP_0_TX3_N
MGTYTXN3_120
QSFP_0_TX3_P
MGTYTXP3_120
QSFP_0_TX4_N
MGTYTXN0_233
QSFP_0_TX4_P
MGTYTXP0_233
QSFP_0_TX5_N
MGTYTXN1_233
QSFP_0_TX5_P
MGTYTXP1_233
QSFP_0_TX6_N
MGTYTXN2_233
QSFP_0_TX6_P
MGTYTXP2_233
QSFP_0_TX7_N
MGTYTXN3_233
QSFP_0_TX7_P
MGTYTXP3_233
Table 8 : Complete Pinout Table (continued on next page)
1.8 (LVCMOS18) 1.8 (LVCMOS18)
MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18)
1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT
Complete Pinout Table ad-ug-1385_v1_5.pdf
Page 27
ADM-PCIE-9V5 User Manual
Pin Number
K24 K23 N20 L23 AR46 AR45 AN46 AN45 AL46 AL45 AJ46 AJ45 T1 T2 R3 R4 P1 P2 M1
M2 R23 T21 AT43 AT42 AP43 AP42 AM43 AM42 AL41 AL40 L4 L5 K6 K7 J4 J5
Signal Name
Pin Name
Bank Voltage
QSFP_1_INT_1V8_L
IO_L8P_T1L_N2_AD5P_72
QSFP_1_LPMODE_1V8 IO_L7N_T1L_N1_QBC_AD13N_72
QSFP_1_MODPRS_L
IO_L1N_T0L_N1_DBC_72
QSFP_1_RST_1V8_L
IO_L7P_T1L_N0_QBC_AD13P_72
QSFP_1_RX0_N
MGTYRXN0_121
QSFP_1_RX0_P
MGTYRXP0_121
QSFP_1_RX1_N
MGTYRXN1_121
QSFP_1_RX1_P
MGTYRXP1_121
QSFP_1_RX2_N
MGTYRXN2_121
QSFP_1_RX2_P
MGTYRXP2_121
QSFP_1_RX3_N
MGTYRXN3_121
QSFP_1_RX3_P
MGTYRXP3_121
QSFP_1_RX4_N
MGTYRXN0_232
QSFP_1_RX4_P
MGTYRXP0_232
QSFP_1_RX5_N
MGTYRXN1_232
QSFP_1_RX5_P
MGTYRXP1_232
QSFP_1_RX6_N
MGTYRXN2_232
QSFP_1_RX6_P
MGTYRXP2_232
QSFP_1_RX7_N
MGTYRXN3_232
QSFP_1_RX7_P
MGTYRXP3_232
QSFP_1_SCL_1V8
IO_L6N_T0U_N11_AD6N_72
QSFP_1_SDA_1V8
IO_T0U_N12_VRP_72
QSFP_1_TX0_N
MGTYTXN0_121
QSFP_1_TX0_P
MGTYTXP0_121
QSFP_1_TX1_N
MGTYTXN1_121
QSFP_1_TX1_P
MGTYTXP1_121
QSFP_1_TX2_N
MGTYTXN2_121
QSFP_1_TX2_P
MGTYTXP2_121
QSFP_1_TX3_N
MGTYTXN3_121
QSFP_1_TX3_P
MGTYTXP3_121
QSFP_1_TX4_N
MGTYTXN0_232
QSFP_1_TX4_P
MGTYTXP0_232
QSFP_1_TX5_N
MGTYTXN1_232
QSFP_1_TX5_P
MGTYTXP1_232
QSFP_1_TX6_N
MGTYTXN2_232
QSFP_1_TX6_P
MGTYTXP2_232
Table 8 : Complete Pinout Table (continued on next page)
1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18)
MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18)
1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT
Page 28
Complete Pinout Table ad-ug-1385_v1_5.pdf
ADM-PCIE-9V5 User Manual
Pin Number
H6 H7 J20 J22 M23 K22 W46 W45 U46 U45 R46 R45 N46 N45 L46 L45 J46 J45 G46 G45
E46 E45 K21 J21 T43 T42 P43 P42 M43 M42 K43 K42 H43 H42 F43 F42
Signal Name
Pin Name
Bank Voltage
QSFP_1_TX7_N
MGTYTXN3_232
QSFP_1_TX7_P
MGTYTXP3_232
QSFP_2_INT_1V8_L
IO_T1U_N12_72
QSFP_2_LPMODE_1V8
IO_L12N_T1U_N11_GC_72
QSFP_2_MODPRS_L
IO_L2N_T0L_N3_72
QSFP_2_RST_1V8_L
IO_L12P_T1U_N10_GC_72
QSFP_2_RX0_N
MGTYRXN0_126
QSFP_2_RX0_P
MGTYRXP0_126
QSFP_2_RX1_N
MGTYRXN1_126
QSFP_2_RX1_P
MGTYRXP1_126
QSFP_2_RX2_N
MGTYRXN2_126
QSFP_2_RX2_P
MGTYRXP2_126
QSFP_2_RX3_N
MGTYRXN3_126
QSFP_2_RX3_P
MGTYRXP3_126
QSFP_2_RX4_N
MGTYRXN0_127
QSFP_2_RX4_P
MGTYRXP0_127
QSFP_2_RX5_N
MGTYRXN1_127
QSFP_2_RX5_P
MGTYRXP1_127
QSFP_2_RX6_N
MGTYRXN2_127
QSFP_2_RX6_P
MGTYRXP2_127
QSFP_2_RX7_N
MGTYRXN3_127
QSFP_2_RX7_P
MGTYRXP3_127
QSFP_2_SCL_1V8
IO_L11P_T1U_N8_GC_72
QSFP_2_SDA_1V8
IO_L11N_T1U_N9_GC_72
QSFP_2_TX0_N
MGTYTXN0_126
QSFP_2_TX0_P
MGTYTXP0_126
QSFP_2_TX1_N
MGTYTXN1_126
QSFP_2_TX1_P
MGTYTXP1_126
QSFP_2_TX2_N
MGTYTXN2_126
QSFP_2_TX2_P
MGTYTXP2_126
QSFP_2_TX3_N
MGTYTXN3_126
QSFP_2_TX3_P
MGTYTXP3_126
QSFP_2_TX4_N
MGTYTXN0_127
QSFP_2_TX4_P
MGTYTXP0_127
QSFP_2_TX5_N
MGTYTXN1_127
QSFP_2_TX5_P
MGTYTXP1_127
Table 8 : Complete Pinout Table (continued on next page)
MGT MGT 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18) 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT
Complete Pinout Table ad-ug-1385_v1_5.pdf
Page 29
ADM-PCIE-9V5 User Manual
Pin Number
D43 D42 B43 B42 L20 M20 N23 L21 AG46 AG45 AF44 AF43 AE46 AE45 AD44 AD43 AC46
AC45 AB44 AB43 AA46 AA45 Y44 Y43 J24 M21 AK43 AK42 AJ41 AJ40 AG41 AG40 AE41
AE40 AC41 AC40
Signal Name
Pin Name
Bank Voltage
QSFP_2_TX6_N
MGTYTXN2_127
QSFP_2_TX6_P
MGTYTXP2_127
QSFP_2_TX7_N
MGTYTXN3_127
QSFP_2_TX7_P
MGTYTXP3_127
QSFP_3_INT_1V8_L
IO_L10N_T1U_N7_QBC_AD4N_72
QSFP_3_LPMODE_1V8 IO_L10P_T1U_N6_QBC_AD4P_72
QSFP_3_MODPRS_L
IO_L2P_T0L_N2_72
QSFP_3_RST_1V8_L
IO_L9N_T1L_N5_AD12N_72
QSFP_3_RX0_N
MGTYRXN0_122
QSFP_3_RX0_P
MGTYRXP0_122
QSFP_3_RX1_N
MGTYRXN1_122
QSFP_3_RX1_P
MGTYRXP1_122
QSFP_3_RX2_N
MGTYRXN2_122
QSFP_3_RX2_P
MGTYRXP2_122
QSFP_3_RX3_N
MGTYRXN3_122
QSFP_3_RX3_P
MGTYRXP3_122
QSFP_3_RX4_N
MGTYRXN0_125
QSFP_3_RX4_P
MGTYRXP0_125
QSFP_3_RX5_N
MGTYRXN1_125
QSFP_3_RX5_P
MGTYRXP1_125
QSFP_3_RX6_N
MGTYRXN2_125
QSFP_3_RX6_P
MGTYRXP2_125
QSFP_3_RX7_N
MGTYRXN3_125
QSFP_3_RX7_P
MGTYRXP3_125
QSFP_3_SCL_1V8
IO_L8N_T1L_N3_AD5N_72
QSFP_3_SDA_1V8
IO_L9P_T1L_N4_AD12P_72
QSFP_3_TX0_N
MGTYTXN0_122
QSFP_3_TX0_P
MGTYTXP0_122
QSFP_3_TX1_N
MGTYTXN1_122
QSFP_3_TX1_P
MGTYTXP1_122
QSFP_3_TX2_N
MGTYTXN2_122
QSFP_3_TX2_P
MGTYTXP2_122
QSFP_3_TX3_N
MGTYTXN3_122
QSFP_3_TX3_P
MGTYTXP3_122
QSFP_3_TX4_N
MGTYTXN0_125
QSFP_3_TX4_P
MGTYTXP0_125
Table 8 : Complete Pinout Table (continued on next page)
MGT MGT MGT MGT 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18) 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT
Page 30
Complete Pinout Table ad-ug-1385_v1_5.pdf
ADM-PCIE-9V5 User Manual
Pin Number
AA41 AA40 W41 W40 U41 U40 BC15 BB9 AH39 AH38
N8 N9 AY23 AY24 AL24 T39 T38 AN8 AN9 AW22 AW23 AM24 AM21 AL21 BF14 BE15 BF15
BC11 AV9 AV8 AY8 AY7 AW8 AW7 BA15 BA14
Signal Name
Pin Name
QSFP_3_TX5_N QSFP_3_TX5_P QSFP_3_TX6_N QSFP_3_TX6_P QSFP_3_TX7_N QSFP_3_TX7_P
RF_DIR RF_IO SI5328_0_OUT_0_PIN_N SI5328_0_OUT_0_PIN_P SI5328_0_OUT_1_PIN_N
SI5328_0_OUT_1_PIN_P SI5328_0_REFCLK_IN_N SI5328_0_REFCLK_IN_P
SI5328_0_RST_1V8_L SI5328_1_OUT_0_PIN_N SI5328_1_OUT_0_PIN_P
SI5328_1_OUT_1_PIN_N SI5328_1_OUT_1_PIN_P SI5328_1_REFCLK_IN_N
SI5328_1_REFCLK_IN_P SI5328_1_RST_1V8_L SI5328_1V8_SCL SI5328_1V8_SDA
SPARE_SCL SPARE_SDA SPARE_WP SRVC_MD_L_1V8 USER_LED_G0_1V8 USER_LED_G1_1V8
USER_LED_G2_1V8 USER_LED_G3_1V8 USER_LED_G4_1V8 USER_LED_G5_1V8 USR_SW_0
USR_SW_1
MGTYTXN1_125 MGTYTXP1_125 MGTYTXN2_125 MGTYTXP2_125 MGTYTXN3_125 MGTYTXP3_125 IO_L21P_T3L_N4_AD8P_66 IO_L14P_T2L_N2_GC_66 MGTREFCLK1N_121 MGTREFCLK1P_121 MGTREFCLK1N_232 MGTREFCLK1P_232 IO_L11N_T1U_N9_GC_64 IO_L11P_T1U_N8_GC_64 IO_L24P_T3U_N10_64 MGTREFCLK1N_126 MGTREFCLK1P_126 MGTREFCLK1N_224 MGTREFCLK1P_224 IO_L12N_T1U_N11_GC_64 IO_L12P_T1U_N10_GC_64 IO_L24N_T3U_N11_64 IO_L23N_T3U_N9_64 IO_L23P_T3U_N8_64 IO_L5N_T0U_N9_AD14N_66 IO_L6P_T0U_N10_AD6P_66 IO_L6N_T0U_N11_AD6N_66 IO_L3P_T0L_N4_AD15P_66 IO_L16P_T2U_N6_QBC_AD3P_66 IO_L16N_T2U_N7_QBC_AD3N_66 IO_L17P_T2U_N8_AD10P_66 IO_L17N_T2U_N9_AD10N_66 IO_L18P_T2U_N10_AD2P_66 IO_L18N_T2U_N11_AD2N_66 IO_L22N_T3U_N7_DBC_AD0N_66 IO_L23P_T3U_N8_66
Table 8 : Complete Pinout Table
Complete Pinout Table ad-ug-1385_v1_5.pdf
Bank Voltage
MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18) 1.8 (LVCMOS18) MGT REFCLK MGT REFCLK
MGT REFCLK MGT REFCLK 1.8 (LVDS) 1.8 (LVDS) 1.8 (LVCMOS18) MGT REFCLK MGT
REFCLK MGT REFCLK MGT REFCLK 1.8 (LVDS) 1.8 (LVDS) 1.8 (LVCMOS18) 1.8
(LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8
(LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8
(LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18)
Page 31
ADM-PCIE-9V5 User Manual
Revision History
Date 29 Aug 2019 8 Nov 2019 18 Feb 2020 30 Apr 2020
12 Jun 2020 17 Jul 2023
Revision 1.0 1.1 1.2 1.3
1.4 1.5
Changed By K. Roth
K. Roth
Initial Release
Nature of Change
Updated sections Power Requirements and Switches to detail 12V auto-detect feature for rev2 boards.
K. Roth K. Roth
Added section KN32 Emissions
Image QSFP-DD Location updated to show proper QSFP cage order at previous
revision 1.2, and modified section Si5328 to remove reference to VCU110 and
added notes on RXOUTCLK.
K. Roth
Image OpenCAPI Pinout added to show J10 pinout, and updated Thermal Performance with detailed data for blower and LFM thermal performance.
K. Roth
Separated PCB dimensions in Physical Specifications for consistency with other user guides.
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Telephone: +44 131 558 2600
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email:
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5.0
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Telephone: (303) 954 8768
Fax:
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email:
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References
- Salesforce Data Cloud - Salesforce.com US
- Alpha Data - committed to providing solutions
- Xilinx Power Estimator (XPE)
- support.alpha-data.com - /pub/firmware/utilities/linux/
- support.alpha-data.com - /pub/firmware/utilities/windows/