ALPHA DATA ADM-PCIE-9H7 Data Center board with Xilinx Virtex Ultrascale User Manual Product Information
- May 15, 2024
- ALPHA DATA
Table of Contents
ADM-PCIE-9H7 Data Center board with Xilinx Virtex Ultrascale
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Product Information
Specifications
-
Product Name: ADM-PCIE-9H7
-
Revision: 1.5
-
Date: 28th July 2022
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Manufacturer: Alpha Data Parallel Systems
Ltd. -
Key Features: High-performance reconfigurable
computing card for Data Center applications, featuring a Xilinx
Virtex UltraScale+ Plus FPGA with High Bandwidth Memory (HBM)
Product Usage Instructions
Introduction
The ADM-PCIE-9H7 is designed for high-performance reconfigurable
computing in Data Center applications. It features a Xilinx Virtex
UltraScale+ Plus FPGA with High Bandwidth Memory (HBM).
Key Features
The key features of the ADM-PCIE-9H7 include high-performance
computing capabilities suitable for Data Center applications.
Order Code
The order code for the ADM-PCIE-9H7 is ADM-PCIE-9H7. Refer to
the datasheet for complete ordering options.
Board Information
Physical Specifications
-
PCB Dimensions: 111.15 mm x 254 mm x 1.6
mm -
Fully Assembled Dimensions: 125.2 mm x 267.2
mm x 41.9 mm, Weight: 1300 grams
Chassis Requirements
PCI Express
The ADM-PCIE-9H7 complies with PCI Express CEM revision 3.0 and
supports PCIe Gen 1/2/3 with 1/2/4/8/16 lanes using the Xilinx
Integrated Block for PCI Express.
FAQ
Q: What are the key features of the ADM-PCIE-9H7?
A: The key features include high-performance reconfigurable
computing capabilities, a Xilinx Virtex UltraScale+ Plus FPGA, and
High Bandwidth Memory (HBM) suitable for Data Center
applications.
Q: What are the physical dimensions of the ADM-PCIE-9H7?
A: The PCB dimensions are 111.15 mm x 254 mm x 1.6 mm, and the
fully assembled dimensions are 125.2 mm x 267.2 mm x 41.9 mm with a
weight of 1300 grams.
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ADM-PCIE-9H7 User Manual
Document Revision: 1.5 28th July 2022
ADM-PCIE-9H7 User Manual
© 2022 Copyright Alpha Data Parallel Systems Ltd. All rights reserved.
This publication is protected by Copyright Law, with all rights reserved. No
part of this publication may be reproduced, in any shape or form, without
prior written consent from Alpha
Data Parallel Systems Ltd.
Head Office
Address: Suite L4A, 160 Dundee Street,
Edinburgh, EH11 1DQ, UK
Telephone: +44 131 558 2600
Fax:
+44 131 558 2700
email:
website: http://www.alpha-data.com
US Office
10822 West Toller Drive, Suite 250 Littleton, CO 80127 (303) 954 8768 (866)
820 9956 – toll free [email protected] http://www.alpha-data.com
All trademarks are the property of their respective owners.
ADM-PCIE-9H7 User Manual
Table Of Contents
1 1.1 1.2
2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.3 2.3.1
3 3.1 3.1.1 3.1.2 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.3 3.4
3.5 3.5.1 3.6 3.7 3.7.1 3.7.2 3.8 3.9 3.9.1 3.9.1.1 3.9.2 3.10 3.10.1 3.10.2
3.11 3.12 3.12.1
Introduction …………………………………………………………………………………………………………………….. 1 Key Features
…………………………………………………………………………………………………………………. 1 Order Code
…………………………………………………………………………………………………………………… 1
Board Information ……………………………………………………………………………………………………………. 2 Physical
Specifications …………………………………………………………………………………………………… 2 Chassis Requirements
……………………………………………………………………………………………………. 2 PCI Express
………………………………………………………………………………………………………………. 2 Mechanical Requirements
…………………………………………………………………………………………… 2 Power Requirements
………………………………………………………………………………………………….. 2 Thermal Performance
…………………………………………………………………………………………………….. 4 Active VS Passive Thermal
Management ………………………………………………………………………. 5
Functional Description …………………………………………………………………………………………………….. 6 Overview
………………………………………………………………………………………………………………………. 6 Switches
……………………………………………………………………………………………………………………. 7 LEDs
………………………………………………………………………………………………………………………… 8 Clocking
……………………………………………………………………………………………………………………….. 9 Si5328
…………………………………………………………………………………………………………………….. 10 PCIe Reference Clocks
……………………………………………………………………………………………… 10 Fabric Clock
…………………………………………………………………………………………………………….. 10 Auxiliary Clock
………………………………………………………………………………………………………….. 11 Programming Clock (EMCCLK)
………………………………………………………………………………….. 11 QSFP28
………………………………………………………………………………………………………………….. 11 Ultraport SlimSAS (OpenCAPI)
…………………………………………………………………………………… 11 FireFly
…………………………………………………………………………………………………………………….. 11 PCI Express
………………………………………………………………………………………………………………… 12 QSFP28
……………………………………………………………………………………………………………………… 13 FireFly
………………………………………………………………………………………………………………………… 14 QSFP Expansion
……………………………………………………………………………………………………… 15 OpenCAPI Ultraport SlimSAS
………………………………………………………………………………………… 16 System Monitor
……………………………………………………………………………………………………………. 17 System Monitor Status LEDs
……………………………………………………………………………………… 18 Fan Controllers
………………………………………………………………………………………………………… 18 USB Interface
………………………………………………………………………………………………………………. 19 Configuration
……………………………………………………………………………………………………………….. 19 Configuration From Flash
Memory ……………………………………………………………………………… 19 Building and Programming
Configuration Images ……………………………………………………… 20 Configuration via JTAG
……………………………………………………………………………………………… 20 GPIO Connector
………………………………………………………………………………………………………….. 21 Direct Connect FPGA Signals
…………………………………………………………………………………….. 21 Timing Input
…………………………………………………………………………………………………………….. 21 User EEPROM
…………………………………………………………………………………………………………….. 22 Battery Backed Encryption
…………………………………………………………………………………………….. 22 Top Shroud Removal
………………………………………………………………………………………………… 23
Appendix A Complete Pinout Table …………………………………………………………………………………………………… 25
List of Tables
Table 1 Table 2 Table 3
Mechanical Dimensions (PCB only) ……………………………………………………………………………………… 2 Mechanical Dimensions (Fully Assembled) …………………………………………………………………………… 2 Available Power By Rail ……………………………………………………………………………………………………… 3
ADM-PCIE-9H7 User Manual
Table 4 Table 5 Table 6 Table 7 Table 8 Table 9
Switch Functions ……………………………………………………………………………………………………………….. 7 LED Details
………………………………………………………………………………………………………………………. 8 QSFP28 Part Numbers
…………………………………………………………………………………………………….. 13 Voltage, Current, and Temperature
Monitors ……………………………………………………………………….. 17 Status LED Definitions
……………………………………………………………………………………………………… 18 Complete Pinout Table
……………………………………………………………………………………………………… 25
List of Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18
ADM-PCIE-9H7 Product Photo ……………………………………………………………………………………………. 1 Thermal Performance ………………………………………………………………………………………………………… 4 ADM-PCIE-9H7 Heat Sink with Fans ……………………………………………………………………………………. 5 ADM-PCIE-9H7 Block Diagram …………………………………………………………………………………………… 6 Switches …………………………………………………………………………………………………………………………… 7 Front Panel LEDs ………………………………………………………………………………………………………………. 8 Clock Topology ………………………………………………………………………………………………………………….. 9 Si5328 Block Diagram ……………………………………………………………………………………………………… 10 QSFP Locations ………………………………………………………………………………………………………………. 13 FireFly Locations ……………………………………………………………………………………………………………… 14 FQSFP connections …………………………………………………………………………………………………………. 15 FQSFP with shroud ………………………………………………………………………………………………………….. 15 OpenCAPI Location …………………………………………………………………………………………………………. 16 Flash Address Map ………………………………………………………………………………………………………….. 19 GPIO Connector Schematic ………………………………………………………………………………………………. 21 GPIO Connector Location …………………………………………………………………………………………………. 21 Top Shroud Screws ………………………………………………………………………………………………………….. 22 Top Shroud Screws ………………………………………………………………………………………………………….. 23
ADM-PCIE-9H7 User Manual
1 Introduction
The ADM-PCIE-9H7 is a high-performance reconfigurable computing card intended
for Data Center applications, featuring a Xilinx Virtex UltraScale+ Plus FPGA
with High Bandwidth Memory (HBM).
Figure 1 : ADM-PCIE-9H7 Product Photo
1.1 Key Features
Key Features · PCIe Gen1/2/3 x1/2/4/8/16 capable · Passive and active thermal
management configuration · 3/4 length, full height, 2 slot, x16 edge PCIe form
factor (GPU size) · 8GB HBM on-die memory capable of 460GB/s · Four QSFP28
cages capable of data rates up to 28 Gbps per channel (112 Gbps per cage) ·
Two 8 lane Ultraport SlimSAS connectors compliant with OpenCAPI · Supports
either VU35P or VU37P Virtex UltraScale+ FPGAs · Eight (VU37P) or four (VU35P)
FireFly sites capable of data rates up to 28 Gbps per channel (112 Gbps
per site) · Front panel and rear edge JTAG access via USB port · FPGA
configurable over USB/JTAG and SPI configuration flash · Voltage, current, and
temperature monitoring · 16 GPIO signals and 1 isolated timing input
1.2 Order Code
ADM-PCIE-9H7
See the datasheet for complete ordering options.
Introduction ad-ug-1341_v1_5.pdf
Page 1
ADM-PCIE-9H7 User Manual
2 Board Information
2.1 Physical Specifications
The ADM-PCIE-9H7 complies with PCI Express CEM revision 3.0.
Description PCB Dy PCB Dx PCB Dz
Measure 111.15 mm
254 mm 1.6 mm
Table 1 : Mechanical Dimensions (PCB only)
Description Total Dy Total Dx Total Dz Weight
Measure 125.2 mm 267.2 mm 41.9 mm 1300 grams
Table 2 : Mechanical Dimensions (Fully Assembled)
2.2 Chassis Requirements
2.2.1 PCI Express
The ADM-PCIE-9H7 is capable of PCIe Gen 1/2/3 with 1/2/4/8/16 lanes, using the
Xilinx Integrated Block for PCI Express.
2.2.2 Mechanical Requirements
A 16-lane physical PCIe slot is required for mechanical compatibility.
2.2.3 Power Requirements
The ADM-PCIE-9H7 has a PCIe Auxiliary power connector on the back edge. This
must be used in combination with the PCIe edge connector order for the board
to power up. The total power envelope for the card is 225W.
The power sense signals as defined in the PCIe CEM are available to the FPGA
for integration into user logic. It is highly recommended that if the
application requires more than 150W available between the 6-pin Auxiliary plug
and PCIe edge, the sense pins are interrogated to ensure the 8-pin 150W
connector is present. For constraint information, see net names
PWR_SENSE0_PIN, and PWR_SENSE1_PIN in Complete Pinout Table.
The PCIe Specification permits a standard full-height, double slot PCIe card
to dissipate up to 225 W of power, drawn from the PCIe slot and auxiliary
connector combined. Power consumption estimation requires the use of the
Xilinx XPE spreadsheet and a power estimator tool available from Alpha Data.
Please contact [email protected] to obtain this tool.
The power available to the rails calculated using XPE are as follows:
Page 2
Board Information ad-ug-1341_v1_5.pdf
ADM-PCIE-9H7 User Manual
Voltage 0.72-0.90 0.85-0.90
0.9 1.2 1.2 1.8 1.8 2.5 3.3
Source Name VCC_INT
VCCINT_IO + VCC_BRAM MGTAVCC MGTAVTT
VCC_HBM * VCC_IO_HBM VCCAUX + VCCAUX_IO + VCCO_1.8V
MGTVCCAUX VCCAUX_HBM 3.3V for Optics Table 3 : Available Power By Rail
Current Capability 102A 25A 14A 25A 18A 7A 1A 2A 25A
Board Information ad-ug-1341_v1_5.pdf
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ADM-PCIE-9H7 User Manual
2.3 Thermal Performance
If the FPGA core temperature exceeds 105 degrees Celsius, the FPGA design will
be cleared to prevent the card from over-heating. The ADM-PCIE-9H7 comes with
a heat sink to reduce the heat of the FPGA which is typically the hottest
point on the card. The FPGA die temperature must remain under 100 degrees
Celsius. To calculate the FPGA die temperature, take your application power
and multiply by Theta JA from the table below, and add to your system internal
ambient temperature. If you are using the fan provided with the board, you
will find theta JA is approximately 0.4 degC/W for the board in still air. The
power dissipation can be estimated by using the Alpha Data power estimator in
conjunction with the Xilinx Power Estimator (XPE) downloadable at
http://www.xilinx.com/products/technology/power/xpe.html . Download the
UltraScale tool and set the Device to Virtex UltraScale+, VU37P or VU35P,
FSVH2892, -2 or -3, Extended. Set the ambient temperature to your system
ambient and select User Override for the Effective theta JA and enter the
figure associated with your system LFM in the blank field. Proceed to enter
all applicable design elements and utilization in the following spreadsheet
tabs. Next aquire the 9H7 power estimator from Alpha Data by contacting
[email protected]. You will then plug in the FPGA power figures along
with Optical module figures to get a board level estimate.
Figure 2 : Thermal Performance
Page 4
Board Information ad-ug-1341_v1_5.pdf
ADM-PCIE-9H7 User Manual
2.3.1 Active VS Passive Thermal Management
Because it is likely a generic PC chassis to not provide sufficient airflow to
cool the card, the ADM-PCIE-9H7 default built utilizes the active cooling
configuration with fans installed to force air across the heat sink. If the
ADM-PCIE-9H7 will be installed in a server with good controlled airflow, the
order option /NF can be used to receive cards in the passive cooling
configuration with the fans removed. The fans have a much shorter mean time
between failure (MTBF) than the rest of the assembly, so passive cards have
much longer life expectance before requiring maintenance. The ADM-PCIE-9H7
also includes fan speed controllers, allowing variable fan speed based on die
temperature, and detection of failed fans (see section Fan Controllers).
Figure 3 : ADM-PCIE-9H7 Heat Sink with Fans
Board Information ad-ug-1341_v1_5.pdf
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ADM-PCIE-9H7 User Manual
3 Functional Description
3.1 Overview
The ADM-PCIE-9H7 is a versatile reconfigurable computing platform with a
Virtex UltraScale+ VU37P or VU35P FPGA, a Gen3x16 PCIe interface, 8GB of HBM
memory, four QSFP28 cages plus 8 FireFly sites (4 FireFly with a VU35P) each
capable of 4x 28G or 1x 112G Serial IO of any Xilinx supported standard
(Ethernet, SRIO, Infiniband, etc.), two OpenCAPI compatible Ultraport SlimSAS
connector also capable of 28G/channel, an isolated input for a timing
synchronization pulse, a 20 pin header for general purpose use (clocking,
control pins, debug, etc.), and a robust system monitor.
(Q4xS28F(Q4GPxSb22p(8QF48sGxP)S2b28Fp(Q4G8sPx)Sb22p8F8sGP) b2p8s)
GPIO+PWR
x16
PPS ISOLATION
(4Fx2ir8(e4GFFxb2ilrp(y84esFGx)F2ibrl8p(ye4GsFFx)b2ilrpy8esG)Fblpys) x16
USB
Note: 4x FireFly sites not connected in VU35P (non-standard)
(back)
USB to JTAG
Mux+Hub
System Monitor
MGT GPIO
MGT
MGT
XCVU35P-2FSVH2892E or
XCVU37P-2FSVH2892E MGT
x16
(4Fx2ir8(e4GFFxb2ilrp(y84esFGx)F2ibrl8p(ye4GsFFx)b2ilrpy8esG)Fblpys)
x8
OpenCAPI
MGT
x8
OpenCAPI
0
MGT MGT MGT MGT
USB
(front)
QSPI (Config)
I2C (0,4) (5,7) (8,11) (12,15)
x16 PCIe Gen3 Edge
12V connector
(PCIe external)
Figure 4 : ADM-PCIE-9H7 Block Diagram
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Functional Description ad-ug-1341_v1_5.pdf
ADM-PCIE-9H7 User Manual
3.1.1 Switches
The ADM-PCIE-9H7 has an octal DIP switch SW1, located on the rear side of the
board. The function of each switch in SW1 is detailed below:
Figure 5 : Switches
Switch
Factory Default
Function
OFF State
SW1-1 OFF
User Switch 0
Pin BF52 = ‘1’
SW1-2 OFF
User Switch 1
Pin BF47 = ‘1’
SW1-3 SW1-4 SW1-5
SW1-6
SW1-7
OFF OFF OFF
ON
ON
Reserved
Power Off
Service Mode
HOST_I2 C_EN
CAPI_VP D_EN
Reserved Board will power up Regular Operation
Sysmon over PCIe I2C
OpenCAPI VPD available
SW1-8
ON
CAPI_VP D_WP
CAPI VPD is write protected
Table 4 : Switch Functions Use IO Standard “LVCMOS18” when constraining the user switch pins.
ON State Pin BF52 = ‘0’ Pin BF47 = ‘0’
Reserved Immediately power down Firmware update service mode
Sysmon isolated OpenCAPI VPD isolated
CAPI VPD is writable
Functional Description ad-ug-1341_v1_5.pdf
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ADM-PCIE-9H7 User Manual
3.1.2 LEDs
There are 24 LEDs on the ADM-PCIE-9H7, 21 of which are general purpose and
whose meaning can be defined by the user. The other 3 have fixed functions
described below:
D9 D11 D13 D14
CG1 CG0 CR0 CR1
D15 D16 D17 D18
BG0 BG1 BR0 BR1
D4 D6 D7
D8
DG0 DG1 DR0 DR1
QSFP LEDs
D21 D22 D23 D24
AG0 AG1 AR0 AR1
Status LEDs
D1
D2
D3
STAT_0 STAT_1 DONE
User LEDs
D25
D26
D27
LED_G2 LED_G1 LED_G0
D29
D30
LED_G3 LED_R0
Figure 6 : Front Panel LEDs
Comp. Ref. D1 D2 D3
D4-D24
Function
Status 0 Status 1 DONE QSFPLED*
ON State
OFF State
See Status LED Definitions
See Status LED Definitions
FPGA is configured
FPGA is not configured
User defined ‘0’
User defined ‘1’
D25-D30 USERLED*
User defined ‘0’
User defined ‘1’
Table 5 : LED Details See Section Complete Pinout Table for full list of user controlled LED nets and pins
Rev 1 PCBs LED nets QSFP_LED_CG0 and QSFP_LED_CR0 are tied together
Rev 1 PCBs LED nets QSFP_LED_CG1 and QSFP_LED_CR1 are tied together
Page 8
Functional Description ad-ug-1341_v1_5.pdf
ADM-PCIE-9H7 User Manual
3.2 Clocking
The ADM-PCIE-9H7 provides flexible reference clock solutions for the many
multi-gigabit transceiver quads and FPGA fabric. Any clock out of the Si5338
Clock Synthesizer is re-configurable from either the front panel USB USB
Interface or the Alpha Data sysmon FPGA serial port. This allows the user to
configure almost any arbitrary clock frequencies during application run time.
Maximum clock frequency is 312.5MHz. After a clock is programmed to a certain
frequency, that frequency will become the default on power-up.
There are also three available Si5328 jitter attenuators. These can provide
clean clocks to all FireFly and QSFP28 quad locations at many clock
frequencies. These devices do only use volatile memory, so the FPGA design
will need to re-configure the circuits after any power cycle event.
All clock names in the section below can be found in Complete Pinout Table.
Card Edge PCIe Ref Clock (100MHz) On-board PCIe Ref Clock (100MHz)
PCIe Ref Clock (MGTREFCLK0_225) PCIe Ref Clock (MGTREFCLK0_226)
25MHz 30ppm Source
Si5338 0 Clock 1 Synth 2
3
SI5330B Fanout
SI5330B Fanout
FireFly CLK 161.1328125MHz Default (MGTREFCLK0_125) FireFly CLK 161.1328125MHz
Default (MGTREFCLK0_126) FireFly CLK 161.1328125MHz Default (MGTREFCLK0_234)
FireFly CLK 161.1328125MHz Default (MGTREFCLK0_135) QSFP28 161.1328125MHz
Factory Default (MGTREFCLK0_228) QSFP28 161.1328125MHz Factory Default
(MGTREFCLK0_230) QSFP28 161.1328125MHz Factory Default (MGTREFCLK0_129) QSFP28
161.1328125MHz Factory Default (MGTREFCLK0_131)
AUX_CLK 300Mhz Default (IO Bank 64)
FABRIC_CLK 300MHz Default (IO Bank 64)
CAPI Cable Clock (156.25MHz when used) CAPI Cable Clock (156.25MHz when used)
CAPI Cable Clock (MGTREFCLK0_128) CAPI Cable Clock (MGTREFCLK0_130)
Figure 7 : Clock Topology
Functional Description ad-ug-1341_v1_5.pdf
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ADM-PCIE-9H7 User Manual
3.2.1 Si5328
If jitter attenuation is required please see the reference documentation for
the Si5328. https://www.silabs.com/
Support%20Documents/TechnicalDocs/Si5328.pdf
See diagram below for net names and configuration settings.
Crystal
114.285MHz
Crystal
114.285MHz
Crystal
114.285MHz
XA/XB CLKIN1
I2C
Si5328_2 CLKOUT1
(2.5V VCC)
CLKOUT2
Address: 1101010 CS_CA = CMODE = GND
Other control pins = N/C
XA/XB CLKIN1
I2C
Si5328 _1 CLKOUT1
(2.5V VCC)
CLKOUT2
Address: 1101001 CS_CA = CMODE = GND
Other control pins = N/C
XA/XB CLKIN1
I2C
Si5328_0 CLKOUT1
(2.5V VCC)
CLKOUT2
Address: 1101000 CS_CA = CMODE = GND
Other control pins = N/C
GPIO (LVCMOS18) Bank 66 SI5328_1V8_SDA SI5328_1V8_SCL
GPIO (LVDS) Bank 64 SI5328_0_REFCLK_IN_P SI5328_0_REFCLK_IN_N
GPIO (LVDS) Bank 66 SI5328_1_REFCLK_IN_P SI5328_1_REFCLK_IN_N
GPIO (LVDS) Bank 66 SI5328_2_REFCLK_IN_P SI5328_2_REFCLK_IN_N
FPGA
Quad 127 REFCLK0 (LVDS) SI5328_0_OUT1_P SI5328_0_OUT1_N
Quad 124 REFCLK0 (LVDS) SI5328_0_OUT0_P SI5328_0_OUT0_N
Quad 134 REFCLK0 (LVDS) SI5328_1_OUT1_P SI5328_1_OUT1_N
Quad 235 REFCLK0 (LVDS) SI5328_1_OUT0_P SI5328_1_OUT0_N
Quad 231 REFCLK0 (LVDS) SI5328_2_OUT1_P SI5328_2_OUT1_N
Quad 229 REFCLK0 (LVDS) SI5328_2_OUT0_P SI5328_2_OUT0_N
Figure 8 : Si5328 Block Diagram
3.2.2 PCIe Reference Clocks
The 16 MGT lanes connected to the PCIe card edge use MGT tiles 224 through 227
and use the system 100 MHz clock (net name PCIE_REFCLK). Alternatively, a
clean, onboard 100MHz clock is available as well (net name PCIE_LCL_REFCLK).
3.2.3 Fabric Clock
The design offers a fabric clock (net name FABRIC_SRC_CLK) which defaults to
300 MHz. This clock is intended to be used for IDELAY elements in FPGA
designs. The fabric clock is connected to a Global Clock (GC) pin.
DIFF_TERM_ADV = TERM_100 is required for LVDS termination
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Functional Description ad-ug-1341_v1_5.pdf
ADM-PCIE-9H7 User Manual
3.2.4 Auxiliary Clock
The design offers a auxiliary clock (net name AUX_CLK) which defaults to 300
MHz. This clock can be used for any purpose and is connected to a Global Clock
(GC) pin. DIFF_TERM_ADV = TERM_100 is required for LVDS termination
3.2.5 Programming Clock (EMCCLK)
A 100MHz clock (net name EMCCLK_B) is fed into the EMCCLK pin to drive the SPI
flash device during configuration of the FPGA. Note that this is not a global
clock capable IO pin.
3.2.6 QSFP28
The QSFP28 cages are located in MGT tiles 228 through 231 and use a
161.1328125MHz default reference clock. Note that this clock frequency can be
changed to any arbitrary clock frequency up to 312MHz by re-programing the
Si5338 reprogrammable clock oscillator via system monitor. This can be done
using the Alpha Data API or over USB with the appropriate Alpha Data Software
tools. See net names QSFP_CLK_0 and QSFP_CLK_1 for pin locations. The QSFP28
cages are also located such that they can be clocked from a Si5328 jitter
attenuator clock multiplier. See net names SI5328_2_OUT0 and SI5328_2_OUT1 for
pin locations.
3.2.7 Ultraport SlimSAS (OpenCAPI)
The Ultraport SlimSAS connectors are located in MGT tile 128 through 131. For
OpenCAPI an external 156.25MHz clock is provided over the cable. See net names
CAPI_0_CLK1 and CAPI_1_CLK1 for pin locations. For other applications, this
clock is shared with the QSFP clock from the Si5328 clock synthesizer
(defaults to 161.1328125MHz). See net names QSFP_CLK_2 and QSFP_CLK_3 for pin
locations.
3.2.8 FireFly
Eight FireFly connectors use MGT quads 124-127, 134-135, and 234-235 (134-135
and 234-235 are not present in VU35P). All eight quads can access the shared
FireFly reference clock, which is independent from all other onboard clocks,
and defaults to 161.1328125MHz. See net names FIREFLY_CLK_0, FIREFLY_CLK_1,
FIREFLY_CLK_2, FIREFLY_CLK_3 for pin locations. Alternatively, two of the
Si5328 clock synthesizers are connected to the FireFly quads. See net names
SI5328_0_OUT0, SI5328_0_OUT1, SI5328_1_OUT0, and SI5328_1_OUT1 for pin
locations.
Functional Description ad-ug-1341_v1_5.pdf
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ADM-PCIE-9H7 User Manual
3.3 PCI Express
The ADM-PCIE-9H7 is capable of PCIe Gen 1/2/3 with 1/2/4/8/16 lanes. The FPGA
drives these lanes directly using the Integrated PCI Express block from
Xilinx. Negotiation of PCIe link speed and number of lanes used is generally
automatic and does not require user intervention. PCI Express reset (PERST#)
connected to the FPGA at one location. See Complete Pinout Table signals
PERST0_1V8_L. The other pin assignments for the high speed lanes are provided
in the pinout attached to the Complete Pinout Table The PCI Express
specification requires that all add-in cards be ready for enumeration within
120ms after power is valid (100ms after power is valid + 20ms after PERST is
released). The ADM-PCIE-9H7 does meet this requirement when configured from a
tandem bitstream with the proper SPI constraints detailed in the section:
Configuration From Flash Memory. For more details on tandem configuration, see
Xilinx xapp 1179.
Note: Different motherboards/backplanes will benefit from different RX
equalization schemes within the PCIe IP core provided by Xilinx. Alpha Data
recommends using the following setting if a user experiences link errors or
training issues with their system: within the IP core generator, change the
mode to “Advanced” and open the “GT Settings” tab, change the “form factor
driven insertion loss adjustment” from “Add-in Card” to “Chip-to-Chip” (See
Xilinx PG239 for more details).
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ADM-PCIE-9H7 User Manual
3.4 QSFP28
4 QSFP28 cages are available at the front panel. All cages are capable of
housing either active optical or passive copper QSFP28 or QSFP compatible
components. The communication interface can run at up to 28Gbps per channel.
There are 16 channels between the 4 QSFP28 cages (total maximum bandwidth of
448Gbps). These cages are ideally suited for 16x 10G/25G, 4x 100G Ethernet, or
any other protocol supported by the Xilinx GTY Transceivers. Please see Xilinx
User Guide UG578 for more details on the capabilities of the transceivers. All
QSFP28 cages have control signals connected to the FPGA. Their connectivity is
detailed in the Complete Pinout Table at the end of this document. The
notation used to differentiate between cages in the pin assignments is
QSFPA, QSFPB, QSFP_C, and QSFP_D with locations clarified in the
diagram below. To communicate with the QSFP module register space, use the
QSFP__SDA1V8 and QSFP_SCL_1V8 as detailed in Complete Pinout Table.
Note: The LP_MODE (Low Power Mode) to each QSFP28 cage is tied to ground.
Figure 9 : QSFP Locations
It is possible for Alpha Data to pre-fit the ADM-PCIE-9H7 with QSFP28 optical transceivers. The table below shows the part number for the transceivers fitted when ordered with this board.
Order Code Q10 Q14 Q25
Description 40G (4×10) QSFP Optical Transceiver 56G (4×14) QSFP Optical Transceiver 100G (4×25) QSFP28 Optical Transceiver
Part Number FTL410QE2C FTL414QB2C FTLC9551REPM
Manufacturer Finisar Finisar Finisar
Table 6 : QSFP28 Part Numbers
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3.5 FireFly
8 FireFly sites are available on the circuit board. All sites are capable of
hosting either active optical or passive copper FireFly connectors. The
communication interface can run at up to 28Gbps per channel in either medium.
There are 32 channels between the 8 FireFly sites (total maximum bandwidth of
896Gbps). These cages are ideally suited for 32x 10G/25G, 8x 100G Ethernet, or
any other protocol supported by the Xilinx GTY Transceivers. Please see Xilinx
User Guide UG578 for more details on the capabilities of the transceivers. All
FireFly sites have control signals connected to the FPGA. Their connectivity
is detailed in the Complete Pinout Table at the end of this document. The
notation used in the pin assignments is FIREFLY with locations clarified in
the diagram below. To communicate with the optical module register space, use
the FIREFLY_SDA_1V8 and FIREFLY*_SCL_1V8 as detailed in Complete Pinout
Table. To install new FireFly modules, the top shroud will need to be
temporarily or permanently removed. See Top Shroud Removal for details.
Note: If the ADM-PCIE-9H7 is fitted with a VU35P FPGA (non-standard) then
FireFly interfaced 4-7 are not connected.
Figure 10 : FireFly Locations
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3.5.1 QSFP Expansion
Alpha Data part number AD-PCIE-FQSFP is available to expand the QSFP slot
availability on the ADM-PCIE-9H7 from 4 to up to 12. These cards utilize the
samtec FQSFP product https://www.samtec.com/ products/fqsfp Each QSFP slot can
house a passive or optical QSFP cable, and are controllable over I2C using the
GPIO expansion capabilities of the ADM-PCIE-9H7. These slots are suitable for
100Gbps Ethernet or any other similar high speed protocol.
Figure 11 : FQSFP connections
Figure 12 : FQSFP with shroud
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ADM-PCIE-9H7 User Manual
3.6 OpenCAPI Ultraport SlimSAS
An Ultraport SlimSAS receptacles along the back of the board allow for
OpenCAPI compliant interfaces running at 200G (8 chanels at 25G). Please
contact [email protected] or your IBM representative for more details on
OpenCAPI and its benefits. The SlimSAS connector can also be used to connect
an additional 4x QSFP breakout board. When combined with the FireFly breakout
boards, this results in 16 ports capable of 100Gbps each (1.6Tbps total).
Alternatively, cabling can be used to connect multiple 9H7 cards within a
chassis.
Figure 13 : OpenCAPI Location
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ADM-PCIE-9H7 User Manual
3.7 System Monitor
The ADM-PCIE-9H7 has the ability to monitor temperature, voltage, and current
of the system to check on the operation of the board. The monitoring is
implemented using an Atmel AVR microcontroller.
If the core FPGA temperature exceeds 105 degrees Celsius, the FPGA will be
cleared to prevent damage to the card.
Control algorithms within the microcontroller automatically check line
voltages and on board temperatures and shares makes the information available
to the FPGA over a dedicated serial interface built into the Alpha Data
reference design package (sold separately). The information can also be
accessed directly from the microcontroller over the USB interface on the front
panel or via the IPMI interface available at the PCIe card edge.
Monitors ETC EC 12.0V 12.0V 12.0V 3.3V 3.3V_I 3.3V 2.5V 1.8V 1.8V 1.2V 1.2V 0.9V 0.85-0.90V 0.72-0.90V uC_Temp Board0_Temp Board1_Temp FPGA_Temp
Index
Purpose/Description
ETC
Elapsed time counter (seconds)
EC
Event counter (power cycles)
ADC00 ADC01 ADC02 ADC03 ADC04
Board Input Supply (Edge Connector) Board Input Supply (Auxiliary 6-pin) Board Input Supply (Auxiliary 8-pin) Board Input Supply (Edge Connector) 3.3V input current in amps
ADC05 Board Input Auxiliary Power Supply
ADC06 Clock and DRAM Voltage Supply
ADC07 ADC08 ADC09 ADC10 ADC11
FPGA IO Voltage (VCCO) Transceiver Power (AVCC_AUX) HBM Power Transceiver Power (AVTT) Transceiver Power (AVCC)
ADC12 BRAM + INT_IO (VccINT_IO)
ADC13 FPGA Core Supply (VccINT)
TMP00 TMP01 TMP02 TMP03
FPGA on-die temperature Board temperature near front panel Board temperature near back top corner FPGA on-die temperature
Table 7 : Voltage, Current, and Temperature Monitors
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ADM-PCIE-9H7 User Manual
3.7.1 System Monitor Status LEDs
LEDs D2 (Red) and D1 (Green) indicate the card health status.
LEDs Green Green + Red Flashing Green + Flashing Red (together) Flashing Green
- Flashing Red (alternating) Flashing Green + Red
Red
Flashing Red
Status Running and no alarms Standby (Powered off)
Attention – critical alarm active
Service Mode
Attention – alarm active Missing application firmware or invalid firmware FPGA
configuration cleared to protect board
Table 8 : Status LED Definitions
3.7.2 Fan Controllers
The onboard USB bus controlled by the system monitor has access to a MAX6620
fan controller. This device can be controlled through the multiple onboard
system monitor communication interfaces, including USB, PCIe Edge SMBUS, and
FPGA sysmon seral communication port. The fan controller is on I2C bus 1 at
address 0x2a. For additional questions. Contact [email protected] with
additional questions on utilizing these controllers.
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3.8 USB Interface
The FPGA can be configured directly from the USB connection on either the
front panel or the rear card edge. The ADM-PCIE-9H7 utilizes the Digilent USB-
JTAG converter box which is supported by the Xilinx software tool suite.
Simply connect a micro-USB AB type cable between the ADM-PCIE-9H7 USB port and
a host computer with Vivado installed. Vivado Hardware Manager will
automatically recognize the FPGA and allow you to configure the FPGA and the
SBPI configuration PROM.
The same USB connector is used to directly access the system monitor system.
All voltages, currents, temperatures, and non-volatile clock configuration
settings can be accessed using Alpha Data’s avr2util software at this
interface.
Avr2util for Windows and the associated USB driver is downloadable here:
https://support.alpha-data.com/pub/firmware/utilities/windows/
Avr2util for Linux is downloadable here:https://support.alpha-
data.com/pub/firmware/utilities/linux/
Use “avr2util.exe /?” to see all options.
For example “avr2util.exe /usbcom com4 display-sensors” will display all
sensor values.
For example “avr2util.exe /usbcom com4 setclknv 0 156250000” will set the
FireFly clock to 156.25MHz. setclk index 0 = FireFly_CLK, setclk index 1 =
QSFP_CLK, index 2 = AUX_CLK, index 3 = Fabric_CLK.
Change ‘com4’ to match the com port number assigned under windows device
manager.
3.9 Configuration
There are two main ways of configuring the FPGA on the ADM-PCIE-9H7: · From
Flash memory, at power-on, as described in Section 3.9.1
· Using USB cable connected at either USB port Section 3.9.2
3.9.1 Configuration From Flash Memory
The FPGA can be automatically configured at power-on from two 1 Gbit QSPI
flash memory device configured as an x8 SPI device (Micron part numbers
MT25QU01GBBB8E12-0SIT). These flash devices are typically divided into two
regions of 128 MiByte each, where each region is sufficiently large to hold an
uncompressed bitstream for a VU37P FPGA.
The ADM-PCIE-9H7 is shipped with a simple PCIe endpoint bitstream containing a
basic Alpha Data ADXDMA bitstream. Alpha Data can load in other custom
bitstreams during production test, please contact [email protected] for
more details.
It is possible to use Multiboot with a fallback image on this hardware. The
master SPI configuration interface and the Fallback MultiBoot are discussed in
detail in Xilinx UG570.
The flash address map is as detailed below:
Data Region
Region 0 Default (128 MiB)
Region 1 Multi-boot (128 MiB)
Start Address (Bytes) 0x000_0000
0x800_0000
Figure 14 : Flash Address Map
At power-on, the FPGA attempts to configure itself automatically in serial
master mode based on the contents of the header in the programing file.
Multibook and ICAP can be used to selected between the two configuration
regions to be loaded into the FPGA. See Xilinx UG570 MultiBoot for details.
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The image loaded can also support tandem PROM or tandem PCIE with field update
configuration methods. These options reduce power-on load times to help meet
the PCIe reset timing requirements. Tandem with field also enables a host
system to reconfigure the user FPGA logic without losing the PCIe link, a
useful feature when system resets and power cycles are not an option.
The Alpha Data System Monitor is also capable of reconfiguring the flash
memory and reprograming the FPGA. This provides a useful failsafe mechanism to
re-program the FPGA even if it drops off the PCIe bus. The system monitor can
be accessed over USB at the front panel and rear edge, or over the SMBUS
connections on the PCIe edge.
3.9.1.1 Building and Programming Configuration Images
Generate a bitfile with these constraints (see xapp1233): · set_property
BITSTREAM.GENERAL.COMPRESS TRUE [ current_design ] · set_property
BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-2} [current_design] · set_property
BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] · set_property
BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] · set_property
BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] · set_property
BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design] · set_property CFGBVS
GND [ current_design ] · set_property CONFIG_VOLTAGE 1.8 [ current_design ] ·
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
Generate an MCS file with these properties (write_cfgmem): · -format MCS ·
-size 64 · -interface SPIx8 · -loadbit “up 0x0000000
<directory/to/file/filename.bit>” (0th location) · -loadbit “up 0x8000000
<directory/to/file/filename.bit>” (1st location, optional) Program with vivado
hardware manager with these settings (see xapp1233): · SPI part: mt25qu01-spi-
x1_x2_x4_x8 · State of non-config mem I/O pins: Pull-none · Target the four
files generated from the write_cfgmem tcl command.
3.9.2 Configuration via JTAG
A micro-USB AB Cable may be attached to the front panel or rear edge USB port.
This permits the FPGA to be reconfigured using the Xilinx Vivado Hardware
Manager via the integrated Digilent JTAG converter box. The device will be
automatically recognized in Vivado Hardware Manager.
For more detailed instructions, please see “Using a Vivado Hardware Manager to
Program an FPGA Device” section of Xilinx UG908:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ ug908
-vivado-programming-debugging.pdf
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3.10 GPIO Connector
The GPIO option consists of a versatile shrouded connector from Molex with
part number 87832-2020 that give users with custom IO requirements four direct
connect to FPGA signals. Recommended mating plug: Molex 87568-2093
Figure 15 : GPIO Connector Schematic
Figure 16 : GPIO Connector Location
3.10.1 Direct Connect FPGA Signals
16 nets are broken out to the GPIO header, 6 as three differential pairs.
These signal are suitable for any 1.8V supported signaling standards supported
by the Xilinx UltraScale architecture. See Xilinx UG571 for IO options. LVDS
and 1.8 CMOS are popular options. The direct connect GPIO signals are limited
to 1.8V by a quickswitch (74CBTLVD3245PW) in order to protect the FPGA from
overvoltage on IO pins. This quickswitch allows the signals to travel in
either direction with only 4 ohms of series impedance and less than 1ns of
propagation delay. The nets are directly connected to the FPGA after the
quickswitch. Direct connect signal names are labeled GP0_1V8_P/N and
GP1_1V8_P/N, etc. to show polarity and grouping. The signal pin allocations
can be found in Complete Pinout Table
3.10.2 Timing Input
J22 (SMB jack) can be used as an isolated timing input signal (up to 10MHz).
Applications can either directly connect to the GPIO connector, or Alpha Data
can provide a cabled solution with an SMA or similar connector on the front
panel. Contact [email protected] for front panel connector options. For pin
locations, see signal name PPS_BUF_1V8 in Complete Pinout Table. The signal is
isolated through a optical isolator part number ACPL-M61L with a 739 ohm of
series resistance.
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ADM-PCIE-9H7 User Manual
3.11 User EEPROM
A 2Kb I2C user EEPROM is provided for storing MAC addresses or other user
information. The EEPROM is part number CAT34C02HU4IGT4A The address pins A2,
A1, and A0 are all strapped to a logical ‘0’. Write protect (WP), Serial Clock
(SCL), and Serial Data (SDA) pin assignments can be found in Complete Pinout
Table with the names SPARE_WP, SPARE_SCL, and SPARE_SDA respectively. WP, SDA,
and SCL signals all have external pull-up resistors on the card.
3.12 Battery Backed Encryption
Two coin cell batter holders are available to provide voltage to the VBATT pin
of the FPGA. When at least one battery is populated, the FPGA can hold an AES
encryption key to guarantee the security of user IP. See Xilinx UG570, chapter
8 for more details. Two battery holders are present to allow hot swapping and
battery replacement without losing the key information within the FPGA. Use a
battery cell of less than 2.0V (NOT lithium chemistry) with 6.8mm diameter and
between 2.1 and 2.6mm in height (i.e. SR621 or SR626 type). The battery slots
are not filled by default. Please contact [email protected] to have these
fitted prior to shipping. The batteries can be accessed by removing the top
shroud, see Top Shroud Removal for details.
Figure 17 : Top Shroud Screws
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ADM-PCIE-9H7 User Manual
3.12.1 Top Shroud Removal
The board can be accessed by removing the top shroud using a 1/16″ hex driver.
Remove the 7 button head screws shown in the image below. Do not remove the
other screws. The shroud will then lift straight up with no resistance for
passive cooling configurations. Active cooling configurations will have fan
connections that will resist removal after about 30mm. These four plugs can be
safely removed to allow for complete board access. When re-installing, plug
the fans back in with the shroud assembly hovering about 30mm above the top of
the circuit board before installing the screws.
Figure 18 : Top Shroud Screws
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Appendix A: Complete Pinout Table
Pin Number
BK9
BJ9
BN50 BP48 BH50 BP49 BH49 BN51 AJ41 AJ40 BM29 BM28 BN31 AL50 AL49 AK52 AK51
AE50 AE49 AJ54 AJ53 AH52 AH51 AG54 AG53 AF52 AF51 AE54 AE53 AK47 AK46 AJ49
Signal Name
Pin Name
Bank Voltage
AUX_CLK_PIN_N
IO_L12N_T1U_N11_GC_68
1.8 (LVDS with DIFF_TERM_ADV)
AUX_CLK_PIN_P
IO_L12P_T1U_N10_GC_68
1.8 (LVDS with DIFF_TERM_ADV)
AVR_B2U_1V8
IO_L2P_T0L_N2_66
1.8 (LVCMOS18)
AVR_HS_B2U_1V8
IO_L1P_T0L_N0_DBC_66
1.8 (LVCMOS18)
AVR_HS_CLK_1V8
IO_L12N_T1U_N11_GC_66
1.8 (LVCMOS18)
AVR_HS_U2B_1V8
IO_L1N_T0L_N1_DBC_66
1.8 (LVCMOS18)
AVR_MON_CLK_1V8
IO_L12P_T1U_N10_GC_66
1.8 (LVCMOS18)
AVR_U2B_1V8
IO_L2N_T0L_N3_66
1.8 (LVCMOS18)
CAPI_0_CLK1_PIN_N
MGTREFCLK0N_128
MGT REFCLK
CAPI_0_CLK1_PIN_P
MGTREFCLK0P_128
MGT REFCLK
CAPI_0_I2C_SCL_1V8
IO_L1N_T0L_N1_DBC_64
1.8 (LVCMOS18)
CAPI_0_I2C_SDA_1V8
IO_L1P_T0L_N0_DBC_64
1.8 (LVCMOS18)
CAPI_0_INT/RESET_1V8
IO_L3P_T0L_N4_AD15P_64
1.8 (LVCMOS18)
CAPI_0_RX0_N
MGTYRXN0_128
MGT
CAPI_0_RX0_P
MGTYRXP0_128
MGT
CAPI_0_RX1_N
MGTYRXN1_128
MGT
CAPI_0_RX1_P
MGTYRXP1_128
MGT
CAPI_0_RX10_N
MGTYRXN3_129
MGT
CAPI_0_RX10_P
MGTYRXP3_129
MGT
CAPI_0_RX2_N
MGTYRXN2_128
MGT
CAPI_0_RX2_P
MGTYRXP2_128
MGT
CAPI_0_RX3_N
MGTYRXN3_128
MGT
CAPI_0_RX3_P
MGTYRXP3_128
MGT
CAPI_0_RX7_N
MGTYRXN0_129
MGT
CAPI_0_RX7_P
MGTYRXP0_129
MGT
CAPI_0_RX8_N
MGTYRXN1_129
MGT
CAPI_0_RX8_P
MGTYRXP1_129
MGT
CAPI_0_RX9_N
MGTYRXN2_129
MGT
CAPI_0_RX9_P
MGTYRXP2_129
MGT
CAPI_0_TX0_N
MGTYTXN0_128
MGT
CAPI_0_TX0_P
MGTYTXP0_128
MGT
CAPI_0_TX1_N
MGTYTXN1_128
Table 9 : Complete Pinout Table (continued on next page)
MGT
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ADM-PCIE-9H7 User Manual
Pin Number
AJ48 AE45 AE44 AJ45 AJ44 AH47 AH46 AG49 AG48 AG45 AG44 AF47 AF46 AD43 AD42
BP29 BP28 BP31 AD52 AD51 AC54 AC53 V52 V51 AC50 AC49 AB52 AB51 AA54 AA53 Y52
Y51 W54 W53 AD47 AD46
Signal Name
Pin Name
Bank Voltage
CAPI_0_TX1_P
MGTYTXP1_128
CAPI_0_TX10_N
MGTYTXN3_129
CAPI_0_TX10_P
MGTYTXP3_129
CAPI_0_TX2_N
MGTYTXN2_128
CAPI_0_TX2_P
MGTYTXP2_128
CAPI_0_TX3_N
MGTYTXN3_128
CAPI_0_TX3_P
MGTYTXP3_128
CAPI_0_TX7_N
MGTYTXN0_129
CAPI_0_TX7_P
MGTYTXP0_129
CAPI_0_TX8_N
MGTYTXN1_129
CAPI_0_TX8_P
MGTYTXP1_129
CAPI_0_TX9_N
MGTYTXN2_129
CAPI_0_TX9_P
MGTYTXP2_129
CAPI_1_CLK1_PIN_N
MGTREFCLK0N_130
CAPI_1_CLK1_PIN_P
MGTREFCLK0P_130
CAPI_1_I2C_SCL_1V8
IO_L2N_T0L_N3_64
CAPI_1_I2C_SDA_1V8
IO_L2P_T0L_N2_64
CAPI_1_INT/RESET_1V8
IO_L3N_T0L_N5_AD15N_64
CAPI_1_RX0_N
MGTYRXN0_130
CAPI_1_RX0_P
MGTYRXP0_130
CAPI_1_RX1_N
MGTYRXN1_130
CAPI_1_RX1_P
MGTYRXP1_130
CAPI_1_RX10_N
MGTYRXN3_131
CAPI_1_RX10_P
MGTYRXP3_131
CAPI_1_RX2_N
MGTYRXN2_130
CAPI_1_RX2_P
MGTYRXP2_130
CAPI_1_RX3_N
MGTYRXN3_130
CAPI_1_RX3_P
MGTYRXP3_130
CAPI_1_RX7_N
MGTYRXN0_131
CAPI_1_RX7_P
MGTYRXP0_131
CAPI_1_RX8_N
MGTYRXN1_131
CAPI_1_RX8_P
MGTYRXP1_131
CAPI_1_RX9_N
MGTYRXN2_131
CAPI_1_RX9_P
MGTYRXP2_131
CAPI_1_TX0_N
MGTYTXN0_130
CAPI_1_TX0_P
MGTYTXP0_130
Table 9 : Complete Pinout Table (continued on next page)
MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT REFCLK MGT REFCLK 1.8 (LVCMOS18) 1.8 (LVCMOS18) 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT
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ADM-PCIE-9H7 User Manual
Pin Number
AC45 AC44 W45 W44 AB47 AB46 AA49 AA48 AA45 AA44 Y47 Y46 W49 W48 BD14 BE43
BJ53
BJ52
AR41 AR40 AN41 AN40 T12 T13 P43 P42 BG10 AY52 AY51 AW54 AW53 AW50 AW49
AV52
Signal Name
Pin Name
Bank Voltage
CAPI_1_TX1_N
MGTYTXN1_130
MGT
CAPI_1_TX1_P
MGTYTXP1_130
MGT
CAPI_1_TX10_N
MGTYTXN3_131
MGT
CAPI_1_TX10_P
MGTYTXP3_131
MGT
CAPI_1_TX2_N
MGTYTXN2_130
MGT
CAPI_1_TX2_P
MGTYTXP2_130
MGT
CAPI_1_TX3_N
MGTYTXN3_130
MGT
CAPI_1_TX3_P
MGTYTXP3_130
MGT
CAPI_1_TX7_N
MGTYTXN0_131
MGT
CAPI_1_TX7_P
MGTYTXP0_131
MGT
CAPI_1_TX8_N
MGTYTXN1_131
MGT
CAPI_1_TX8_P
MGTYTXP1_131
MGT
CAPI_1_TX9_N
MGTYTXN2_131
MGT
CAPI_1_TX9_P
MGTYTXP2_131
MGT
CCLK
CCLK_0
STARTUPE3
EMCCLK_B
IO_L24P_T3U_N10_EMCCLK_65
1.8 (LVCMOS18)
FABRIC_SRC_CLK_PIN_N IO_L13N_T2L_N1_GC_QBC_66
1.8 (LVDS with DIFF_TERM_ADV)
FABRIC_SRC_CLK_PIN_P IO_L13P_T2L_N0_GC_QBC_66
1.8 (LVDS with DIFF_TERM_ADV)
FIREFLY_CLK_0_PIN_N
MGTREFCLK0N_125
MGT REFCLK
FIREFLY_CLK_0_PIN_P
MGTREFCLK0P_125
MGT REFCLK
FIREFLY_CLK_1_PIN_N
MGTREFCLK0N_126
MGT REFCLK
FIREFLY_CLK_1_PIN_P
MGTREFCLK0P_126
MGT REFCLK
FIREFLY_CLK_2_PIN_N
MGTREFCLK0N_234
MGT REFCLK
FIREFLY_CLK_2_PIN_P
MGTREFCLK0P_234
MGT REFCLK
FIREFLY_CLK_3_PIN_N
MGTREFCLK0N_135
MGT REFCLK
FIREFLY_CLK_3_PIN_P
MGTREFCLK0P_135
MGT REFCLK
FIREFLY0_MODPRS_L
IO_L21P_T3L_N4_AD8P_68
1.8 (LVCMOS18)
FIREFLY0_RX0_N
MGTYRXN0_125
MGT
FIREFLY0_RX0_P
MGTYRXP0_125
MGT
FIREFLY0_RX1_N
MGTYRXN1_125
MGT
FIREFLY0_RX1_P
MGTYRXP1_125
MGT
FIREFLY0_RX2_N
MGTYRXN2_125
MGT
FIREFLY0_RX2_P
MGTYRXP2_125
MGT
FIREFLY0_RX3_N
MGTYRXN3_125
Table 9 : Complete Pinout Table (continued on next page)
MGT
Complete Pinout Table ad-ug-1341_v1_5.pdf
Page 27
ADM-PCIE-9H7 User Manual
Pin Number
AV51 BP11 BP12 AY47 AY46 AW45 AW44 AV47 AV46 AU45 AU44 BG9 BC54 BC53 BB52 BB51
BA54 BA53 BA50 BA49 BP13 BP14 BC49 BC48 BC45 BC44 BB47 BB46 BA45 BA44 BF12
AU54 AU53 AT52 AT51 AR54
Signal Name
Pin Name
Bank Voltage
FIREFLY0_RX3_P
MGTYRXP3_125
FIREFLY0_SCL_1V8
IO_L1N_T0L_N1_DBC_68
FIREFLY0_SDA_1V8
IO_L1P_T0L_N0_DBC_68
FIREFLY0_TX0_N
MGTYTXN0_125
FIREFLY0_TX0_P
MGTYTXP0_125
FIREFLY0_TX1_N
MGTYTXN1_125
FIREFLY0_TX1_P
MGTYTXP1_125
FIREFLY0_TX2_N
MGTYTXN2_125
FIREFLY0_TX2_P
MGTYTXP2_125
FIREFLY0_TX3_N
MGTYTXN3_125
FIREFLY0_TX3_P
MGTYTXP3_125
FIREFLY1_MODPRS_L
IO_L21N_T3L_N5_AD8N_68
FIREFLY1_RX0_N
MGTYRXN0_124
FIREFLY1_RX0_P
MGTYRXP0_124
FIREFLY1_RX1_N
MGTYRXN1_124
FIREFLY1_RX1_P
MGTYRXP1_124
FIREFLY1_RX2_N
MGTYRXN2_124
FIREFLY1_RX2_P
MGTYRXP2_124
FIREFLY1_RX3_N
MGTYRXN3_124
FIREFLY1_RX3_P
MGTYRXP3_124
FIREFLY1_SCL_1V8
IO_L2N_T0L_N3_68
FIREFLY1_SDA_1V8
IO_L2P_T0L_N2_68
FIREFLY1_TX0_N
MGTYTXN0_124
FIREFLY1_TX0_P
MGTYTXP0_124
FIREFLY1_TX1_N
MGTYTXN1_124
FIREFLY1_TX1_P
MGTYTXP1_124
FIREFLY1_TX2_N
MGTYTXN2_124
FIREFLY1_TX2_P
MGTYTXP2_124
FIREFLY1_TX3_N
MGTYTXN3_124
FIREFLY1_TX3_P
MGTYTXP3_124
FIREFLY2_MODPRS_L
IO_L22P_T3U_N6_DBC_AD0P_68
FIREFLY2_RX0_N
MGTYRXN0_126
FIREFLY2_RX0_P
MGTYRXP0_126
FIREFLY2_RX1_N
MGTYRXN1_126
FIREFLY2_RX1_P
MGTYRXP1_126
FIREFLY2_RX2_N
MGTYRXN2_126
Table 9 : Complete Pinout Table (continued on next page)
MGT 1.8 (LVCMOS18) 1.8 (LVCMOS18)
MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT
1.8 (LVCMOS18) 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18)
MGT MGT MGT MGT MGT
Page 28
Complete Pinout Table ad-ug-1341_v1_5.pdf
ADM-PCIE-9H7 User Manual
Pin Number
AR53 AP52 AP51 BN12 BM12 AU49 AU48 AT47 AT46 AR49 AR48 AR45 AR44 BF11 AN54
AN53 AN50 AN49 AM52 AM51 AL54 AL53 BN14 BN15 AP47 AP46 AN45 AN44 AM47 AM46
AL45 AL44 BE11 L1 L2 K3**
Signal Name
Pin Name
Bank Voltage
FIREFLY2_RX2_P
MGTYRXP2_126
FIREFLY2_RX3_N
MGTYRXN3_126
FIREFLY2_RX3_P
MGTYRXP3_126
FIREFLY2_SCL_1V8
IO_L3N_T0L_N5_AD15N_68
FIREFLY2_SDA_1V8
IO_L3P_T0L_N4_AD15P_68
FIREFLY2_TX0_N
MGTYTXN0_126
FIREFLY2_TX0_P
MGTYTXP0_126
FIREFLY2_TX1_N
MGTYTXN1_126
FIREFLY2_TX1_P
MGTYTXP1_126
FIREFLY2_TX2_N
MGTYTXN2_126
FIREFLY2_TX2_P
MGTYTXP2_126
FIREFLY2_TX3_N
MGTYTXN3_126
FIREFLY2_TX3_P
MGTYTXP3_126
FIREFLY3_MODPRS_L
IO_L22N_T3U_N7_DBC_AD0N_68
FIREFLY3_RX0_N
MGTYRXN0_127
FIREFLY3_RX0_P
MGTYRXP0_127
FIREFLY3_RX1_N
MGTYRXN1_127
FIREFLY3_RX1_P
MGTYRXP1_127
FIREFLY3_RX2_N
MGTYRXN2_127
FIREFLY3_RX2_P
MGTYRXP2_127
FIREFLY3_RX3_N
MGTYRXN3_127
FIREFLY3_RX3_P
MGTYRXP3_127
FIREFLY3_SCL_1V8
IO_L4N_T0U_N7_DBC_AD7N_68
FIREFLY3_SDA_1V8
IO_L4P_T0U_N6_DBC_AD7P_68
FIREFLY3_TX0_N
MGTYTXN0_127
FIREFLY3_TX0_P
MGTYTXP0_127
FIREFLY3_TX1_N
MGTYTXN1_127
FIREFLY3_TX1_P
MGTYTXP1_127
FIREFLY3_TX2_N
MGTYTXN2_127
FIREFLY3_TX2_P
MGTYTXP2_127
FIREFLY3_TX3_N
MGTYTXN3_127
FIREFLY3_TX3_P
MGTYTXP3_127
FIREFLY4_MODPRS_L
IO_L23P_T3U_N8_68
FIREFLY4_RX0_N
MGTYRXN0_234
FIREFLY4_RX0_P
MGTYRXP0_234
FIREFLY4_RX1_N
MGTYRXN1_234
Table 9 : Complete Pinout Table (continued on next page)
MGT MGT MGT 1.8 (LVCMOS18) 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18) 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18) MGT MGT MGT
Complete Pinout Table ad-ug-1341_v1_5.pdf
Page 29
ADM-PCIE-9H7 User Manual
Pin Number
K4 J1 J2 H3 H4 BM13 BM14 L6 L7 L10 L11 K8 K9 J6 J7
BF10 G1 G2 F3 F4 E1 E2 D3 D4 BM15 BL15 G6 G7 E6 E7
C6 C7 A5 A6 BE10 G54
Signal Name
Pin Name
Bank Voltage
FIREFLY4_RX1_P
MGTYRXP1_234
FIREFLY4_RX2_N
MGTYRXN2_234
FIREFLY4_RX2_P
MGTYRXP2_234
FIREFLY4_RX3_N
MGTYRXN3_234
FIREFLY4_RX3_P
MGTYRXP3_234
FIREFLY4_SCL_1V8
IO_L5N_T0U_N9_AD14N_68
FIREFLY4_SDA_1V8
IO_L5P_T0U_N8_AD14P_68
FIREFLY4_TX0_N
MGTYTXN0_234
FIREFLY4_TX0_P
MGTYTXP0_234
FIREFLY4_TX1_N
MGTYTXN1_234
FIREFLY4_TX1_P
MGTYTXP1_234
FIREFLY4_TX2_N
MGTYTXN2_234
FIREFLY4_TX2_P
MGTYTXP2_234
FIREFLY4_TX3_N
MGTYTXN3_234
FIREFLY4_TX3_P
MGTYTXP3_234
FIREFLY5_MODPRS_L
IO_L23N_T3U_N9_68
FIREFLY5_RX0_N
MGTYRXN0_235
FIREFLY5_RX0_P
MGTYRXP0_235
FIREFLY5_RX1_N
MGTYRXN1_235
FIREFLY5_RX1_P
MGTYRXP1_235
FIREFLY5_RX2_N
MGTYRXN2_235
FIREFLY5_RX2_P
MGTYRXP2_235
FIREFLY5_RX3_N
MGTYRXN3_235
FIREFLY5_RX3_P
MGTYRXP3_235
FIREFLY5_SCL_1V8
IO_L6N_T0U_N11_AD6N_68
FIREFLY5_SDA_1V8
IO_L6P_T0U_N10_AD6P_68
FIREFLY5_TX0_N
MGTYTXN0_235
FIREFLY5_TX0_P
MGTYTXP0_235
FIREFLY5_TX1_N
MGTYTXN1_235
FIREFLY5_TX1_P
MGTYTXP1_235
FIREFLY5_TX2_N
MGTYTXN2_235
FIREFLY5_TX2_P
MGTYTXP2_235
FIREFLY5_TX3_N
MGTYTXN3_235
FIREFLY5_TX3_P
MGTYTXP3_235
FIREFLY6_MODPRS_L
IO_L24P_T3U_N10_68
FIREFLY6_RX0_N
MGTYRXN0_135
Table 9 : Complete Pinout Table (continued on next page)
MGT MGT MGT MGT MGT 1.8 (LVCMOS18) 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18) 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18) MGT
Page 30
Complete Pinout Table ad-ug-1341_v1_5.pdf
ADM-PCIE-9H7 User Manual
Pin Number G53
F52 F51 E54 E53 D52 D51 BP9 BN11 G49 G48 E49 E48 C49
C48 A50 A49 BE9 L54 L53 K52 K51 J54 J53 H52 H51 BM10 BP8
L49 L48 L45 L44 K47 K46 J49 J48**
Signal Name
Pin Name
Bank Voltage
FIREFLY6_RX0_P
MGTYRXP0_135
FIREFLY6_RX1_N
MGTYRXN1_135
FIREFLY6_RX1_P
MGTYRXP1_135
FIREFLY6_RX2_N
MGTYRXN2_135
FIREFLY6_RX2_P
MGTYRXP2_135
FIREFLY6_RX3_N
MGTYRXN3_135
FIREFLY6_RX3_P
MGTYRXP3_135
FIREFLY6_SCL_1V8
IO_L7P_T1L_N0_QBC_AD13P_68
FIREFLY6_SDA_1V8
IO_T0U_N12_VRP_68
FIREFLY6_TX0_N
MGTYTXN0_135
FIREFLY6_TX0_P
MGTYTXP0_135
FIREFLY6_TX1_N
MGTYTXN1_135
FIREFLY6_TX1_P
MGTYTXP1_135
FIREFLY6_TX2_N
MGTYTXN2_135
FIREFLY6_TX2_P
MGTYTXP2_135
FIREFLY6_TX3_N
MGTYTXN3_135
FIREFLY6_TX3_P
MGTYTXP3_135
FIREFLY7_MODPRS_L
IO_L24N_T3U_N11_68
FIREFLY7_RX0_N
MGTYRXN0_134
FIREFLY7_RX0_P
MGTYRXP0_134
FIREFLY7_RX1_N
MGTYRXN1_134
FIREFLY7_RX1_P
MGTYRXP1_134
FIREFLY7_RX2_N
MGTYRXN2_134
FIREFLY7_RX2_P
MGTYRXP2_134
FIREFLY7_RX3_N
MGTYRXN3_134
FIREFLY7_RX3_P
MGTYRXP3_134
FIREFLY7_SCL_1V8
IO_L8P_T1L_N2_AD5P_68
FIREFLY7_SDA_1V8
IO_L7N_T1L_N1_QBC_AD13N_68
FIREFLY7_TX0_N
MGTYTXN0_134
FIREFLY7_TX0_P
MGTYTXP0_134
FIREFLY7_TX1_N
MGTYTXN1_134
FIREFLY7_TX1_P
MGTYTXP1_134
FIREFLY7_TX2_N
MGTYTXN2_134
FIREFLY7_TX2_P
MGTYTXP2_134
FIREFLY7_TX3_N
MGTYTXN3_134
FIREFLY7_TX3_P
MGTYTXP3_134
Table 9 : Complete Pinout Table (continued on next page)
MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18) 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT 1.8 (LVCMOS18) 1.8 (LVCMOS18) MGT MGT MGT MGT MGT MGT MGT MGT
Complete Pinout Table ad-ug-1341_v1_5.pdf
Page 31
ADM-PCIE-9H7 User Manual
Pin Number
BC15 BP47 AW15 AY15 AY14 AY13
BE45
BE46
BF42 BF43 BJ32 BH32 BF36 BF35 BG32 BF32 BK30 BH35 BH34 BG29 BG33 BH29 BG30
BF31 BH30 BJ29 BJ31 BK29 AN14 AN15 AR14 AR15 AL1 AL2
Signal Name
Pin Name
Bank Voltage
FPGA_FLASH_CE0_L
RDWR_FCS_B_0
STARTUPE3
FPGA_FLASH_CE1_L
IO_L2N_T0L_N3_FWE_FCS2_B_65
1.8 (LVCMOS18)
FPGA_FLASH_DQ0
D00_MOSI_0
STARTUPE3
FPGA_FLASH_DQ1
D01_DIN_0
STARTUPE3
FPGA_FLASH_DQ2
D02_0
STARTUPE3
FPGA_FLASH_DQ3
D03_0
STARTUPE3
FPGA_FLASH_DQ4
IO_L22P_T3U_N6_DBC_AD0P _D04_65
1.8 (LVCMOS18)
FPGA_FLASH_DQ5
IO_L22N_T3U_N7_DBC_AD0N _D05_65
1.8 (LVCMOS18)
FPGA_FLASH_DQ6
IO_L21P_T3L_N4_AD8P_D06_65
1.8 (LVCMOS18)
FPGA_FLASH_DQ7
IO_L21N_T3L_N5_AD8N_D07_65
1.8 (LVCMOS18)
GPIO_0_1V8_N
IO_L13N_T2L_N1_GC_QBC_64 1.8 (LVDS or LVCMOS18)
GPIO_0_1V8_P
IO_L13P_T2L_N0_GC_QBC_64 1.8 (LVDS or LVCMOS18)
GPIO_1_1V8_N
IO_L17N_T2U_N9_AD10N_64
1.8 (LVDS or LVCMOS18)
GPIO_1_1V8_P
IO_L17P_T2U_N8_AD10P_64
1.8 (LVDS or LVCMOS18)
GPIO_10
IO_L21N_T3L_N5_AD8N_64
1.8 ( LVCMOS18)
GPIO_11
IO_L23P_T3U_N8_64
1.8 ( LVCMOS18)
GPIO_12
IO_L22N_T3U_N7_DBC_AD0N_64
1.8 ( LVCMOS18)
GPIO_2_1V8_N
IO_L18N_T2U_N11_AD2N_64
1.8 (LVDS or LVCMOS18)
GPIO_2_1V8_P
IO_L18P_T2U_N10_AD2P_64
1.8 (LVDS or LVCMOS18)
GPIO_3
IO_L19P_T3L_N0_DBC_AD9P_64
1.8 ( LVCMOS18)
GPIO_4
IO_T2U_N12_64
1.8 ( LVCMOS18)
GPIO_5
IO_L20P_T3L_N2_AD1P_64
1.8 ( LVCMOS18)
GPIO_6
IO_L19N_T3L_N1_DBC_AD9N_64
1.8 ( LVCMOS18)
GPIO_7
IO_L21P_T3L_N4_AD8P_64
1.8 ( LVCMOS18)
GPIO_8
IO_L20N_T3L_N3_AD1N_64
1.8 ( LVCMOS18)
GPIO_9
IO_L22P_T3U_N6_DBC_AD0P_64
1.8 ( LVCMOS18)
OPTICAL_INT_1V8_L
IO_L24N_T3U_N11_64
1.8 ( LVCMOS18)
OPTICAL_RST_1V8_L
IO_T3U_N12_64
1.8 ( LVCMOS18)
PCIE_LCL_REFCLK_PIN_N
MGTREFCLK0N_226
MGT REFCLK
PCIE_LCL_REFCLK_PIN_P
MGTREFCLK0P_226
MGT REFCLK
PCIE_REFCLK_PIN_N
MGTREFCLK0N_225
MGT REFCLK
PCIE_REFCLK_PIN_P
MGTREFCLK0P_225
MGT REFCLK
PCIE_RX0_N
MGTYRXN3_227
MGT
PCIE_RX0_P
MGTYRXP3_227
Table 9 : Complete Pinout Table (continued on next page)
MGT
Page 32
Complete Pinout Table ad-ug-1341_v1_5.pdf
ADM-PCIE-9H7 User Manual
Pin Number
AM3 AM4 AW1 AW2 AY3 AY4 BA5 BA6 BA1 BA2 BB3 BB4 BC1 BC2 AN5 AN6 AN1 AN2 AP3
AP4 AR1 AR2 AT3 AT4 AU1 AU2 AV3 AV4 AW5 AW6 AL10 AL11 AM8 AM9 AW10 AW11
Signal Name
Pin Name
PCIE_RX1_N
MGTYRXN2_227
PCIE_RX1_P
MGTYRXP2_227
PCIE_RX10_N
MGTYRXN1_225
PCIE_RX10_P
MGTYRXP1_225
PCIE_RX11_N
MGTYRXN0_225
PCIE_RX11_P
MGTYRXP0_225
PCIE_RX12_N
MGTYRXN3_224
PCIE_RX12_P
MGTYRXP3_224
PCIE_RX13_N
MGTYRXN2_224
PCIE_RX13_P
MGTYRXP2_224
PCIE_RX14_N
MGTYRXN1_224
PCIE_RX14_P
MGTYRXP1_224
PCIE_RX15_N
MGTYRXN0_224
PCIE_RX15_P
MGTYRXP0_224
PCIE_RX2_N
MGTYRXN1_227
PCIE_RX2_P
MGTYRXP1_227
PCIE_RX3_N
MGTYRXN0_227
PCIE_RX3_P
MGTYRXP0_227
PCIE_RX4_N
MGTYRXN3_226
PCIE_RX4_P
MGTYRXP3_226
PCIE_RX5_N
MGTYRXN2_226
PCIE_RX5_P
MGTYRXP2_226
PCIE_RX6_N
MGTYRXN1_226
PCIE_RX6_P
MGTYRXP1_226
PCIE_RX7_N
MGTYRXN0_226
PCIE_RX7_P
MGTYRXP0_226
PCIE_RX8_N
MGTYRXN3_225
PCIE_RX8_P
MGTYRXP3_225
PCIE_RX9_N
MGTYRXN2_225
PCIE_RX9_P
MGTYRXP2_225
PCIE_TX0_PIN_N
MGTYTXN3_227
PCIE_TX0_PIN_P
MGTYTXP3_227
PCIE_TX1_PIN_N
MGTYTXN2_227
PCIE_TX1_PIN_P
MGTYTXP2_227
PCIE_TX10_PIN_N
MGTYTXN1_225
PCIE_TX10_PIN_P
MGTYTXP1_225
Table 9 : Complete Pinout Table (continued on next page)
Bank Voltage
MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT
MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT MGT
Complete Pinout Table ad-ug-1341_v1_5.pdf
Page 33
ADM-PCIE-9H7 User Manual
Pin Number
AY8 AY9 BA10 BA11 BB8 BB9 BC10 BC11 BC6 BC7 AN10 AN11 AP8 AP9 AR10 AR11 AR6
AR7 AT8 AT9 AU10 AU11 AU6 AU7 AV8 AV9 BF41 BG50 BJ54 BH54 BK54 BN35 AL5 AL6
AK3 AK4
Signal Name
Pin Name
Bank Voltage
PCIE_TX11_PIN_N
MGTYTXN0_225
MGT
PCIE_TX11_PIN_P
MGTYTXP0_225
MGT
PCIE_TX12_PIN_N
MGTYTXN3_224
MGT
PCIE_TX12_PIN_P
MGTYTXP3_224
MGT
PCIE_TX13_PIN_N
MGTYTXN2_224
MGT
PCIE_TX13_PIN_P
MGTYTXP2_224
MGT
PCIE_TX14_PIN_N
MGTYTXN1_224
MGT
PCIE_TX14_PIN_P
MGTYTXP1_224
MGT
PCIE_TX15_PIN_N
MGTYTXN0_224
MGT
PCIE_TX15_PIN_P
MGTYTXP0_224
MGT
PCIE_TX2_PIN_N
MGTYTXN1_227
MGT
PCIE_TX2_PIN_P
MGTYTXP1_227
MGT
PCIE_TX3_PIN_N
MGTYTXN0_227
MGT
PCIE_TX3_PIN_P
MGTYTXP0_227
MGT
PCIE_TX4_PIN_N
MGTYTXN3_226
MGT
PCIE_TX4_PIN_P
MGTYTXP3_226
MGT
PCIE_TX5_PIN_N
MGTYTXN2_226
MGT
PCIE_TX5_PIN_P
MGTYTXP2_226
MGT
PCIE_TX6_PIN_N
MGTYTXN1_226
MGT
PCIE_TX6_PIN_P
MGTYTXP1_226
MGT
PCIE_TX7_PIN_N
MGTYTXN0_226
MGT
PCIE_TX7_PIN_P
MGTYTXP0_226
MGT
PCIE_TX8_PIN_N
MGTYTXN3_225
MGT
PCIE_TX8_PIN_P
MGTYTXP3_225
MGT
PCIE_TX9_PIN_N
MGTYTXN2_225
MGT
PCIE_TX9_PIN_P
MGTYTXP2_225
MGT
PERST0_1V8_L
IO_T3U_N12_PERSTN0_65
1.8 ( LVCMOS18)
PPS_BUF_1V8
IO_L20N_T3L_N3_AD1N_66
1.8 ( LVCMOS18)
PWR_SENSE_PIN
IO_L16N_T2U_N7_QBC_AD3N_66
1.8 ( LVCMOS18)
PWR_SENSE0_PIN
IO_L16P_T2U_N6_QBC_AD3P_66
1.8 ( LVCMOS18)
PWR_SENSE1_PIN
IO_L15N_T2L_N5_AD11N_66
1.8 ( LVCMOS18)
QSFP_A_MODPRS_L
IO_L7N_T1L_N1_QBC_AD13N_64
1.8 ( LVCMOS18)
QSFP_A_RX0_N
MGTYRXN0_228
MGT
QSFP_A_RX0_P
MGTYRXP0_228
MGT
QSFP_A_RX1_N
MGTYRXN1_228
MGT
QSFP_A_RX1_P
MGTYRXP1_228
Table 9 : Complete Pinout Table (continued on next page)
MGT
Page 34
Complete Pinout Table ad-ug-1341_v1_5.pdf
ADM-PCIE-9H7 User Manual
Pin Number
AJ1 AJ2 AH3 AH4 BN29 BN30 AK8 AK9 AJ6 AJ7 AJ10 AJ11 AH8 AH9 BN34 AG1 AG2 AF3
AF4 AE1 AE2 AE5 AE6 BL30 BM30 AG6 AG7 AG10 AG11 AF8 AF9 AE10 AE11 BP34 AD3 AD4
Signal Name
Pin Name
Bank Voltage
QSFP_A_RX2_N
MGTYRXN2_228
MGT
QSFP_A_RX2_P
MGTYRXP2_228
MGT
QSFP_A_RX3_N
MGTYRXN3_228
MGT
QSFP_A_RX3_P
MGTYRXP3_228
MGT
QSFP_A_SCL_1V8
IO_L4P_T0U_N6_DBC_AD7P_64
1.8 ( LVCMOS18)
QSFP_A_SDA_1V8
IO_L4N_T0U_N7_DBC_AD7N_64
1.8 ( LVCMOS18)
QSFP_A_TX0_N
MGTYTXN0_228
MGT
QSFP_A_TX0_P
MGTYTXP0_228
MGT
QSFP_A_TX1_N
MGTYTXN1_228
MGT
QSFP_A_TX1_P
MGTYTXP1_228
MGT
QSFP_A_TX2_N
MGTYTXN2_228
MGT
QSFP_A_TX2_P
MGTYTXP2_228
MGT
QSFP_A_TX3_N
MGTYTXN3_228
MGT
QSFP_A_TX3_P
MGTYTXP3_228
MGT
QSFP_B_MODPRS_L
IO_L8P_T1L_N2_AD5P_64
1.8 ( LVCMOS18)
QSFP_B_RX0_N
MGTYRXN0_229
MGT
QSFP_B_RX0_P
MGTYRXP0_229
MGT
QSFP_B_RX1_N
MGTYRXN1_229
MGT
QSFP_B_RX1_P
MGTYRXP1_229
MGT
QSFP_B_RX2_N
MGTYRXN2_229
MGT
QSFP_B_RX2_P
MGTYRXP2_229
MGT
QSFP_B_RX3_N
MGTYRXN3_229
MGT
QSFP_B_RX3_P
MGTYRXP3_229
MGT
QSFP_B_SCL_1V8
IO_L5P_T0U_N8_AD14P_64
1.8 ( LVCMOS18)
QSFP_B_SDA_1V8
IO_L5N_T0U_N9_AD14N_64
1.8 ( LVCMOS18)
QSFP_B_TX0_N
MGTYTXN0_229
MGT
QSFP_B_TX0_P
MGTYTXP0_229
MGT
QSFP_B_TX1_N
MGTYTXN1_229
MGT
QSFP_B_TX1_P
MGTYTXP1_229
MGT
QSFP_B_TX2_N
MGTYTXN2_229
MGT
QSFP_B_TX2_P
MGTYTXP2_229
MGT
QSFP_B_TX3_N
MGTYTXN3_229
MGT
QSFP_B_TX3_P
MGTYTXP3_229
MGT
QSFP_C_MODPRS_L
IO_L8N_T1L_N3_AD5N_64
1.8 ( LVCMOS18)
QSFP_C_RX0_N
MGTYRXN0_230
MGT
QSFP_C_RX0_P
MGTYRXP0_230
Table 9 : Complete Pinout Table (continued on next page)
MGT
Complete Pinout Table ad-ug-1341_v1_5.pdf
Page 35
ADM-PCIE-9H7 User Manual
Pin Number
AC1 AC2 AC5 AC6 AB3 AB4 BN32 BP32 AD8 AD9 AC10 AC11 AB8 AB9 AA6 AA7 AJ14 AJ15
AD12 AD13 AG41 AG40 AB43 AB42 BL32 AA1 AA2 Y3 Y4 W1 W2 V3 V4 BM32 BM34 AA10
Signal Name
Pin Name
Bank Voltage
QSFP_C_RX1_N
MGTYRXN1_230
MGT
QSFP_C_RX1_P
MGTYRXP1_230
MGT
QSFP_C_RX2_N
MGTYRXN2_230
MGT
QSFP_C_RX2_P
MGTYRXP2_230
MGT
QSFP_C_RX3_N
MGTYRXN3_230
MGT
QSFP_C_RX3_P
MGTYRXP3_230
MGT
QSFP_C_SCL_1V8
IO_L6P_T0U_N10_AD6P_64
1.8 ( LVCMOS18)
QSFP_C_SDA_1V8
IO_L6N_T0U_N11_AD6N_64
1.8 ( LVCMOS18)
QSFP_C_TX0_N
MGTYTXN0_230
MGT
QSFP_C_TX0_P
MGTYTXP0_230
MGT
QSFP_C_TX1_N
MGTYTXN1_230
MGT
QSFP_C_TX1_P
MGTYTXP1_230
MGT
QSFP_C_TX2_N
MGTYTXN2_230
MGT
QSFP_C_TX2_P
MGTYTXP2_230
MGT
QSFP_C_TX3_N
MGTYTXN3_230
MGT
QSFP_C_TX3_P
MGTYTXP3_230
MGT
QSFP_CLK_0_PIN_N
MGTREFCLK0N_228
MGT REFCLK
QSFP_CLK_0_PIN_P
MGTREFCLK0P_228
MGT REFCLK
QSFP_CLK_1_PIN_N
MGTREFCLK0N_230
MGT REFCLK
QSFP_CLK_1_PIN_P
MGTREFCLK0P_230
MGT REFCLK
QSFP_CLK_2_PIN_N
MGTREFCLK0N_129
MGT REFCLK
QSFP_CLK_2_PIN_P
MGTREFCLK0P_129
MGT REFCLK
QSFP_CLK_3_PIN_N
MGTREFCLK0N_131
MGT REFCLK
QSFP_CLK_3_PIN_P
MGTREFCLK0P_131
MGT REFCLK
QSFP_D_MODPRS_L
IO_L9P_T1L_N4_AD12P_64
1.8 ( LVCMOS18)
QSFP_D_RX0_N
MGTYRXN0_231
MGT
QSFP_D_RX0_P
MGTYRXP0_231
MGT
QSFP_D_RX1_N
MGTYRXN1_231
MGT
QSFP_D_RX1_P
MGTYRXP1_231
MGT
QSFP_D_RX2_N
MGTYRXN2_231
MGT
QSFP_D_RX2_P
MGTYRXP2_231
MGT
QSFP_D_RX3_N
MGTYRXN3_231
MGT
QSFP_D_RX3_P
MGTYRXP3_231
MGT
QSFP_D_SCL_1V8
IO_T0U_N12_VRP_64
1.8 ( LVCMOS18)
QSFP_D_SDA_1V8
IO_L7P_T1L_N0_QBC_AD13P_64
1.8 ( LVCMOS18)
QSFP_D_TX0_N
MGTYTXN0_231
Table 9 : Complete Pinout Table (continued on next page)
MGT
Page 36
Complete Pinout Table ad-ug-1341_v1_5.pdf
ADM-PCIE-9H7 User Manual
Pin Number
AA11 Y8 Y9 W6 W7 W10 W11
BN49 BM49 BK48 BK49 BM50 BL51 BK50 BK51 BM52 BJ48 BL52 BJ49 BL53 BL50 BH47
BJ47 AV43 AV42 AL41 AL40 BL33 BK33 P12 P13 T43 T42 BJ51 BH51 BG54
Signal Name
Pin Name
Bank Voltage
QSFP_D_TX0_P
MGTYTXP0_231
MGT
QSFP_D_TX1_N
MGTYTXN1_231
MGT
QSFP_D_TX1_P
MGTYTXP1_231
MGT
QSFP_D_TX2_N
MGTYTXN2_231
MGT
QSFP_D_TX2_P
MGTYTXP2_231
MGT
QSFP_D_TX3_N
MGTYTXN3_231
MGT
QSFP_D_TX3_P
MGTYTXP3_231
MGT
QSFP_LED_AG0_1V8
IO_L3N_T0L_N5_AD15N_66
1.8 ( LVCMOS18)
QSFP_LED_AG1_1V8
IO_L4P_T0U_N6_DBC_AD7P_66
1.8 ( LVCMOS18)
QSFP_LED_AR0_1V8
IO_L7P_T1L_N0_QBC_AD13P_66
1.8 ( LVCMOS18)
QSFP_LED_AR1_1V8
IO_L7N_T1L_N1_QBC_AD13N_66
1.8 ( LVCMOS18)
QSFP_LED_BG0_1V8
IO_L4N_T0U_N7_DBC_AD7N_66
1.8 ( LVCMOS18)
QSFP_LED_BG1_1V8
IO_L5P_T0U_N8_AD14P_66
1.8 ( LVCMOS18)
QSFP_LED_BR0_1V8
IO_L8P_T1L_N2_AD5P_66
1.8 ( LVCMOS18)
QSFP_LED_BR1_1V8
IO_L8N_T1L_N3_AD5N_66
1.8 ( LVCMOS18)
QSFP_LED_CG0_1V8
IO_L5N_T0U_N9_AD14N_66
1.8 ( LVCMOS18)
QSFP_LED_CG0_1V8
IO_L9P_T1L_N4_AD12P_66
1.8 ( LVCMOS18)
QSFP_LED_CG1_1V8
IO_L6P_T0U_N10_AD6P_66
1.8 ( LVCMOS18)
QSFP_LED_CG1_1V8
IO_L9N_T1L_N5_AD12N_66
1.8 ( LVCMOS18)
QSFP_LED_DG0_1V8
IO_L6N_T0U_N11_AD6N_66
1.8 ( LVCMOS18)
QSFP_LED_DG1_1V8
IO_T0U_N12_VRP_66
1.8 ( LVCMOS18)
QSFP_LED_DR0_1V8
IO_L10P_T1U_N6_QBC_AD4P_66
1.8 ( LVCMOS18)
QSFP_LED_DR1_1V8
IO_L10N_T1U_N7_QBC_AD4N_66
1.8 ( LVCMOS18)
SI5328_0_OUT0_PIN_N
MGTREFCLK0N_124
MGT REFCLK
SI5328_0_OUT0_PIN_P
MGTREFCLK0P_124
MGT REFCLK
SI5328_0_OUT1_PIN_N
MGTREFCLK0N_127
MGT REFCLK
SI5328_0_OUT1_PIN_P
MGTREFCLK0P_127
MGT REFCLK
SI5328_0_REFCLK_IN_N
IO_L12N_T1U_N11_GC_64
MGT REFCLK
SI5328_0_REFCLK_IN_P
IO_L12P_T1U_N10_GC_64
MGT REFCLK
SI5328_1_OUT0_PIN_N
MGTREFCLK0N_235
MGT REFCLK
SI5328_1_OUT0_PIN_P
MGTREFCLK0P_235
MGT REFCLK
SI5328_1_OUT1_PIN_N
MGTREFCLK0N_134
MGT REFCLK
SI5328_1_OUT1_PIN_P
MGTREFCLK0P_134
MGT REFCLK
SI5328_1_REFCLK_IN_N
IO_L11N_T1U_N9_GC_66
MGT REFCLK
SI5328_1_REFCLK_IN_P
IO_L11P_T1U_N8_GC_66
MGT REFCLK
SI5328_1V8_SCL
IO_L17N_T2U_N9_AD10N_66
Table 9 : Complete Pinout Table (continued on next page)
MGT REFCLK
Complete Pinout Table ad-ug-1341_v1_5.pdf
Page 37
ADM-PCIE-9H7 User Manual
Pin Number BG53 AG14 AG15
AB12 AB13 BH52 BG52 BF51 BE49 BE50 BD51 BM48 BF53 BG48 BG49 BE54 BE53 BF52
BF47
Signal Name
SI5328_1V8_SDA SI5328_2_OUT0_PIN_N SI5328_2_OUT0_PIN_P SI5328_2_OUT1_PIN_N
SI5328_2_OUT1_PIN_P SI5328_2_REFCLK_IN_N SI5328_2_REFCLK_IN_P
SI5328_RST_1V8_L SPARE_SCL SPARE_SDA SPARE_WP
SRVC_MD_L_1V8 USER_LED_G0_1V8 USER_LED_G1_1V8 USER_LED_G2_1V8 USER_LED_G3_1V8
USER_LED_R0_1V8
USR_SW_0 USR_SW_1
Pin Name
IO_L17P_T2U_N8_AD10P_66 MGTREFCLK0N_229 MGTREFCLK0P_229 MGTREFCLK0N_231
MGTREFCLK0P_231
IO_L14N_T2L_N3_GC_66 IO_L14P_T2L_N2_GC_66 IO_L21P_T3L_N4_AD8P_66
IO_L23P_T3U_N8_66 IO_L23N_T3U_N9_66 IO_L24P_T3U_N10_66 IO_L3P_T0L_N4_AD15P_66
IO_T2U_N12_66 IO_L19P_T3L_N0_DBC_AD9P_66 IO_L19N_T3L_N1_DBC_AD9N_66
IO_L18N_T2U_N11_AD2N_66 IO_L18P_T2U_N10_AD2P_66 IO_L21N_T3L_N5_AD8N_66
IO_L22P_T3U_N6_DBC_AD0P_66
Table 9 : Complete Pinout Table ** Pin fields marked are not present in VU35P (FireFly 4-7)
Bank Voltage
MGT REFCLK MGT REFCLK MGT REFCLK MGT REFCLK MGT REFCLK MGT REFCLK MGT REFCLK
1.8 ( LVCMOS18) 1.8 ( LVCMOS18) 1.8 ( LVCMOS18) 1.8 ( LVCMOS18) 1.8 (
LVCMOS18) 1.8 ( LVCMOS18) 1.8 ( LVCMOS18) 1.8 ( LVCMOS18) 1.8 ( LVCMOS18) 1.8
( LVCMOS18) 1.8 ( LVCMOS18) 1.8 ( LVCMOS18)
Page 38
Complete Pinout Table ad-ug-1341_v1_5.pdf
ADM-PCIE-9H7 User Manual
Revision History
Date 17 Jul 2018 20 Sep 2018
19 Oct 2018 10 Jun 2019 28 Jul 2022
17 Jul 2023
Revision 1.0 1.1
1.2 1.3 1.4
1.5
Changed By K. Roth
K. Roth
Initial Release
Nature of Change
Added thermal data, added FQSFP details, added link to linux avr2util.
K. Roth
Added section Battery Backed Encryption, corrected grammatical errors, clarified FireFly site reduction from 8 to 4 with VU35P
K. Roth K. Roth
Corrected LED labeling mistakes in section LEDs
Clarified section Power Requirements in that both the PCIE AUX power cable and
the PCIE edge are required for the baord to power on.
K. Roth
Corrected clock index numbers in USB Interface for setclk commands, add table for PCB dimmension in Board Information
Address: Suite L4A, 160 Dundee Street,
Edinburgh, EH11 1DQ, UK
Telephone: +44 131 558 2600
Fax:
+44 131 558 2700
email:
website: http://www.alpha-data.com
5.0
Address: 10822 West Toller Drive, Suite 250
Littleton, CO 80127
Telephone: (303) 954 8768
Fax:
(866) 820 9956 – toll free
email:
website: http://www.alpha-data.com
References
- Salesforce Data Cloud - Salesforce.com US
- Alpha Data - committed to providing solutions
- Xilinx Power Estimator (XPE)
- support.alpha-data.com - /pub/firmware/utilities/linux/
- support.alpha-data.com - /pub/firmware/utilities/windows/
- Connectors, Cables, Optics, RF, Silicon to Silicon Solutions | Samtec
- Silicon Labs