ALPHA DATA VA600-RTM Evaluation Board User Manual

VA600-RTM
User Manual
Document Revision: 1.2
9th November 2023

VA600-RTM Evaluation Board

© 2023 Copyright Alpha Data Parallel Systems Ltd.
All rights reserved.
This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Ltd.

Address: Suite L4A, 160 Dundee Street,
Edinburgh, EH11 1DQ, UK
Telephone: +44 131 558 2600
Fax: +44 131 558 2700
email: sales@alpha-data.com
website: http://www.alpha-data.com| 10822 West Toller Drive, Suite 250
Littleton, CO 80127
(303) 954 8768
(866) 820 9956 – toll free
sales@alpha-data.com
http://www.alpha-data.com

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Introduction

The VA600-RTM is a 6U VPX RTM for the ADK-VA600 6U Space VPX reference platform. It has high-speed and low-speed IO breakout for the Versal board, as well as it’s own Zynq MPSoC FPGA connected to the Versal SMAP interface
1.1 Key Features
Key Features

• 6U VPX RTM with Zynq MPSoC for Versal SMAP control.
• Versal Debug Interfaces:
  • USB to UART converter
  • USB to JTAG converter
  • ADM SmartLynq+ compatible High-Speed Debug Port (HSDP).
  • RS-232 DB-9 serial output
• Versal IO Interfaces:
  • 8 8Gbps MGT lanes to two SF-8644 connectors
  • 3 10Gbps MGT lanes to three SFP+ connectors
  • 8 10Gbps MGT lanes to two Samtec FireFly connectors
  • Two SpaceWire interfaces
  • Gigabit Ethernet Port
  • External reference clock input
  • 40 Singled Ended GPIO
  • CAN Bus interface to GPIO connector
• On-Board Zynq MPSoC:
  • 4GB PS DDR4
  • 37 GPIOs to the FPGA fabric, enough to allow SMAP Passthrough
  • USB to UART converter
  • SD Card boot device
  • Gigabit Ethernet interface to PS
  • USB interface to PS
  • I2C/sideband signal connections to on-board transceivers
  • I2C interface to VPX backplane
  • 4 User controllable LEDs
  • 4 User controllable switches
  • On-Board voltage monitoring
  • Weight: 224g

Installation

2.1 Hardware Installation
2.1.1 Handling Instructions
The components on this board can be damaged by electrostatic discharge (ESD). To prevent damage, observe ESD precautions:
– Always wear a wrist-strap when handling the card
– Hold the board by the edges
– Avoid touching any components
– Store in ESD safe bag.
2.1.2 Cooling Requirements
The power dissipation of the board is highly dependent on the FPGA application. A power estimator spreadsheet is available on request from Alpha Data. This should be used in conjunction with Xilinx power estimation tools to determine the exact current requirements for each power rail.

Functional Description

3.1 Overview
3.1.1 Switch Definitions
There are two sets of eight DIP switches (16 switches in total) placed on the top of the board. Some switch states can be controlled using the FPGA IO. These signals are shown in the corresponding table.
The default switch states for SD card boot mode are SW2[8:1]:00000000 and SW1[8:1]:00001100.

Switch Ref.| Function| FPGA Pin| ON State| Off State
---|---|---|---|---
SW2-1| VA600 UART RS485 TE| K17| VA600 UART RS485 Termination Enabled| VA600 RS485 Termination Disabled
SW2-2| VA600 UART RS485 EN| J17| VA600 UART RS485 Mode| VA600 UART RS232 Mode
SW2-3| Bypass ZU4EG JTAG| –| ZU4EG removed from JTAG chain| ZU4EG included in JTAG chain
SW2-4| Bypass VPX JTAG| –| VPX Backplane removed from JTAG chain| VPX Backplane included in JTAG chain
SW2-5| VA600 USB- to-UART EN| –| VA600 USB-to-UART enabled (RS232/485 disabled)| VA600 USB-to-UART disabled (RS232/485 enabled)
SW2-6| ZU4EG Reset| –| ZU4EG held reset active| ZU4EG held reset cleared
SW2-7| VPX SYSRESET| –| VPX SYSRESET active| VPX SYSRESET cleared
SW2-8| VPX POR EN| –| RTM drives power on reset to VPX_SYSRESET| Leaves VPX_SYSRESET floating

Table 1 : SW2 Switch Definitions

Switch Ref.| Function| FPGA Pin| ON State| Off State
---|---|---|---|---
SW1-1| BootMode 0| –| See Table 11
SW1-2| BootMode 1| –| See Table 11
SW1-3| BootMode 2| –| See Table 11
SW1-4| BootMode 3| –| See Table 11
SW1-5| User switch 1| B11| FPGA Pin High| FPGA Pin Low
SW1-6| User switch 2| A10| FPGA Pin High| FPGA Pin Low
SW1-7| User switch 3| A12| FPGA Pin High| FPGA Pin Low
SW1-8| User switch 4| A11| FPGA Pin High| FPGA Pin Low

Table 2 : SW1 Switch Definitions
3.1.2 LED Definitions

Deasserted
D36(Red)| ZU4 PS Error Pin| PS Error Asserted| PS Error Deasserted
D39(Green)| VA600 Ethernet LED0| See VA600 User Guide
D40(Amber)| VA600 Ethernet LED1| See VA600 User Guide
D28(Green)| ZU4 UART RX Activity| Activity| No Activity
D29(Green)| ZU4 UART TX Activity| Activity| No Activity
D33(Green)| ZU4 Controlled LED 1| ZU4 Pin G1 High| ZU4 Pin G1 Low
D32(Green)| ZU4 Controlled LED 2| ZU4 Pin F1 High| ZU4 Pin F1 Low
D31(Green)| ZU4 Controlled LED 3| ZU4 Pin E1 High| ZU4 Pin E1 Low
D30(Green)| ZU4 Controlled LED 4| ZU4 Pin D1 High| ZU4 Pin D1 Low
D22(Green)| Versal Controlled LED 1| Versal Pin AR9 high| Versal Pin AR9 low
D23(Green)| Versal Controlled LED 2| Versal Pin AN8 high| Versal Pin AN8 low
D24(Green)| Versal Controlled LED 3| Versal Pin AP7 high| Versal Pin AP7 low

Table 3 : LED Definitions
3.2 Versal I/O

3.2.1 SFF-8644
A dual SFF-8644 connector is provided to break out VA600 MGT interfaces on banks 103 and 104. SFF J14A connects to bank 103 and J14B connects to bank 104. This can be used to bring out the VA600 PCIe over a cable.
The SFF-8644 interfaces connect to the ZU4EG PS I2C0 interface. Each SFF I2C interface has a bidirectional buffer with an enable control pin, controlled through PS MIO GPIO and PL GPIO. The pin should be driven high to enable the interface. The enables have a pull-down resistor so they can be undriven if unused. The pins to enable the SFF I2C interfaces are:

Table 4 : SFF I2C Enables
To control the transceiver’s I2C interface, see section: I2C Interface
3.2.2 SFP+
Three SFP+ cages are connected to VA600 MGT bank 105. SFP J32 connects to lane 1, SFP J33 connects to lane 2 and SFP J34 connects to lane 3. Lane 0 is used for the High-Speed Debug Port (HSDP).
The SFP I2C interfaces connect to the ZU4EG PS I2C0 interface. Each SFP I2C interface has a bidirectional buffer with an enable control pin, controlled through PS MIO GPIO. The pin should be driven high to enable the interface. The enables have a pull-down resistor so they can be undriven if unused. The pins to enable the SFP I2C interfaces are:

Table 5 : SFP I2C Enables
To control the transceiver’s I2C interface, see section: I2C Interface
3.2.3 FireFly
Two FireFly connectors are connected to VA600 MGT banks 106 and 206. FireFly 1 J19 connects to bank 106 and FireFly 2 J21 connects to bank 206. Each FireFly connector has the sideband signals: I2C_SDA, I2C_SCL, MODPRES_L, MODSEL_L, INT_L, RESET_L.
RESET_L and INT_L are common to both FireFly transceivers

Table 6 : FireFly Sideband Signals
To control the transceiver’s I2C interface, see section: I2C Interface
3.2.4 UART/RS232/RS485
The RS232/485 interface connects to the Versal pins LPD MIO17 (TX) and LDP MIO16 (RX). The table below describes the behaviour of the switches that control the RS232/485 interface.

Switch Ref.| Function| FPGA Pin| ON State| Off State
---|---|---|---|---
SW2-1| VA600 UART RS485 TE| K17| VA600 UART RS485 Termination Enable| VA600 RS485 Termination Disable
SW2-2| VA600 UART RS485 EN| J17| VA600 UART RS485 Mode| VA600 UART RS232 Mode
SW2-5| VA600 USB-to- UART EN| –| VA600 USB-to-UART enabled (RS232/485 disabled)| VA600 USB-to-UART disabled (RS232/485 enabled)

Table 7 : SW2 RS232/485 Definitions
3.2.5 JTAG Interface
3.2.5.1 On-board JTAG Interface
A JTAG boundary scan chain is connected to either an on-board USB to JTAG converter, or 14-pin JTAG header J29. This allows the connection of a Xilinx JTAG cable for FPGA debug using the Xilinx tools. The on-board USB to JTAG converter is enabled whenever a USB connection is made.
The scan chain is shown in JTAG Boundary Scan Chain:

SW2-4 can be turned on to remove the VPX connector from the JTAG chain, leaving only the ZU4EG, and SW2-3 can be turned on to remove the ZU4EG from the JTAG chain, leaving only the VPX connector
3.2.5.2 JTAG Voltages
The on-board JTAG scan chain uses 3.3V. The VCC supply provided on J29 to the JTAG cable is +3.3V and is protected by a poly fuse rated at 350mA.
The JTAG signals at the VPX interface use 3.3V signals and are connected through level translators to the on-board scan chain.
3.2.6 High-Speed Debug Port (HSDP)
The VA600-RTM is compatible with the AMD SmartLynq+ JTAG cable, allowing 10Gb/s serial data transfer between the SmartLynq+ and the Versal device. The SmartLyqn+ supports JTAG, UART and HSDP over a single USB-C connection. The diagram below shows the full UART/JTAG/HSDP circuit:

3.2.7 SpaceWire
There are two spacewIre connectors, each of which contains 4 differential pairs. The differential pairs are driven by single-ended to differential converters on the VA600 board, so the P and N diff parts are shown as going to the same Versal pin in the table below. These signals use LVDS signalling levels, and can accept a -4V to +5V common mode voltage range.

Table 8 : SpaceWire Pinout
3.3 Clocks
The VA600-RTM provides a variety of clocking options using fixed oscillators. These clocks can be combined with the FPGA’s internal PLLs to generate a range of frequencies.

3.3.1 300MHz Reference Clock
The fixed 300MHz reference clock REFCLK_300M is a differential LVDS signal.
REFCLK_300M is used as the reference clock for the PL and can be used as a reference for the IO delay control block (IDELAYCTRL).

Signal| Frequency| FPGA Input| IO Standard| “P” pin| “N” pin
---|---|---|---|---|---
REFCLK_300M| 300 MHz| IO_L11_T1U_N8_GC_66| LVDS| D4| C4

Table 9 : 300MHz Connections
3.3.2 PS Reference Clock (PS_REF_CLK)
A 50MHz PS reference clock is provided for the ZU4EG processing system

Table 10 : PS_REF_CLK Connections
3.4 Zynq PS Block
3.4.1 Boot Modes

BootMode0 (SW1-1)| BootMode1 (SW1-2)| BootMode2 (SW1-3)| BootMode3 (SW1-4)| Boot Mode
---|---|---|---|---
ON| ON| ON| ON| JTAG
OFF| OFF| ON| ON| SD Flash
–| –| –| –| Reserved

Table 11 : Boot Mode Selection
3.4.2 MicroSD Flash Memory
A MicroSD card is used for storing executable code and data for the PS and PL, such as a bootloader, operating system and bitstream.
The SD Card can only be accessed by the PS.
3.4.3 PS DDR4 Memory
The VA600-RTM is fitted with one bank of PS DDR4 SDRAM. The bank is made up of a two 16-bit wide memory devices in parallel to provide a 32-bit data-path capable of running up to 1200MHz (DDR4-2400). 2GByte devices (Micron MT40A1G16RC-062) are fitted as standard to provide 4GByte of memory.
Full details of the interface and PS configuration example design are provided in the VA600-RTM example design.
3.4.4 I2C Interface
The on-board I2C devices are connected to an I2C bus from the PS of the ZU4EG. Devices that don’t have individual I2C enables (SFF/SFP connectors) use an I2C buffer with an enable pin. These enable signals are drive by the PS and each have a pull-down resistor so they are disabled by default.
The I2C interface can be accessed from the PS. The Alpha Data example design PetaLinux image includes i2c utilities such as i2cdetect, i2cget and i2cset.

3.4.5 Ethernet Interfaces
The VA600-RTM has one 1000BASE-T Ethernet interface.
The interface has a Marvell 88E1512 PHY, connected to the Zynq via RGMII.
The interface has three status LEDs. The functions of these are shown in Table 12 below.

Table 12 : Ethernet Status LEDs
3.4.6 Serial COM Port
There is one PS COM port connected to an on-board USB to serial converter. This USB to serial converter has a dedicated USB-C port that is separate from the Versal UART/JTAG connector.
3.4.7 USB Interface
The VA600-RTM has an external USB interface. The Zynq PS is configured as the USB host to the external interfaces.
3.5 PL Interfaces
3.5.1 I/O Bank Voltages
The FPGA IO is arranged in banks, each with their own power supply pins. The bank numbers, their voltage and function are shown in FPGA IO Banks. Full details of the IOSTANDARD required for each signal are given in the xdc constraints files of VA600-RTM example designs.

Table 13 : FPGA IO Banks
3.5.2 PL GPIO
There are 37 single ended GPIO pins from the FPGA to the VPX backplane. These connect to the Versal MIO pins and can be used as a 32-bit wide SMAP interface. There are also 37 GPIO pins between the FPGA and external SMAP connector J10, which can be used to pass the SMAP through the FPGA, for example if an external device is used to control the SMAP interface.
There is also a reset signal that can be driven by the ZU4EG to assert the Versal power-on reset, as the SMAP clock must be running when the Versal POR is released.
Mating cable is Samtec SQCD-025-XX.XX-TEU-TEU-3, where XX.XX is the cable length in inches. See https://www.samtec.com/products/sqcd for details.

3.6 Configuration
3.6.1 Power-Up Sequence
At power-up, the PS will load the first-stage bootloader from the memory interface selected by the Boot Mode select switches.
The first stage bootloader is responsible for configuring the FPGA and PS attached interfaces.
3.7 System Monitoring
The Zynq MPSoC on the VA600-RTM has the ability to monitor temperature and voltage to maintain a check on  the operation of the board.
Control algorithms within the microcontroller automatically check line voltages and on board temperatures. The Zynq can monitor it’s own power rails and temperatures. Supplies not monitored by the Zynq Sysmon are connected (though a resistor divider) to the Zynq’s ADC blocks.

Table 14 : Zynq ADC inputs

Example Design

A set of Vivado example designs, pinout/constraint files and Petalinux BSP are available at https://alpha-data.sharefile.com

Revision History

switches to RS232/RS485 diagram.

Address: Suite L4A, 160 Dundee Street,
Edinburgh, EH11 1DQ, UK
Telephone: +44 131 558 2600
Fax: +44 131 558 2700
email:sales@alpha-data.com
website:http://www.alpha-data.com 
Address: 10822 West Toller Drive, Suite 250
Littleton, CO 80127
Telephone: (303) 954 8768
Fax: (866) 820 9956 – toll free
email:sales@alpha-data.com
website:http://www.alpha-data.com

References

• ShareFile
• Salesforce Data Cloud - Salesforce.com US
• Alpha Data - committed to providing solutions
• SQCD - 0.635 mm Q Strip® High-Speed Coax Cable Assembly | Samtec

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