Cactus Technologies 245S Series Industrial pSLC Instruction Manual
- June 12, 2024
- Cactus Technologies
Table of Contents
- 245S Series Industrial pSLC
- Introduction to Cactus Technologies® Industrial pSLC -245S Series M.2
- Product Specifications
- Capacities
- Interface Description
- Electrical Specifications
- ATA Drive Register Set Definition and Protocol
- ATA Command Description
- S.M.A.R.T. Feature Set
- Appendix A. Ordering Information
- Appendix B.Technical Support Services
- Appendix C.Cactus Technologies® Worldwide Sales Offices
- Appendix D.Limited Warranty
- Read User Manual Online (PDF format)
- Download This Manual (PDF format)
Industrial pSLC
-245S series
M.2 SSD
Product Manual
245S Series Industrial pSLC
The information in this manual is preliminary and is subject to change without
notice. Cactus Technologies®, Limited shall not be liable for technical or
editorial errors or omissions contained herein; nor for incidental or
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Introduction to Cactus Technologies® Industrial pSLC -245S Series M.2
SSD Products
Features:
- Solid state design with no moving parts
- Capacities from 4GB to 128GB
- Available in M.2 2242, 2260 and 2280 form factors
- Compliant with Serial ATA 3.1 specifications
- Compliant with PCI Express M.2 specification, ver.1.0
- ATA-8 ACS2 compatible
- Supports Serial ATA Generation I/II/III transfer rate of 1.5/3.0/6.0 Gbps
- Supports ATA SMART Feature Set
- Supports ATA Security Feature Set
- Supports Data Set Management (TRIM)
- Supports NCQ w/ max. queue depth of 32
- Supports AHCI
- Supports DEVSLP
- True Psuedo-SLC mode operation
- ECC capable of correcting up to 66 bit errors per 1KB
- Enhanced error correction, < 1 error in 1014 bits read
- Voltage support: 3.3V±5%
Cactus Technologies® Industrial pSLC M.2 SATA SSD is a high capacity solid-
state flash memory product that complies with the Serial ATA 3.1 standard and
PCI Express M.2 1.0 standard and is functionally compatible with a SATA hard
disk drive. Cactus Technologies® Industrial pSLC M.2 SSD provides up to 128GB
of formatted storage capacity.
Cactus Technologies® Industrial pSLC M.2 SSD product uses high quality
industrial grade MLC NAND flash memory from Kioxia Corporation and operates in
true Psuedo-SLC mode (i.e. not Fast Page mode), thus resulting in enhanced
endurance and performance over standard MLC NAND flash. In addition, it
includes an on-drive intelligent controller that manages interface protocols,
data storage and retrieval as well as ECC, defect handling and diagnostics,
power management, and clock control. The controller’s firmware is upgradeable,
thus allowing feature enhancements and firmware updates while keeping the BOM
stable.
1.1. Supported Standards
Cactus Technologies® M.2 SSD is fully compatible with the following
specification:
- ATA 8/ACS2 Specification published by ANSI
- Serial ATA 3.1 Specification published by the Serial ATA International Organization
- PCI Express M.2 Specification 1.0 published by PCI SIG
1.2. Product Features
Cactus Technologies® Industrial pSLC M.2 SSD contains a high level,
intelligent controller.
This intelligent controller provides many capabilities including the
following:
- Standard ATA register and command set (same as found on most magnetic disk drives).
- Manages details of erasing and programming flash memory independent of the host system
- Sophisticated defect managing capabilities (similar to magnetic disk drives).
- Sophisticated system for error recovery using powerful error correction code (ECC).
- Intelligent power management for low power operation.
1.2.1. Host and Technology Independence
Cactus Technologies® Industrial pSLC M.2 SSD appears as a standard SATA disk
drive to the host system. The drive utilizes a 512-byte sector which is the
same as that in an IDE magnetic disk drive. To write or read a sector (or
multiple sectors), the host computer software simply issues an ATA Read or
Write command to the drive as per the SATA protocol. The host software then
waits for the command to complete. The host system does not get involved in
the details of how the flash memory is erased, programmed or read as this is
all managed by the built-in controller in the drive. Also, with the
intelligent on-board controller, the host system software will not require
changing as new flash memory evolves. Thus, systems that support the Cactus
Technologies® Industrial pSLC M.2 SSD products today will continue to work
with future Cactus Technologies® Industrial pSLC M.2 SSDs built with new flash
technology without having to update or change host software.
1.2.2. Defect and Error Management
Cactus Technologies® Industrial pSLC M.2 SSD contains a sophisticated defect
and error management system similar to those found in magnetic disk drives.
The defect management is completely transparent to the host and does not
consume any user data space. The soft error rate for Cactus Technologies®
Industrial pSLC M.2 SSD is much lower than that of magnetic disk drives. In
the extremely rare case where a read error does occur, the drive has
sophisticated ECC to recover the data.
These defect and error management systems, coupled with the solid-state
construction, give Cactus Technologies® Industrial pSLC M.2 SSDs unparalleled
reliability.
1.2.3. Power Supply Requirements
Cactus Technologies® Industrial pSLC M.2 SSD operates at a voltage range of
3.3 volts ± 5%.
Product Specifications
For all the following specifications, values are defined at ambient
temperature and nominal supply voltage unless otherwise stated.
2.1. System Environmental Specifications
Table 2-1. Environmental Specifications
| | Cactus Technologies ® Industrial pSLC M.2 SSD
---|---|---
Temperature| Operating:| 0° C to +70° C (Standard)
-40° C to +85° C (Extended)
Humidity| Operating & Non- Operating:| 8% to 95%, non-condensing
Vibration| Operating & Non- Operating:| 20G, MIL-STD-883G Method
2005.2, Condition A
Shock| Operating & Non- Operating:| 3,000 G, MIL-STD-883G
Method 2002.4, Condition C
Altitude (relative to sea level)| Operating & Non- Operating:| 100,000
feet maximum
Note: Extended temp. version is temperature screened via burn-in testing.
They are verified to work at the extended temperatures initially but long term
reliability may be reduced if the part is used at such temperatures for
extended period of time.
2.2. System Power Requirements
Table 2-2. Power Requirements
| | Cactus Technologies ® Industrial pSLC M.2 SSD
---|---|---
DC Input Voltage (VCC) 100 mV max. ripple (p-p)| | 3.3V ±5%
| | 2242
| | 4GB| 8GB| 16GB| 32GB| 64GB| 128GB
(Maximum Average Value)
See Notes.| Idle(mA):
Reading(mA):
Writing(mA):| 95
270
280| 110
340
330| 105
345
340| 100
395
440| 105
420
520| 105
485
665
| | 2260/2280
| | 4GB| 8GB| 16GB| 32GB| 64GB| 128GB
(Maximum Average Value)
See Notes.| Idle(mA):
Reading(mA):
Writing(mA):| 95
290
300| 95
330
330| 110
465
455| 105
475
495| 105
485
630| 100
495
680
NOTES: All values quoted are typical at ambient temperature and nominal
supply voltage unless otherwise stated.
Sleep mode is specified under the condition that all drive inputs are static
CMOS levels and in a “Not Busy“ operating state.
2.3. System Performance
All performance timings assume the drive controller is in the default
(i.e., fastest) mode.
Table 2-3. Performance
| | 2242| 2260/2280
---|---|---|---
Read Transfer Rate| 4GB| Up to 150MBytes/sec| Up to 150MBytes/sec
8GB| Up to 300MBytes/sec| Up to 300MBytes/sec
16GB| Up to 300MBytes/sec| Up to 540MBytes/sec
32GB| Up to 325MBytes/sec| Up to 540MBytes/sec
64GB| Up to 350MBytes/sec| Up to 540MBytes/sec
128GB| Up to 540MBytes/sec| Up to 540MBytes/sec
Write Transfer Rate| 4GB| Up to 70 MBytes/sec| Up to 70 MBytes/sec
8GB| Up to 140 MBytes/sec| Up to 135 MBytes/sec
16GB| Up to 120 MBytes/sec| Up to 265 MBytes/sec
32GB| Up to 225 Mbytes/sec| Up to 205 Mbytes/sec
64GB| Up to 315 Mbytes/sec| Up to 420 Mbytes/sec
128GB| Up to 450 MBytes/sec| Up to 450 MBytes/sec
2.4. System Reliability
Table 2-4. Reliability
Data Reliability | < 1 non-recoverable error in 1014 bits READ |
---|---|
Endurance (estimated TBW): | Up to 20TB/GB: |
4GB | 80TB |
8GB | 160TB |
16GB | 320TB |
32GB | 640TB |
64GB | 1280TB |
128GB | 2560TB |
Note: estimated TBW assumes workload consisting of mostly large block
writes; estimated TBW will be significantly reduced for workloads consisting
of mostly random, small block writes.
2.5. Physical Specifications
The following sections provide the physical specifications for Cactus
Technologies® Industrial pSLC M.2 SSD products.
2.5.1. M.2 2260 SSD Physical Specifications 2.5.2. M.2 2242 SSD Physical Specifications 2.5.3. M.2 2280 SSD Physical Specifications Note: the measurements for key details and device thickness for
2242, 2260 and 2280 form factors are identical.
Capacities
Cactus Technologies® Industrial pSLC M.2 SSD is available in 4, 8, 16, 32, 64 and 128GB capacities.
Interface Description
The following sections provide detailed information on the Cactus
Technologies® Industrial pSLC M.2 SSD interface.
4.1. M.2 SSD Pin Assignments and Pin Type
The signal/pin assignments and descriptions are listed in Table 3-5. Table 3-5. M.2 SSD Pin Assignments and Pin Type
Pin #| Pin Name| Description| Pin #| Pin Name|
Description
---|---|---|---|---|---
1| CONFIG_3| Connected to GND for SATA SSD| 2| 3.3V| 3.3V supply
3| GND| | 4| 3.3V|
5| N/C| No connect| 6| Reserved|
7| DNU| | 8| Reserved|
9| DNU| | 10| DAS/DSS| Drive activity
11| NC| No connect| 12| B Key
13| B Key| 14
15| 16
17| 18
19| 20| Reserved|
21| CONFIG_0| Connected to GND for SATA SSD| 22| Reserved|
23| DNU| | 24| Reserved|
25| DNU| | 26| Reserved|
27| GND| | 28| Reserved|
29| Reserved| | 30| Reserved|
31| Reserved| | 32| Reserved|
33| GND| | 34| Reserved|
35| Reserved| | 36| Reserved|
Pin #| Pin Name| Description| Pin #| Pin Name|
Description
---|---|---|---|---|---
37| Reserved| | 38| DEVSLP| Device Sleep control
39| GND| | 40| Reserved|
41| SATA RX+| Host SATA receive differential pair| 42| Reserved|
43| SATA RX-| 44| Reserved|
45| GND| | 46| Reserved|
47| SATA TX-| Host SATA transmit differential pair| 48| Reserved|
49| SATA TX+| 50| Reserved|
51| GND| | 52| Reserved|
53| Reserved| | 54| Reserved|
55| Reserved| | 56| MFG_1| Reserved for manufacturer use
57| GND| | 58| MFG_2| Reserved for manufacture use
59| M Key| 60| M Key
61| 62
63| 64
65| 66
67| DNU| | 68| SUSCLK| 32kHz clock input; not used
69| CONFIG_1| Connected to GND for SATA SSD| 70| 3.3V|
71| GND| | 72| 3.3V|
73| GND| | 74| 3.3V|
75| CONFIG_2| Connected to GND for SATA SSD| | |
Electrical Specifications
The following table defines all D.C. Characteristics for the M.2 SSD products.
Unless otherwise stated, conditions are:
Vcc = 3.3V ± 5%
Ta = -40°C to 85°C
5.1.1. Absolute Maximum Ratings
Parameter | Symbol | MIN | MAX | Unit s |
---|---|---|---|---|
Storage Temperature | Ts | -55 | +100 | oC |
Operating Temperature | TA | -40 | +85 | oC |
Vcc with respect to GND | Vcc | -0.3 | 3.6 | V |
5.1.2. DC Characteristics
Parameter | Symbol | MIN | MAX | Unit s |
---|---|---|---|---|
Input Voltage | Vin | -0.5 | Vcc + 0.5 | V |
Output Voltage | Vout | -0.3 | Vcc + 0.3 | V |
Input Leakage Current | ILI | -10 | 10 | uA |
Output Leakage Current | ILO | -10 | 10 | uA |
Input/Output Capacitance | CI/Co | 10 | pF |
Operating Current
Idle
Active| ICC| | 110
670| mA
5.1.3. AC Characteristics
Cactus Technologies® M.2 SSD products conforms to all AC timing requirements as specified in the Serial ATA v3.1 specifications. Please refer to that document for details of AC timing for all operation modes of the device.
ATA Drive Register Set Definition and Protocol
The communication to or from the SSD is done using FIS. Legacy ATA protocol is
supported by using the legacy mode defined in the SATA specifications. In this
mode, the FIS has defined fields which provide all the necessary ATA task file
registers for control and status information. The Serial ATA interface does
not support Primary/Secondary or Master/Slave configurations. Each SATA
channel supports only one SATA device, with the register selection as defined
by the ATA standard.
6.1. ATA Task File Definitions
The following sections describes the usage of the ATA task file registers.
Note that the Alternate Status Register of legacy ATA is not defined for SATA
drives.
6.1.1. Data Register
The Data Register is a 16-bit register, and it is used to transfer data blocks
between the SSD data buffer and the Host.
6.1.2. Error Register
This register contains additional information about the source of an error
when an error is indicated in bit 0 of the Status register. The bits are
defined as follows:
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|
BBK | UNC | 0 | IDNF | 0 | ABRT | 0 | AMNF |
Bit 7 (BBK) This bit is set when a Bad Block is detected.
Bit 6 (UNC) This bit is set when an Uncorrectable Error is
encountered.
Bit 5 This bit is 0.
Bit 4 (IDNF) The requested sector ID is in error or cannot be found.
Bit 3 This bit is 0.
Bit 2 (Abort) This bit is set if the command has been aborted because
of a status condition: (Not Ready, Write Fault, etc.) or when an invalid
command has been issued.
Bit 1 This bit is 0.
Bit 0 (AMNF) This bit is set in case of a general error.
6.1.3. Feature Register
This register provides information regarding features of the SSD that the host
can utilize.
6.1.4. Sector Count Register
This register contains the number of sectors of data requested to be
transferred on a read or write operation between the host and the SSD. If the
value in this register is zero, a count of 256 sectors is specified. If the
command was successful, this register is zero at command completion. If not
successfully completed, the register contains the number of sectors that need
to be transferred in order to complete the request.
6.1.5. Sector Number (LBA 7-0) Register
This register contains the starting sector number or bits 7-0 of the Logical
Block Address (LBA) for any SSD data access for the subsequent command.
6.1.6. Cylinder Low (LBA 15-8) Register
This register contains the low order 8 bits of the starting cylinder address
or bits 15-8 of the Logical Block Address.
6.1.7. Cylinder High (LBA 23-16) Register
This register contains the high order bits of the starting cylinder address or
bits 23-16 of the Logical Block Address.
6.1.8. Drive/Head (LBA 27-24) Register
The Drive/Head register is used to select the drive and head. It is also used
to select LBA addressing instead of cylinder/head/sector addressing. The bits
are defined as follows:
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|
1 | LBA | 1 | DRV | HS3 | HS2 | HS1 | HS0 |
Bit 7 This bit is set to 1.
Bit 6 LBA is a flag to select either Cylinder/Head/Sector (CHS) or
Logical Block Address Mode (LBA).
When LBA=0, Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block
Address is selected. In Logical Block Mode, the Logical Block Address is
interpreted as follows:
LBA07-LBA00: Sector Number Register D7-D0.
LBA15-LBA08: Cylinder Low Register D7-D0.
LBA23-LBA16: Cylinder High Register D7-D0.
LBA27-LBA24: Drive/Head Register bits HS3-HS0.
Bit 5 This bit is set to 1.
Bit 4 (DRV) DRV is the drive number. This should always be set to 0.
Bit 3 (HS3) When operating in the Cylinder, Head, Sector mode, this
is bit 3 of the head number. It is Bit 27 in the Logical Block Address mode.
Bit 2 (HS2) When operating in the Cylinder, Head, Sector mode, this is
bit 2 of the head number. It is Bit 26 in the Logical Block Address mode.
Bit 1 (HS1) When operating in the Cylinder, Head, Sector mode, this is
bit 1 of the head number. It is Bit 25 in the Logical Block Address mode.
Bit 0 (HS0) When operating in the Cylinder, Head, Sector mode, this is
bit 0 of the head number. It is Bit 24 in the Logical Block Address mode.
6.1.9. Status Registers
These registers return the status when read by the host. Reading the Status
register does clear a pending interrupt while reading the Auxiliary Status
register does not. The meaning of the status bits are described as follows:
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|
BUSY | RDY | DWF | DSC | DRQ | CORR | 0 | ERR |
Bit 7 (BUSY) The busy bit is set when the device has access to the
command buffer and registers and the host is locked out from accessing the
command register and buffer. No other bits in this register are valid when
this bit is set to a 1.
Bit 6 (RDY) RDY indicates whether the device is capable of performing
operations requested by the host. This bit is cleared at power up and remains
cleared until the device is ready to accept a command.
Bit 5 (DWF) This bit, if set, indicates a write fault has occurred.
Bit 4 (DSC) This bit is set when the device is ready.
Bit 3 (DRQ) The Data Request is set when the device requires that
information be transferred either to or from the host through the Data
register.
Bit 2 (CORR) This bit is set when a Correctable data error has been
encountered and the data has been corrected. This condition does not terminate
a multi-sector read operation.
Bit 1 (IDX) This bit is always set to 0.
Bit 0 (ERR) This bit is set when the previous command has ended in some
type of error. The bits in the Error register contain additional information
describing the error.
6.1.10. Device Control Register
This register is used to control the drive interrupt request and to issue an
ATA soft reset to the drive. The bits are defined as follows:
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|
HOB | X | X | X | 1 | SW Rst | -IEn | 0 |
Bit 7 This bit is used in 48-bit addressing mode. When cleared, the host
can read the most recently written values of the Sector Count,Drive/Head and
LBA registers. When set, the host will read the previous written values of
these registers. A write to any Command block register will clear this bit.
Bit 6 This bit is an X (Do not care).
Bit 5 This bit is an X (Do not care).
Bit 4 This bit is an X (Do not care).
Bit 3 This bit is ignored by the drive.
Bit 2 (SW Rst) This bit is set to 1 in order to force the drive to
perform an AT Disk controller Soft Reset operation. The drive remains in Reset
until this bit is reset to ‘0’.
Bit 1 (-IEn) The Interrupt Enable bit enables interrupts when the bit is
0. When the bit is 1, interrupts from the drive are disabled. This bit is set
to 0 at power on and Reset.
Bit 0 This bit is ignored by the drive.
6.1.11. Drive Address Register
This register is provided for compatibility with the AT disk drive interface.
It is recommended that this register not be mapped into the host’s I/O space
because of potential conflicts on Bit 7. The bits are defined as follows:
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|
X | -WTG | -HS3 | -HS2 | -HS1 | -HS0 | -nDS1 | -nDS0 |
Bit 7 This bit is unknown.
Implementation Note:
Conflicts may occur on the host data bus when this bit is provided by a Floppy
Disk Controller operating at the same addresses as the SSD. Following are some
possible solutions to this problem:
-
Locate the SSD at a non-conflicting address (i.e., Secondary address (377) when a Floppy Disk Controller is located at the Primary addresses).
-
Do not install a Floppy and a SSD in the system at the same time.
-
Implement a socket adapter that can be programmed to (conditionally) tri-state D7 of I/0 address 3F7/377 when a SSD product is installed and conversely to tri-state D6-D0 of
I/O address 3F7/377 when a floppy controller is installed. -
Do not use the SSD’s Drive Address register. This may be accomplished by either a) If possible, program the host adapter to enable only I/O addresses 1F0-1F7, 3F6 (or 170177, 176) to the SSD or b) if provided use an additional Primary/Secondary configuration in the SSD that does not respond to accesses to I/O locations 3F7 and 377. With either of these implementations, the host software must not attempt to use information in the Drive Address Register.
Bit 6 (-WTG) This bit is 0 when a write operation is in progress,
otherwise, it is 1.
Bit 5 (-HS3) This bit is the negation of bit 3 in the Drive/Head
register.
Bit 4 (-HS2) This bit is the negation of bit 2 in the Drive/Head
register.
Bit 3 (-HS1) This bit is the negation of bit 1 in the Drive/Head
register.
Bit 2 (-HS0) This bit is the negation of bit 0 in the Drive/Head
register.
Bit 1 (-nDS1) This bit is 0 when drive 1 is active and selected.
Bit 0 (-nDS0) This bit is 0 when the drive 0 is active and selected.
ATA Command Description
This section defines the ATA command set supported by Cactus Technologies® M.2
SSDs.
7.1. ATA Command Set
Table 5-6 summarizes the supported ATA command set .
Table 5-6. ATA Command Set
COMMAND | Code |
---|---|
Check Power Mode | E5h, 98h |
Data Set Management | 06h |
Execute Drive Diagnostic | 90h |
Flush Cache | E7h |
Flush Cache Ext | EAh |
Identify Drive | ECh |
Idle | E3h, 97h |
Idle Immediate | E1h, 95h |
Initialize Drive Parameters | 91h |
NOP | 00h |
Read Buffer | E4h |
Read DMA | C8h |
Read DMA Ext | 25h |
Read FPDMA Queued | 60h |
Read Multiple | C4h |
Read Multiple Ext | 29h |
Read Sector(s) | 20h, 21h |
Read Sector(s) Ext | 24h |
COMMAND | Code |
--- | --- |
Read Verify Sector(s) | 40h, 41h |
Read Verify Sector(s) Ext | 42h |
Security Disable Password | F6h |
Security Erase Prepare | F3h |
Security Erase Unit | F4h |
Security Freeze Lock | F5h |
Security Set Password | F1h |
Security Unlock | F2h |
Seek | 70h |
Set Features | EFh |
Set Multiple Mode | C6h |
Set Sleep Mode | E6h, 99h |
SMART | B0h |
Stand By | E2h, 96h |
Stand By Immediate | E0h, 94h |
Write Buffer | E8h |
Write DMA | CAh |
Write DMA Ext | 35h |
Write FPDMA Queued | 61h |
Write Multiple | C5h |
Write Multiple Ext | 39h |
Write Sector(s) | 30h, 31h |
Write Sector(s) Ext | 34h |
S.M.A.R.T. Feature Set
Cactus Technologies® -245 Series M.2 SSD supports S.M.A.R.T. attribute reporting. This following subcommands are supported when programmed into the Feature Register:
Value | Command | Value | Command |
---|---|---|---|
D0h | Read Data | D5h | Reserved |
D1h | Read Attribute Threshold | D6h | Reserved |
D2h | Enable/Disable Autosave | D8h | Enable SMART operationes |
D3h | Save Attribute Values | D9h | Disable SMART operations |
D4h | Execute OFF-LINE Immediate | DAh | Return Status |
8.1. S.M.A.R.T Data Structure
The Read Data commands returns 512 bytes of data in the following structure:
Byte | Description |
---|---|
0-1 | Revision code |
2-361 | Vendor specific |
362 | Off-line data collection status |
363 | Self-test execution status byte |
364-365 | Total time in seconds to complete off-line data collection |
activitiies
366| Vendor specific
367| Off-line data collection capabilities
368-369| SMART capabilities
370| Error logging capabilities: bit[7:1] – reserved; bit[0]: 1=device error
logging supported
371| Vendor specific
372| Short self-test routine recommended polling time (in minutes)
373| Extended self-test routine recommended polling time (in minutes)
374| Conveyance self-test routine recommended polling time (in minutes)
375-385| Reserved
386-395| Firmware Version/Date Code
396-397| Reserved
398-399| Reserved
400-405| ‘SM2246’
406-510| Vendor specific
511| Data structure checksum
8.2. S.M.A.R.T Attributes
The following table lists the attributes returned in bytes 2-361 of the
512-byte SMART data. Byte 0 is Attribute ID, bytes 1-2 are status flags, bytes
3-4 are reserved bytes; the table below shows the definition for bytes 5-11:
Attribute ID | Attribute values | Attribute Name |
---|---|---|
Byte 5 | Byte 6 | Byte 7 |
01h | MSB | 00 |
05h | LSB | MSB |
09h | LSB | |
0Ch | LSB | |
A0h | LSB | |
Attribute ID | Attribute values | Attribute Name |
--- | --- | --- |
Byte 5 | Byte 6 | Byte 7 |
A1h | LSB | MSB |
A3h | LSB | MSB |
A4h | LSB | |
A5h | LSB | |
A6h | LSB | |
A7h | LSB | |
A8h | LSB | |
A9h | ||
AFh | LSB | |
B0h | LSB | MSB |
B1h | LSB | |
B2h | LSB | MSB |
B5h | LSB | |
B6h | LSB | MSB |
BBh | LSB | |
C0h | LSB | |
C2h | MSB | 00 |
C3h | ||
C4h | LSB | |
C6h | LSB | |
C7h | LSB | MSB |
F1h | LSB | |
F2h | LSB |
*1: Note that some 3rd party SMART utilities may report this attribute as ‘Percent Remaining Life’ or ‘SATA PHY Error Count’; this is not valid for -245S series pSLC products, please ignore it.
Appendix A. Ordering Information
Model KDXFI-245SY
Where: X is drive capacities:
4G —————- 4GB
8G —————- 8GB
16G ————– 16GB
32G ————– 32GB
64G ————– 64GB
128G ———— 128GB
Where: I is temperature grade:
blank ———— standard
I ——————- extended
Where: Y is form factor:
M5 ————— 2260
M6 ————— 2242
M7 ————— 2280 (32/64/128G only)
Example:
- 8GB M.2 2260 SSD ———————————————————– KD8GF-245SM5
- 8GB M.2 SSD 2260 extended temp. ———————————— KD8GFI-245SM5
- 8GB M.2 2242 SSD ———————————————————– KD8GF-245SM6
- 64GB M.2 2280 SSD ——————————————————— KD64GF-245SM7
Appendix B.Technical Support Services
B.1.Direct Cactus Technologies® Technical Support
Email: tech@cactus-tech.com
Appendix C.Cactus Technologies® Worldwide Sales Offices
Email: sales@cactus-tech.com
Email: americas@cactus-tech.com
Appendix D.Limited Warranty
I. WARRANTY STATEMENT
Cactus Technologies® warrants its Industrial pSLC products only to be free of
any defects in materials or workmanship that would prevent them from
functioning properly for two years from the date of purchase or when rated TBW
is exceeded, whichever occurs first. This express warranty is extended by
Cactus Technologies® Limited to customers of our products.
II. GENERAL PROVISIONS
This warranty sets forth the full extent of Cactus Technologies®
responsibilities regarding the Cactus Technologies®, at its sole option, will
repair, replace or refund the purchase price of the defective product. Cactus
Technologies® Commercial Grade Flash Storage Products. Cactus Technologies®
guarantees our products meet all specifications detailed in our product
manuals. Although Cactus Technologies® products are designed to withstand
harsh environments and have the highest specifications in the industry, they
are not warranted to never have failure and Cactus Technologies® does not
warranty against incidental or consequential damages. Accordingly, in any use
of products in life support systems or other applications where failure could
cause injury or loss of life, the products should only be incorporated in
systems designed with appropriate redundancy, fault tolerant or backup
features.
III. WHAT THIS WARRANTY COVERS
For products found to be defective, Cactus Technologies® will have the option
of repairing, replacing or refunding the purchase price the defective product,
if the following conditions are met:
A. The defective product is returned to Cactus Technologies® for failure
analysis as soon as possible after the failure occurs.
B. An incident card filled out by the user, explaining the conditions of usage
and the nature of the failure, accompanies each returned defective product.
C. No evidence is found of abuse or operation of products not in accordance
with the published specifications, or of exceeding maximum ratings or
operating conditions.
All failing products returned to Cactus Technologies® under the provisions of
this limited warranty shall be tested to the product’s functional and
performance specifications. Upon confirmation of failure, each product will be
analyzed, by whatever means necessary, to determine the root cause of failure.
If the root cause of failure is found to be not covered by the above
provisions, then the product will be returned to the customer with a report
indicating why the failure was not covered under the warranty.
This warranty does not cover defects, malfunctions, performance failures or
damages to the unit resulting from use in other than its normal and customary
manner, misuse, accident or neglect; or improper alterations or repairs.
Cactus Technologies® Limited may repair or replace, at its discretion, any
product returned by its customers, even if such product is not covered under
warranty, but is under no obligation to do so.
IV. RECEIVING WARRANTY SERVICE
According to Cactus Technologies® warranty procedure, defective product should
be returned only with prior authorization from Cactus Technologies® Limited.
Please contact Cactus Technologies® Customer Service department (tech@cactus-
tech.com) with the following information:
product model number and description, nature of defect, conditions of use,
proof of purchase and purchase date. If approved, Cactus Technologies® will
issue a Return Material Authorization or Product Repair Authorization number
and instructions to ship the product back to us for service.
Cactus Technologies Limited
August 14, 2023
www.cactus-tech.com
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