Microchip Technology MIV_RV32 v3.0 IP Core Tool Dynamic Page User Manual

: June 12, 2024
: Microchip Technology

Table of Contents

Microchip Technology MIV_RV32 v3.0 IP Core Tool Dynamic Page
MIV_RV32 v3.0 Release Notes
Features
Documentation
References
Read User Manual Online (PDF format)
Download This Manual (PDF format)

Microchip Technology MIV_RV32 v3.0 IP Core Tool Dynamic Page

Product Information
The product is MIV_RV32 v3.0, released in October 2020. It is a proprietary and confidential product developed by Microsemi. The release notes provide information about the features, enhancements, system requirements, supported families, implementations, known issues, and workarounds of the IP.

Features

MIV_RV32 has the following features:

Delivery Types
No license is required to use MIV_RV32. The complete RTL source code is provided for the core.

Supported Families
The supported families are not mentioned in the user manual text.

Installation Instructions
To install the MIV_RV32 CPZ file, it must be done through the Libero software using either the Catalog update function or manually adding the CPZ file using the Add Core catalog feature. Once installed, the core can be configured, generated, and instantiated within a design for inclusion in the Libero project. Refer to the Libero SoC Online Help for further instructions on core installation, licensing, and general use.

Documentation
For updates and additional information about the software, devices, and hardware, visit the Intellectual Property pages on the Microsemi SoC Products Group website: http://www.microsemi.com/products/fpga-soc/design-resources /ip-cores.
More information can also be obtained from MI-V embedded ecosystem.

Supported Test Environments

No testbench is provided with MIV_RV32. The MIV_RV32 RTL can be used to simulate the processor executing a program using a standard Libero generated testbench.

Discontinued Features and Devices
None.

Known Limitations and Workarounds
The following limitations and workarounds apply to the MIV_RV32 v3.0 release:

The TCM is limited to a maximum size of 256 Kb.
To initialize the TCM in PolarFire using the system controller, a local parameter l_cfg_hard_tcm0_en is required.

Please note that this information is based on the provided text extract from the user manual. For more detailed and complete information, refer to the full user manual or contact Microsemi directly.

Revision History
The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Revision 2.0
Revision 2.0 of this document was published in October 2020. The following is a summary of the changes. Changed the core name to MIV_RV32 from MIV_RV32IMC. This configuration-neutral name allows for future expansion of support for additional RISC-V ISA extensions.

Revision 1.0
Revision 1.0 is the first publication of this document published in March 2020.

MIV_RV32 v3.0 Release Notes

Overview
These release notes are issued with the production release of MIV_RV32 v3.0. This document provides details about the features, enhancements, system requirements, supported families, implementations, and known issues and workarounds of the IP.

Features

MIV_RV32 has the following features

Designed for low-power FPGA soft-core implementations
Supports the RISC-V standard RV32I ISA with optional M and C extensions
Availability of Tightly Coupled Memory, with size defined by address range
TCM APB Slave (TAS) to TCM
Boot ROM feature to load an image and run from memory
External, Timer, and Soft Interrupts
Up to six optional external interrupts
Vectored and non-vectored interrupt support
optional on-chip debug unit with a JTAG interface
AHBL, APB3, and AXI3/AXI4 optional external bus interfaces

Delivery Types
No license is required to use MIV_RV32. Complete RTL source code is provided for the core.

Supported Families

PolarFire SoC®
PolarFire RT®
PolarFire®
RTG4TM
IGLOO®2
SmartFusion®2

Installation Instructions
The MIV_RV32 CPZ file must be installed into Libero software. This is done automatically through the Catalog update function in Libero, or the CPZ file can be manually added using the Add Core catalog feature. Once the CPZ file is installed in Libero, the core can be configured, generated, and instantiated within a design for inclusion in the Libero project. See the Libero SoC Online Help for further instructions on core installation, licensing, and general use.

Documentation

This release contains a copy of the MIV_RV32 Handbook and RISC-V Specification documents. The handbook describes the core functionality and gives step-by- step instructions on how to simulate, synthesize, and place and route this core, and also implementation suggestions. See the Libero SoC Online Help for instructions on obtaining IP documentation. A design guide is also included which walks through an example Libero design for PolarFire®. For updates and additional information about the software, devices, and hardware, visit the Intellectual Property pages on the Microsemi SoC Products Group website: http://www.microsemi.com/products/fpga-soc/design-resources/ip-cores
More information can also be obtained from MI-V embedded ecosystem.

Supported Test Environments
No testbench is provided with MIV_RV32. The MIV_RV32 RTL can be used to simulate the processor executing a program using a standard Libero-generated test bench.

Discontinued Features and Devices
None.

Known Limitations and Workarounds
The following are the limitations and workaround applicable to the MIV_RV32 v3.0 release.

The TCM is limited to a maximum size of 256 Kb.
To initialize the TCM in PolarFire using the system controller, a local parameter l_cfg_hard_tcm0_en, in the miv_rv32_opsrv_cfg_pkg.v file should be changed to 1’b1 prior to synthesis. See section 2.7 in MIV_RV32 v3.0 Handbook.
Debugging over GPIO using FlashPro 5 should be limited to 10 MHz maximum.
Please note the JTAG_TRSTN input is now active low. In previous versions, this input was actively high.

Microsemi’s product warranty is set forth in Microsemi’s Sales Order Terms and Conditions. Information contained in this publication is provided for the sole purpose of designing with and using Microsemi products. Information regarding device applications and the like is provided only for your convenience and may be superseded by updates. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is your responsibility to ensure that your application meets your specifications.

THIS INFORMATION IS PROVIDED “AS IS.” MICROSEMI MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROSEMI BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE WHATSOEVER RELATED TO THIS INFORMATION OR ITS USE, HOWEVER, CAUSED, EVEN IF MICROSEMI HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE? TO THE FULLEST EXTENT ALLOWED BY LAW, MICROSEMI’S TOTAL LIABILITY ON ALL CLAIMS IN RELATED TO THIS INFORMATION OR ITS USE WILL NOT EXCEED THE NUMBER OF FEES, IF ANY, YOU PAID DIRECTLY TO MICROSEMI FOR THIS INFORMATION.

Use of Microsemi devices
in life support, mission-critical equipment or applications, and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend and indemnify Microsemi from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microsemi intellectual property rights unless otherwise stated.

Microsemi Corporation, a subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), and its corporate affiliates are leading providers of smart, connected, and secure embedded control solutions. Their easy-to-use development tools and comprehensive product portfolio enable customers to create optimal designs which reduce risk while lowering total system cost and time to market. These solutions serve more than 120,000 customers across the industrial, automotive, consumer, aerospace and defense, communications, and computing markets. Headquartered in Chandler, Arizona, the company offers outstanding technical support along with dependable delivery and quality. Learn more at www.microsemi.com.

Microsemi
2355 W. Chandler Blvd.
Chandler, AZ 85224 USA
Within the USA: +1 480-792-7200
Fax: +1 480-792-7277
www.microsemi.com © 2020 Microsemi and its corporate affiliates. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation and its corporate affiliates. All other trademarks and service marks are the property of their respective owners.