Microsemi M2GL090T/TS IGLOO2 M2GL090T/TS and SmartFusion2 Device User Guide

Microsemi M2GL090T/TS IGLOO2 M2GL090T/TS and SmartFusion2 Device

Product Information: IGLOO2 M2GL090T/TS and SmartFusion2 M2S090T/TS

Device

Introduction

The IGLOO2 M2GL090T/TS and SmartFusion2 M2S090T/TS devices are equipped with a High Speed Serial Interface block that allows for multiple high-speed serial protocols, including PCIe end-point and XAUI. The block enables the FPGA fabric to connect with the External Physical Coding Sublayer (EPCS) interface and implement any user-defined protocol in the fabric. The devices contain one High Speed Serial Interface block that has two SERDES IP cores.

Functionality

The High Speed Serial Interface block in the IGLOO2 M2GL090T/TS and SmartFusion2 M2S090T/TS devices provides the following functionalities:

• Multiple high-speed serial protocols, including PCIe end-point and XAUI.
• Enables the FPGA fabric to connect with the External Physical Coding Sublayer (EPCS) interface.
• Implements any user-defined protocol in the fabric.
• Two SERDES IP cores.

Identification

The devices contain one High Speed Serial Interface block. Under the Identification Heading, SERDESIF_0 is selected by default to identify the SERDES block that is being configured.

Protocol Configuration

For High Speed Serial Interface 2 core, you must configure the Type and Number of Lanes for each of the two protocols. For High Speed Serial Interface 3 core, you cannot configure the protocol type and lane configuration. They are fixed as follows:

• Protocol 1 and Protocol 2
• If Protocol Type is XAUI, all four lanes are selected by default.

Protocol 1 and 2: Type, Number of Lanes, Speed

Table 1-1 shows the protocol combinations that are feasible within a single High Speed Serial Interface block.

Product Usage Instructions

To use the High Speed Serial Interface block in the IGLOO2 M2GL090T/TS and SmartFusion2 M2S090T/TS devices:

1. Identify the SERDES block that needs to be configured – this is typically SERDESIF_0.
2. Configure the Type and Number of Lanes for Protocol 1 and Protocol 2 by selecting the appropriate options from the drop-down lists.
3. Configure the speed according to the available choices.
4. If using Protocol PCI or PCIe Reverse, click on the Configure PCIe button to configure additional options for SERDES in PCIe mode.
5. Note that Protocol 2 Types are context-sensitive and depend on the options selected in Protocol 1. Protocol 2 Type selection is disabled when XAUI is selected in Protocol 1. It is activated only when PCIe, PCIe Reverse or EPCS is selected for Protocol 1 and less than four lanes are used.

Product Introduction

The High Speed Serial Interface block in the IGLOO2 M2GL090T/TS and SmartFusion2 M2S090T/TS devices (Figure 3) provides multiple high speed serial protocols, such as PCIe end-point and XAUI. In addition, it enables the FPGA fabric to connect with the External Physical Coding Sublayer (EPCS) interface and implement any user defined protocol in the fabric.

Two SERDES IP cores are available:

• High Speed Serial Interface 2 – supports 2 protocols: 1 and 2
• High Speed Serial Interface 3 – supports 3 protocols: 1, 2 and 3

As you make selections in the core configurator, it automatically narrows down the subsequent choices and defaults. Only the relevant ports appear in the generated macro.

This document describes how to configure a High Speed Serial Interface instance and define how the signals are connected. For more details about the High Speed Serial Interface, refer to the SmartFusion2 or IGLOO2 High Speed Serial Interfaces User’s Guide.

To access the High Speed Serial Interface Configurator:

1. Instantiate the High Speed Serial Interface 2 core or the High Speed Serial Interface 3 core from the Catalog into the SmartDesign Canvas, as shown in Figure 1 and Figure 2.
   Figure 1 • SERDES IF2 Block Instantiation on the SmartDesign Canvas
   Figure 2 • SERDES IF3 Block Instantiation on the Smart Design Canvas

2. Double-click the SERDES block on the Canvas to open the Configurator (Figure 3 and Figure 4).
   

Functionality

Identification
IGLOO2 M2GL090T/TS and SmartFusion2 M2S090T/TS devices contain one High Speed Serial Interface block. Under the Identification Heading, SERDESIF_0 is selected by default to identify the SERDES block you are configuring.

Protocol Configuration
For High Speed Serial Interface 2 core, you must configure the Type and Number of Lanes for each of the two protocols.
For High Speed Serial Interface 3 core, you cannot configure the protocol type and lane configuration. They are fixed as follows;

• Protocol 1: PCIe One Lane (Lane 0), at either Gen1 or Gen2 speed
• Protocol 2: PCIe One Lane (Lane 1), at either Gen1 or Gen2 speed
• Protocol 3: EPCS One Lane (Lane 2 or Lane 3) or Two Lanes (Lane 2 and Lane 3) at Custom speed.

High Speed Serial Interface 3 core gives you three protocols but you have less flexibility to configure. High Speed Serial Interface 2 core gives you two protocols only but allows more flexibility for configuration.

Protocol 1 and Protocol 2
Select your Protocol type from the drop-down menu:

• PCIe
• PCIe (Reverse)
• XAUI
• EPCS

When you select the Protocol PCI or PCIe Reverse, you must click the Configure PCIe button to configure additional options for SERDES in PCIe mode. See “Configure PCIe” on page 7 for details.

Note: You must Configure Protocol 1 before configuring Protocol 2.

Protocol 2 Types are context sensitive; they depend on the options you have selected in Protocol 1.

Protocol 2 Type selection is disabled when you select XAUI in Protocol 1. It is activated only when PCIe, PCIe Reverse or EPCS is selected for Protocol 1 and you use less than four lanes. Refer to Table 1-1 for the Protocol 1 and Protocol 2 configuration combinations.

Number of Lanes
Select the number of lanes you wish to configure for Protocol 1 from the drop- down menu:

• X1 – Configure for 1 lane
• X2 – Configure for 2 lanes
• X4 – Configure for all 4 lanes

Note: Items in the drop-down list are context sensitive and depend on the Protocol Type.
If Protocol Type is XAUI, all four lanes are selected by default.

Protocol 1 and 2: Type, Number of Lanes, Speed
Table 1-1 shows the protocol combinations that are feasible within a single High Speed Serial Interface block.

Table 1-1 • Available Protocols

Protocol Type| Protocol #| Lane Width| Lane Assignment| Description| Speed Choices
---|---|---|---|---|---
PCIe| Protocol 1| x1| Lane 0| | Gen1 (2.5 Gbps), Gen2 (5.0 Gbps)
x2| Lane 0, Lane 1
x4| Lane 0, Lane 1, Lane 2, Lane 3
Protocol 2| x1| Lane 2| Available only when PCIe or PCIe Reverse is selected for Protocol 1
x2| Lane 2, Lane 3
PCIe Reverse| Protocol 1| x1| Lane 1 or Lane 3| If Protocol 2 is used, it is Lane 1; otherwise, it is Lane 3| Gen1 (2.5 Gbps), Gen2 (5.0 Gbps)
x2| Lane 0, Lane 1 or Lane 2, Lane 3| If Protocol 2 is used, it is Lanes 0 and 1; otherwise, it is Lanes 2 and 3
x4| Lane 0, Lane 1, Lane 2, Lane 3|
Protocol 2| x1| Lane 3| Available only when PCIe or PCIe Reverse is selected for Protocol 1
x2| Lane 2, Lane 3
XAUI| Protocol 1| x4| Lane 0, Lane 1, Lane 2, Lane 3| | 3.125 Gpbs
EPCS| Protocol 1| x1| Users can select Lane 0, 1, 2 or 3| | Custom Speed
X2| Lane 0, Lane 1
x4| Lane 0, Lane 1, Lane 2, Lane 3
Protocol 2| x1| Users can select Lane 2 or 3|
x2| Lane 2, Lane 3

The PCIe GEN 2 (5.0 Gbps) speed is not available in STD speed-grade devices. Refer to your device datasheet (SmartFusion2 Datasheet; IGLOO2 Datasheet) for more information.

Configure PCIe
The Configure PCIe button appears only when you select the PCIe or PCI Reverse Protocol.

Configuration
The Configuration tab sets your Identification Registers, Fabric Interface, Base Address Registers and Options (Figure 1-1).

Identification Registers
There are six identification registers for PCIe that you can assign 16-bit hexadecimal signatures.

• Vendor ID – 0x11AA is the Vendor ID assigned to Microsemi by PCI-SIG. Contact Microsemi if you would like to allocate Subsystems under the Microsemi vendor ID.
• Subsystem vendor ID – Card manufacturer’s ID.
• Device ID – Manufacturer’s assigned part number assigned by the vendor.
• Revision ID – Revision number, if available.
• Subsystem Device ID – Assigned by the subsystem vendor.
• Class Code – PCIe device’s generic function.

Fabric Interface
Use this field to configure the Bus Standard (AXI or AHBLite) and the Interface (Master Only, Slave Only, or Master and Slave) for the PCIe protocol. You can select the Bus Standard and the Interface Mode for both Protocol 1 and Protocol 2, separately and independently. Dual-PCIe Mode operation is supported.
In PCIe mode, the SERDES block can act as an AXI or AHBLite Master.

You must instantiate a COREAXI or CoreAHBLite Bus into the SmartDesign Canvas and then connect the Master and/or Slave Bus Interface (BIF) of the SERDES to the Master and/or Slave BIF of the COREAXI bus or COREAHBLite bus.

Base Address Registers
The individual fields of the six Base Address Registers (Bar 0 through Bar 5) can be configured as follows:

• Width – The width on even registers can be 32 bits or 64 bits. If an even register is set to 64 bits wide, the subsequent (odd) register serves as the upper half of 64 bits. The width of odd registers is restricted to 32 bits.
• Size – Ranges from 4 KB to 2 GB when the Width is 32 bit. Some devices support only up to 1 GB. When the Width is 64 bit, the Size can range from 2 KB to 16 EB. Refer to your device datasheet (SmartFusion2 Datasheet; IGLOO2 Datasheet) for more information.
• Prefetchable – Enabled only on even registers with 64-bit width.

Options
Options enables you to configure the following:

• PHY Reference Clock Slot – Sets your reference clock to Slot or Independent.
• Expose Wake Signals – Click the checkbox to add PCIE_WAKE_N, PCIE_WAKE_REQ and PCIE_PERST_N ports.
• PCIe Specification Version – Sets the Specification Version to 1.0, 1.1 or 2.0.
• Interrupt – Sets the Interrupt to:
  • MSI 1
  • MSI 2
  • MSI 4
  • MSI 8
  • MSI 16
  • MSI 32
  • INTx

Your Interrupt selection sets bit 16 of the PCIE_MSI_CTRL_STATUS register and bits [19:17] of the PCIE_MSICTRL STATUS register as shown in Table 1-2 below.

Table 1-2 • MSI and Register Settings

Interrupt Selected| Setting for Bit 16 of PCIE_MSI_CTRL_STATUS Register| Setting for Bits [19:17] of PCIE_MSI_CTRL_STATUS Register
---|---|---
MSI 1| 1| 000
MSI 2| 1| 001
MSI 4| 1| 010
MSI 8| 1| 011
MSI 16| 1| 100
MSI 32| 1| 101
INTx| 0 (Disable MSI)| 000

Power Management Settings
Use the Power Management Settings to configure the ASPM (Active State Power Management) settings. The Configurator sets the correct register values for your SERDES block based on the selections you have made.

Figure 1-2 • Power Management Settings

ASPM L0s Capability
This is mandatory. Settings available are:

• L0s Acceptable Latency – Opens the pull-down list to choose one of the following latency values:
  • Maximum of 64ns
  • Maximum of 128ns
  • Maximum of 256ns
  • Maximum of 512ns
  • Maximum of 1us
  • Maximum of 2us
  • Maximum of 4us
  • No Limit
• FTS in Separate Clock Mode – Enter the number of FTS (Fast Training Sequences) required in separate clock mode. Valid values are from 0 through 255.
• FTS in Common Clock Mode – Enter the number of FTS (Fast Training Sequences) required in common clock mode. Valid values are from 0 through 255.

ASPM L1 Capability
By default, the ASPM L1 Capability is enabled. Configure the settings for ASPM L1 as follows:

• L1 Acceptable Latency – Click the pull-down list to choose one of the of following for latency values:
  • Maximum of 1 us
  • Maximum of 2 us
  • Maximum of 4 us
  • Maximum of 8 us
  • Maximum of 16 us
  • Maximum of 32 us
  • Maximum of 64 us
  • No Limit
• L1 Exit Latency Separate Clock/Common Clock Mode- Click the pull-down menu to choose one of the following for the Exit Latency value of Separate/Common Clock Mode:
  • Less than 1 us
  • 1 us to less than 2 us
  • 2 us to less than 4 us
  • 4 us to less than 8 us
  • 8 us to less than 16 us
  • 16 us to less than 32 us
  • 32 us to 64 us
  • More than 64 us

Note: The Exit Latency value you choose for the Common Clock Mode must be smaller than the value for Separate Clock Mode.

Master Interface
PCIe/PCIe Reverse Protocol 1 or Protocol 2 enables you to use the Master Interface tab to configure up to four PCI windows (Window 0 through Window 3) with the following parameters (as shown in Figure 1-3):

• Size
• PCIe BAR (Base Address Register)
• Local Address
• PCIe Address

Size
For each of the windows 0 through 3, select one of the available window sizes: 4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 1GB and 2GB.
The default selection is 4KB. The size selected is mapped to bits [31:12] of WindowsX_1, where X can be 0, 1, 2, or 3.

PCIe BAR
Select one of the following BAR (Base Address Register):

• BAR0
• BAR1
• BAR2
• BAR3
• BAR4
• BAR5
• BAR0/1
• BAR2/3
• BAR4/5

Bar Size is mapped to bits [5:0] of WindowsX_2, where X can be 0, 1, 2 or 3, as shown in Table 1-3.

Table 1-3 • BAR Size and Corresponding Bit Settings

Local Address
Local Address is 20-bits wide and is mapped to bits [31:12] of Base address AXI Master WindowsX_0. The LSB bits [11:0] of AXI Master WindowsX_0 are reserved and the configurator will account for these bits. Do not include these reserved bits when you specify the local address.

PCIe Address
PCIe Address is mapped to bits [31:12] (LSB of Base address AXI Master WindowsX_2) and bits [31:0] (MSB of Base address AXI Master WindowsX_3).

Slave Interface
If you select PCIe or PCIe Reverse Protocol the Slave Interface tab enables you to configure up to four PCI windows, Window 0 through Window 3, with the following parameters (as shown in Figure 1-4 on page 13):

• Size
• Local Address
• PCIe Address
• Traffic Class: Selects the PCIe Traffic Class in the PCIe packet header.
• Relaxed Ordering: Enables you to generate the PCIe TLP using a selectable relaxed ordering bit.
• No Snoop: Enables you to generate the PCIe TLP using a selectable no snoop bit.

The Size, Local Address and PCIe Address options are the same as those for Master Interface. Refer to “Master Interface” on page 11 for more information.

Traffic Class
Traffic Class enables you to set your Traffic Class and corresponding register bits, as shown in Table 1-4. The Traffic Class value determines the relative priority of a given transaction as it traverses the PCIe link. Use this value to create a priority scheme for different packets.

• TC 0 (Default)
• TC 1
• TC 2
• TC 3
• TC 4
• TC 5
• TC 6
• TC 7

Table 1-4 • Traffic Class and Corresponding Bit Setting

Lane Configuration
Use Lane Configuration to configure up to four lanes for your SERDES. The SERDES can be configured to run in dual-protocol mode. Refer to Table 1-1 on page 7 for lane configuration for dual mode operation.

Speed – Available selections depend on your selected Protocol. Refer to Table 1-1 on page 7 for the valid Speeds and available Protocols.

Reference Clock Source – Two clock sources are available: REFCLK0 and REFCLK1. Each can be differential or single-ended. You can select one of the following options for Protocol 1 and Protocol 2:

• REFCLK0 (Differential),
• REFCLK1 (Differential),
• REFCLK0 (Single-Ended),
• REFCLK1 (Single-Ended)
• Fabric (Available only for the EPCS Protocol)

Note: Lane 0 and Lane 1 share the same Reference Clock and Lane 2 and Lane 3 share the same Reference Clock. The selected Reference Clock is always available as REFCLK0_OUT or REFCLK1_OUT and can be used as clock source for logic inside Fabric.

PHY RefClk Frequency (MHz) – This is a fixed value for all protocols except EPCS Custom Speed in which case you can enter values between 100 and 160 MHz.

Data Rate (Mbps) – Read-only fixed value for all protocols except EPCS Custom Speed, in which case you can select the data rate from the drop-down list. Data Rates are computed based on the PHY RefClk Frequency.

Data Width – Read-only fixed value for all protocols except EPCS Custom Speed. For EPCS, the data width varies with Data Rate (Mbps) as follows:

• 20 bit (for 5000 Mbps and 2500 Mbps)
• 16 bit (for 4000 Mbps or 2000 Mbps)
• 10 bit (2500 Mbps or 1250 Mbps)
• 8 bit (for 2000 Mbps or 1000 Mbps)
• 5 bit for 1250 Mbps
• 4 bit (for 1000 Mbps)

The displayed value is computed and updated based on your selected PHY RefClk Frequency and Data Rate.

FPGA Interface Frequency (MHz) – Read-only fixed value for all protocols except EPCS Custom Speed, the displayed value is computed and updated based on the PHY RefClk Frequency and Data Rate you select.

VCO Rate (MHz) – Read-only fixed value for all protocols except EPCS Custom Speed. The displayed value is computed and updated based on the PHY RefClk Frequency and Data Rate you select.

PCIe/XAUI Fabric SPLL Configuration
The SPLL configuration fields are relevant only for PCIe and XAUI protocols (Figure 1-5). For the PCIe protocol, enter a valid value between 20 and 200 MHz for the CLK_BASE Frequency.
For the XAUI protocol, the CLK_BASE Frequency is read-only and fixed at 156.25 MHz.

Signal Integrity Options
For the XAUI and EPCS protocols, click Signal Integrity Options to open the Signal Integrity Configuration dialog box.

The Signal Integrity Configuration dialog box gives you controls to maintain signal integrity and to mitigate signal integrity problems.

Transmit De-Emphasis
Enter any value between 0.0 & 36.1 (in dB) in the Required edit box for both Pre-Transmit and Post- Transmit stage. Not all values are supported. Refer to Table 1-5 for all Actual values supported. The value you enter in the Required box will be matched to the closest valid Actual value and reported in the Actual box. The Configurator sets appropriate values for LANE_TX_PRE_RATIO and LANE_TX_PST_RATIO registers based on the Actual value.
LANE_TX_PRE_RATIO and LANE_TX_PST_RATIO registers are set based on the Actual value, as shown in Figure 1-5. The default value for Required is 0 for Pre-Transmit and 3.5 for Post-Transmit.
The LANE _TX_AMP_RATIO lane register is always set to 0x80 for all lanes.

Table 1-5 • EPCS/XAUI Signal Integrity Configuration—Transmit De-Emphasis

Feature| Control Registers| Actual Value=value programmed in register|
---|---|---|---
De-Emphasis Pre| LANE_TX_PRE_RATIO| 0dB = 0x0

0.1dB = 0x1

|
| | 0.3dB = 0x2|
0.4dB = 0x3

0.5dB = 0x4

0.7dB = 0x5

|
De-Emphasis Post| LANE_TX_PST_RATIO|
| | 0.9dB = 0x6|
| | 1dB = 0x7|
| | 1.2dB = 0x8|
| | 1.3dB = 0x9|
| | 1.5dB = 0xa|
| | 1.6dB = 0xb|
| | 1.8dB = 0xc|
| | 2dB = 0xd|
| | 2.1dB = 0xe|
| | 2.3dB = 0xf|
| | 2.5dB = 0x10|
| | 2.7dB = 0x11|
| | 2.9dB = 0x12|
| | 3dB = 0x13|
| | 3.3dB = 0x14|
| | 3.5dB = 0x15|
| | 3.7dB = 0x16|
| | 3.9dB = 0x17|
| | 4dB = 0x18|
| | 4.3dB = 0x19|
| | 4.5dB = 0x1a|
| | 4.8dB = 0x1b|
| | 5dB = 0x1c|
| | 5.2dB = 0x1d|
| | 5.5dB = 0x1e|
| | 5.8dB = 0x1f|
| | 6dB = 0x20|
| | 6.3dB = 0x21|
| | 6.5dB = 0x22|
| | 7dB = 0x23|
| | 7.2dB = 0x24|
| | 7.5dB = 0x25|
| | 7.8dB = 0x26|
| | 8dB = 0x27|
| | 8.5dB = 0x28|
| | 9dB = 0x29|
| | 9.3dB = 0x2a|
| | 9.7dB = 0x2b|
| | 10.1dB = 0x2c|
| | 10.5dB = 0x2d|
| | 11dB = 0x2e|
| | 11.5dB = 0x2f|
| | 12dB = 0x30|
| | 12.6dB = 0x31|
| | 13.2dB = 0x32|
| | 13.8dB = 0x33|
| | 14.5dB = 0x34|
| | 15.2dB = 0x35|
| | 16.1dB = 0x36|
| | 17dB = 0x37|
| | 18dB = 0x38|
| | 19.2dB = 0x39|
| | 20.5dB = 0x3a|
| | 22.1dB = 0x3b|
| | 24dB = 0x3c|
| | 26.5dB = 0x3d|
| | 30.1dB = 0x3e|
| | 36.1dB = 0x3f|

Note: LANE denotes the lane number where can be 0, 1, 2 or 3.

For example, if you enter 2.4 dB in the Required box, 2.5dB (the closest match) is displayed in the Actual box and the registers are set as follows:

1. LANE_TX_PRE_RATIO registers are set to 0x10
2. LANE_TX_PST_RATIO registers are set to 0x10
3. LANE_TX_AMP_RATIO registers are set to 0x80.

Receive CTL Equalization
There are 14 predefined settings available for user selection. Each predefined setting has the corresponding Cut-Off Frequency and Low Frequency Amplitude values preset and displayed when the predefined setting is selected. The impedance value for all predefined settings is 100 Ohms. Depending on the predefined setting, lane registers LANE_RE_AMP_RATIO and LANE_RE_CUT_RATIO are set to the values listed in Table 1-6.

Table 1-6 • CTL Equalization Predefined Settings and Register Values

Pre-defined Setting #| Cut-Off Frequency (MHz)| Low Frequency Amplitude (dB)| LANE _REAMP **RATIO (HEX)| LANE _RECUT **RATIO (HEX)
---|---|---|---|---
1| 400| 10.88| 0x77| 0x20
2| 500| 13.06| 0x5B| 0x2A
3| 600| 13.98| 0x51| 0x2F
4| 700| 12.04| 0x4A| 0x32
5| 800| 13.38| 0x3E| 0x3C
6| 900| 13.98| 0x39| 0x40
7| 1000| 12.57| 0x70| 0x4F
8| 1100| 11.6| 0x7D| 0x58
9| 1200| 10.88| 0x37| 0xFE
10| 1300| 9.95| 0x22| 0xFC
11| 1400| 8.52| 0x52| 0xFE
12| 1500| 7.47| 0x5B| 0xFE
13| 1600| 7.04| 0x73| 0xFE
14| 1700| 6.66| 0x78| 0xFE

Note: LANE denotes the lane number where can be 0, 1, 2, or 3.

Power Down Register Settings
This controls the Physical Reset behavior of the EPCS SERDES when there is a lack of RX activity.

• Enabled (Physical Reset behavior is enabled)
• Disabled (Physical Reset behavior is disabled)

High Speed Serial Interface Control Registers
The High Speed Serial Interface has a set of registers that can be configured at runtime. The configuration values for these registers represent different parameters, for example, AXI BAR Window. For details about these registers, refer to the Microsemi UG0447: SmartFusion2 or IGLOO2 High Speed Serial Interfaces User’s Guide.

High Speed Serial Interface Registers Configuration
To enter the High Speed Serial Interface configuration values, specify the register values when you are configuring the High Speed Serial Interface. Click Edit Registers in the High Speed Serial Interface Configurator (Figure 3 on page 4) to open the Registers Configuration dialog box (Figure 1-8). Data entered in this configurator is written at power up in the High Speed Serial Interface registers as described in the SmartFusion2 DDR Controller and Serial High Speed Controller Initialization Methodology document.

Alternatively, you can click the Import Configuration button and import an existing configuration text file to configure the Registers.

The Registers Configuration dialog box enables you to enter High Speed Serial Interface register values using a graphical interface. The dialog box has the following features:

• Registers Table – Enter register values one-by-one using the Registers Table. To enter a register value, expand the register data tree (using the arrow sign), and click the Actual Value column to edit.
• Import Configuration – Import complete register configurations from text files. Register configuration syntax is shown below; Microsemi recommends using this method.
• Export Configuration – You can export the current register configuration data into a text file. The syntax of the exported file is the same as that of importable register configuration text files. For example:

• Reset Configuration – Click Reset Configuration to undo any changes you have made to the register configuration. This deletes all register configuration data and you must either re-import or reenter this data. The data is reset to the hardware reset values.
• Hide Read-Only Registers – Enables you to show or hide the read-only registers in the Register Table. These registers are mostly status registers and do not contribute to the configuration.

When you generate your FPGA, the configuration register data entered in this configurator is used to initialize the High Speed Serial Interface simulation model when performing a BFM simulation.

Firmware (SmartFusion2 Only)

When you generate the SmartDesign, the following files are generated in the