Microsemi UG0944 Histogram User Guide
- June 6, 2024
- Microsemi
Table of Contents
UG0944 Histogram
User Guide
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Revision History
The revision history describes the changes that were implemented in the
document. The changes are listed by revision, starting with the most current
publication.
Revision 1.0
The first publication of this document.
Introduction
The histogram is traditionally used to show a set of data graphically. In the
video and image processing domain, the histogram is used to visualize the
distribution of pixel intensities in an image or a video frame. For an image
with an 8-bit wide pixel, 256 intensity values are possible ranging from 0 to
255. The histogram will show how many times a pixel of particular intensity
occurs in the entire image. Histograms are useful to understand the exposure
and light distribution of the image and possibly correct it in image
processing. One way of correcting the histogram of an image is by using
intensity curves. The curve is adjusted through an interactive graphical
interface such that the histogram has the pixel intensities spread over the
entire range. The Histogram IP provides data that can be used to plot the
histogram and can also correct the pixel intensity distribution from user
inputs. The histogram IP takes video frames as input and generates a plot of
intensities of all the pixels in one frame. The histogram IP computes the
histogram data and also corrects the intensity of DATA_Y_I input. The Cb_I and
Cr_I are passed through the IP with one cycle delay. The IP can be used to
plot luma intensity or R, G, B intensity by using three instances of the IP.
In the case of IP is being used for R, G, B, the inputs Cb and Cr can be left
unused. The histogram IP starts taking pixels with the start of the video
frame and continues till the end of the frame. During each pixel, the logic
inside the IP keeps track of previous pixels with the same intensity and
increments by one. The histogram IP can be used to see effects of changes in
brightness, contrast, and color balance in the image.
Histogram memory: FPGA LSRAM is used to store the pixel intensities. With
every incoming pixel, the corresponding RAM address content is incremented by
one. This process is followed till the end of the frame. This way the RAM
addresses become pixel intensities and content becomes a number of times it
occurs in one frame. Histogram memory is 24 bits wide and 256 addresses deep.
The histogram is computed for 1 out of every 4 frames. For the remaining 3
frames, the histogram data is held constant, and it can be read by the user.
The HIST_RDY_O output is held high for 3 frames, during which the user can
read the histogram data on the CURVE_RDATA_O output signal using HIST_ADDR_I
as the address for pixel intensity.
Curve memory: FPGA LSRAM is used to store correction factors for each
intensity value. By default, it has linear numbers 0 to 255 initially. The
curve memory has a RAM write interface from where these values can be
reprogrammed at run time. Curve memory is 8 bits wide and 256 addresses deep.
Key Features
- Histogram plotting of real-time video
- Curve based correction of live video
Supported Families
- PolarFire® SoC
- PolarFire®
- RTG4TM
- IGLOO®2
- SmartFusion®2
Inputs and Outputs
Figure 1 · Histogram IP Block Diagram
**The following table lists the input and output ports of the Histogram IP.
Table 1 · Input and Output Ports**
| Port Name | Direction | Width | Description |
|---|---|---|---|
| SYS CLK | Input | 1 bit | System Clock. This must be the same as the pixel clock. |
| RESET I | Input | 1 bit | Active low asynchronous reset signal to design |
| DATA VALID I | Input | 1 bit | Input Data Valid Signal. This signal should be |
asserted when the data is valid.
DATA Y I| Input| 8 bits| Input video data intensity
EOF I| Input| 1 bit| Input video frame end
HIST_ADDR_I| Input| 8 bits| Histogram memory read address for reading
histogram plot data
HIST RDY 0| Output| 1 bit| Ready indication when histogram memory can be read
HIST DATA 0| Output| 24 bits| Histogram memory data which is the number of
pixels of intensity represented by the HIST_ADDR_I
CURVE WE I| Input| 8 bits| Curve memory write enable
CURVE WADDR I| Input| 8 bits| Curve memory write address
CURVE WDATA I| Input| 8 bits| Curve memory write data
Cb I| Input| 8 bits| Chroma value for blue color
Cr_I| Input| 8 bits| Chroma value for red color
Y 0| Output| 8 bits| Output intensity after curve correction
Cb 0| Output| 8 bits| Output for Cb_l with one clock cycle delay
Cr_O| Output| 8 bits| Output for Cr_I with one clock cycle delay
Configuration Parameters
There are no configuration parameters for this IP.
License
Histogram IP clear RTL is license locked and the obfuscated RTL is available
for free.
Obfuscated
Complete RTL code is provided for the core, allowing the core to be
instantiated with the SmartDesign tool. Simulation, synthesis, and layout can
be performed within Libero® System-on-Chip (SoC). The RTL code for the core is
obfuscated.
RTL
Complete RTL source code is provided for the core.
Microsemi Proprietary UG0944 Revision 1.0
Histogram Plot
Using video control GUI, the following plot was observed for a 1920X1080 input
image.
Figure 2 · Histogram Plot
Resource Utilization
Histogram IP is implemented on PolarFire FPGA (MPF300TS -1FCG1152I package).
The following table shows the resource utilization report after synthesis.
Table 2 · Resource Utilization
| Resource | Usage |
|---|---|
| DFFs | 29 |
| 4LUTs | 88 |
| LSRAM18K | 2 |
| MACC | 0 |
Testbench
A testbench signal generator hist_stimulus is provided to check the
functionality of the histogram IP. This stimulus must be imported into the
testbench to ensure histogram functionality.
The following steps describe how to simulate the core using the testbench.
-
In the Design Flow window, expand Create Design. Right-click Create SmartDesign and click Run, as shown in the following figure.
Figure 3 ·Create New Smart Design smart design is created, and a canvas appears to the right of the Design Flow pane. -
In the Libero, tool menu go to File -> Import -> HDL Source Files. The hist_ip.vhd, hist_stimulus.vhd, and ram2port.vhd files have to be imported into the project.
Figure 4 • Import HDL Source Files -
Click Build Hierarchy in the leftmost pane in the Libero.
-
Go to the Design Hierarchy tab and drag hit_ip and hist_stimulus in the SmartDesign area of the histogram_simulation.
-
Connect hist_ip and hist_stimulus blocks, as shown in the following figure.
Figure 5 • Testbench Figure 5 · Connect hist_ip and hist_stimulus blocks
-
Click Generate Component and Build Hierarchy.
-
Go to design hierarchy, right-click on the histogram_simulation, and select Set As Root.
Figure 6 · Design Hierarchy
-
Create a testbench with the name hist_tb.
Figure 7 · Create testbench
-
Save the project and click Build Hierarchy.
-
Promote the histogram_simulation ports to the top level.
Figure 8 · Histogram Simulation
-
Click Generate Component.
-
On the Stimulus Hierarchy tab, right-click the hist_tb testbench file and click Open Interactively from Simulate Pre-Synth Design.
Figure 9 · Stimulus Hierarchy
The ModelSim tool appears with the testbench file loaded onto it, as shown in
the following figure.
If the simulation is interrupted because of the runtime limit in the DO file,
use the run -all command to complete the simulation.
Figure 10 · Simulation Result
Microsemi Proprietary UG0944 Revision 1.0
References
Read User Manual Online (PDF format)
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