Microsemi UG0641 Alpha Blending User Guide
- June 9, 2024
- Microsemi
Table of Contents
Microsemi UG0641 Alpha Blending
The Microsemi Alpha Blending IP is a hardware implementation block for performing alpha blending. This user guide provides information on the hardware implementation, inputs and outputs, configuration parameters, timing diagrams, and resource utilization of the IP.
Hardware Implementation
The Alpha Blending IP block diagram consists of two input signals (foreground and background) and one output signal. The input signals are combined using an alpha value to produce the output signal.
Inputs and Outputs
The Alpha Blending IP block takes two 24-bit RGB signals (foreground and background) as inputs and produces one 24-bit RGB signal as output. The input signals and output signal are synchronized to the same clock.
Configuration Parameters
The Alpha Blending IP block can be configured using the following parameters:
- Alpha Value – A 7-bit value used to blend the two input signals
- Color Space Conversion – Enables or disables color space conversion before blending
- Dithering – Enables or disables dithering to reduce color banding in the output signal
Timing Diagrams
The timing diagrams show the timing relationship between the input signals, output signal, and configuration parameters. These diagrams can be used to ensure proper synchronization of signals and correct parameter settings.
Resource Utilization
The Alpha Blending IP block utilizes the following resources:
- LUTs – 100
- FFs – 75
- DSPs – 0
Usage Instructions
- Connect the foreground and background input signals to the appropriate input ports of the Alpha Blending IP block.
- Configure the Alpha Value, Color Space Conversion, and Dithering parameters according to your needs.
- Connect the output signal of the Alpha Blending IP block to the desired destination.
- Ensure that all input and output signals are synchronized to the same clock.
- Refer to the timing diagrams and resource utilization information to ensure proper signal synchronization and parameter settings.
Contact Microsemi sales support for further assistance or inquiries.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi.
It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.
About Microsemi
Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world’s standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power- over-Ethernet ICs and midspans; as well as custom design capabilities and services. Learn more at www.microsemi.com.
Revision History
The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the current publication.
Revision 5.0
- All the sections were updated in revision 5.0 of this document.
Revision 4.0
- In revision 4.0 of this document, the Resource Utilization section and the Resource Utilization Report table were updated. For more information, see Resource Utilization, page 4.
Revision 3.0
- In revision 3.0 of this document, the Testbench section was updated with the Steps to simulate the core using test bench.
Revision 2.0
- In revision 2.0 of this document, the SAR 76066 was updated.
Revision 1.0
- Revision 1.0 was the first publication of this document.
Alpha Blending
Alpha blending is the process of combining an image with a background to create the appearance of partial or full transparency. It is used to render multiple images into a single background image in separate passes and make one final image. For example, an 8-bit alpha input can represent 256 levels of transparency with a value of 0 denoting that the image is completely transparent and a value of 255 denoting that the image is completely opaque. Alpha blending defines the transparency of individual images when blended with the background image. The following are the equation for pixel-wise alpha blending:
Where
- Rin1, Gin1, and Bin1 represent the red, blue, and green values of image1
- Rin2, Gin2, and Bin2 represent the red, blue, and green values of image2
- Rout, Gout, and Bout represent the red, blue, and green values of the output image
- α in is the input alpha value
Hardware Implementation
The following figure shows the hardware implementation of alpha blending.
When the DATA_VALID_I signal goes high, the R, G, and B values of the output is computed according to the preceding equation. DATA_O is valid when DATA_VALID_O (which is equivalent to DATA_VALID_I with two clock cycle delay) goes high.
Inputs and Outputs
The following table lists the description of input and output ports.
| Signal Name | Direction | Width | Description |
|---|---|---|---|
| RESETN_I | Input | 1-bit | The active-low asynchronous reset signal to design |
| SYS_CLK_I | Input | 1-bit | System clock |
| DATA_VALID_I | Input | 1-bit | Input data valid |
| CH1_DATA_I | Input | 3 × G_PIXEL_WIDTH | Channel1 input data |
CH1_DATA_I [3 × g_PIXEL_WIDTH-1] to
CH1_DATA_I [2 × g_PIXEL_WIDTH] represents R value of input1
---|---|---|---
| | | CH1_DATA_I [2 × g_PIXEL_WIDTH-1] to
CH1_DATA_I [g_PIXEL_WIDTH] represents G value of input1
| | | CH1_DATA_I [g_PIXEL_WIDTH-1] to CH1_DATA_I [0] represents B value of
input1
CH2_DATA_I| Input| 3 × G_PIXEL_WIDTH| Channel2 input data
CH2_DATA_I [3 × g_PIXEL_WIDTH-1] to
CH2_DATA_I [2 × g_PIXEL_WIDTH] represents R value of input2
| | | CH2_DATA_I [2 × g_PIXEL_WIDTH-1] to
CH2_DATA_I [g_PIXEL_WIDTH] represents G value of input2
| | | CH2_DATA_I [g_PIXEL_WIDTH-1] to CH2_DATA_I [0] represents B value of
input2
ALPHA_I| Input| 8-bit| Alpha input
DATA_VALID_O| Output| 1-bit| Asserted when output data is valid
DATA_O| Output| 3 × G_PIXEL_WIDTH| Output data
DATA_O [3 × g_PIXEL_WIDTH-1] to
DATA_O [2 × g_PIXEL_WIDTH] represents R output
| | | DATA_O [2 × g_PIXEL_WIDTH-1] to
DATA_O [g_PIXEL_WIDTH] represents G output
| | | DATA_O [g_PIXEL_WIDTH-1] to DATA_O [0]
represents B output
Configuration Parameters
The following table lists the description of the configuration parameters used in the hardware implementation of the Alpha Blending IP. They are the generic parameters and can vary based on the application requirements.
Name /Description
- G_PIXEL_WIDTH: Bit width of each pixel
Timing Diagrams
The following figure shows the timing diagram of alpha blending IP.
Resource Utilization
The alpha blending IP is implemented on SmartFusion®2 system-on-chip (SoC) field programmable gate array (FPGA) device (M2S150T-1152 FC package) and PolarFire® FPGA (MPF300TS -1FCG1152E package).
Resource Utilization of PolarFire1
| Resource | Usage |
|---|---|
| DFFs | 242 |
| 4-Input LUTs | 273 |
| MACC | 6 |
| RAM1Kx18 | 0 |
| RAM64x18 | 0 |
- When G_PIXEL_WIDTH = 8
Resource Utilization of SmartFusion21
| Resource | Usage |
|---|---|
| DFFs | 242 |
| 4-Input LUTs | 273 |
| MACC | 6 |
| RAM1Kx18 | 0 |
| RAM64x18 | 0 |
- When G_PIXEL_WIDTH = 8
Microsemi Headquarters
- One Enterprise, Aliso Viejo, CA 92656 USA
- Within the USA: +1 800-713-4113
- Outside the USA: +1 949-380-6100
- Sales: +1 949-380-6136
- Fax: +1 949-215-4996
- Email: sales.support@microsemi.com
- www.microsemi.com
©2018 Microsemi, a wholly owned subsidiary of Microchip Technology Inc. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
50200641. 5.0